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hw: add compat machines for 6.1
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "exec/address-spaces.h"
69 #include "sysemu/arch_init.h"
70 #include "qemu/bitmap.h"
71 #include "qemu/config-file.h"
72 #include "qemu/error-report.h"
73 #include "qemu/option.h"
74 #include "qemu/cutils.h"
75 #include "hw/acpi/acpi.h"
76 #include "hw/acpi/cpu_hotplug.h"
77 #include "hw/boards.h"
78 #include "acpi-build.h"
79 #include "hw/mem/pc-dimm.h"
80 #include "hw/mem/nvdimm.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/visitor.h"
84 #include "hw/core/cpu.h"
85 #include "hw/usb.h"
86 #include "hw/i386/intel_iommu.h"
87 #include "hw/net/ne2000-isa.h"
88 #include "standard-headers/asm-x86/bootparam.h"
89 #include "hw/virtio/virtio-pmem-pci.h"
90 #include "hw/virtio/virtio-mem-pci.h"
91 #include "hw/mem/memory-device.h"
92 #include "sysemu/replay.h"
93 #include "qapi/qmp/qerror.h"
94 #include "e820_memory_layout.h"
95 #include "fw_cfg.h"
96 #include "trace.h"
97 #include CONFIG_DEVICES
98
99 GlobalProperty pc_compat_6_0[] = {};
100 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
101
102 GlobalProperty pc_compat_5_2[] = {
103 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
104 };
105 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
106
107 GlobalProperty pc_compat_5_1[] = {
108 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
109 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
110 };
111 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
112
113 GlobalProperty pc_compat_5_0[] = {
114 };
115 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
116
117 GlobalProperty pc_compat_4_2[] = {
118 { "mch", "smbase-smram", "off" },
119 };
120 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
121
122 GlobalProperty pc_compat_4_1[] = {};
123 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
124
125 GlobalProperty pc_compat_4_0[] = {};
126 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
127
128 GlobalProperty pc_compat_3_1[] = {
129 { "intel-iommu", "dma-drain", "off" },
130 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
131 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
132 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
133 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
134 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
135 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
136 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
137 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
138 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
139 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
140 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
141 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
142 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
143 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
144 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
146 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
147 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
148 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
149 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
150 };
151 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
152
153 GlobalProperty pc_compat_3_0[] = {
154 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
155 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
156 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
157 };
158 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
159
160 GlobalProperty pc_compat_2_12[] = {
161 { TYPE_X86_CPU, "legacy-cache", "on" },
162 { TYPE_X86_CPU, "topoext", "off" },
163 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
164 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
165 };
166 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
167
168 GlobalProperty pc_compat_2_11[] = {
169 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
170 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
171 };
172 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
173
174 GlobalProperty pc_compat_2_10[] = {
175 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
176 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
177 { "q35-pcihost", "x-pci-hole64-fix", "off" },
178 };
179 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
180
181 GlobalProperty pc_compat_2_9[] = {
182 { "mch", "extended-tseg-mbytes", "0" },
183 };
184 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
185
186 GlobalProperty pc_compat_2_8[] = {
187 { TYPE_X86_CPU, "tcg-cpuid", "off" },
188 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
189 { "ICH9-LPC", "x-smi-broadcast", "off" },
190 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
191 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
192 };
193 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
194
195 GlobalProperty pc_compat_2_7[] = {
196 { TYPE_X86_CPU, "l3-cache", "off" },
197 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
198 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
199 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
200 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
201 { "isa-pcspk", "migrate", "off" },
202 };
203 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
204
205 GlobalProperty pc_compat_2_6[] = {
206 { TYPE_X86_CPU, "cpuid-0xb", "off" },
207 { "vmxnet3", "romfile", "" },
208 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
209 { "apic-common", "legacy-instance-id", "on", }
210 };
211 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
212
213 GlobalProperty pc_compat_2_5[] = {};
214 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
215
216 GlobalProperty pc_compat_2_4[] = {
217 PC_CPU_MODEL_IDS("2.4.0")
218 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
219 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
220 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
221 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
222 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
223 { TYPE_X86_CPU, "check", "off" },
224 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
225 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
226 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
227 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
228 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
229 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
230 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
231 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
232 };
233 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
234
235 GlobalProperty pc_compat_2_3[] = {
236 PC_CPU_MODEL_IDS("2.3.0")
237 { TYPE_X86_CPU, "arat", "off" },
238 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
239 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
240 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
241 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
242 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
243 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
244 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
245 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
247 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
249 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
250 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
251 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
252 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
253 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
254 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
255 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
256 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
257 };
258 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
259
260 GlobalProperty pc_compat_2_2[] = {
261 PC_CPU_MODEL_IDS("2.2.0")
262 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
263 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
265 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
268 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
269 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
270 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
271 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
272 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
273 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
274 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
275 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
276 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
277 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
278 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
279 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
280 };
281 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
282
283 GlobalProperty pc_compat_2_1[] = {
284 PC_CPU_MODEL_IDS("2.1.0")
285 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
286 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
287 };
288 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
289
290 GlobalProperty pc_compat_2_0[] = {
291 PC_CPU_MODEL_IDS("2.0.0")
292 { "virtio-scsi-pci", "any_layout", "off" },
293 { "PIIX4_PM", "memory-hotplug-support", "off" },
294 { "apic", "version", "0x11" },
295 { "nec-usb-xhci", "superspeed-ports-first", "off" },
296 { "nec-usb-xhci", "force-pcie-endcap", "on" },
297 { "pci-serial", "prog_if", "0" },
298 { "pci-serial-2x", "prog_if", "0" },
299 { "pci-serial-4x", "prog_if", "0" },
300 { "virtio-net-pci", "guest_announce", "off" },
301 { "ICH9-LPC", "memory-hotplug-support", "off" },
302 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
303 { "ioh3420", COMPAT_PROP_PCP, "off" },
304 };
305 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
306
307 GlobalProperty pc_compat_1_7[] = {
308 PC_CPU_MODEL_IDS("1.7.0")
309 { TYPE_USB_DEVICE, "msos-desc", "no" },
310 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
311 { "hpet", HPET_INTCAP, "4" },
312 };
313 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
314
315 GlobalProperty pc_compat_1_6[] = {
316 PC_CPU_MODEL_IDS("1.6.0")
317 { "e1000", "mitigation", "off" },
318 { "qemu64-" TYPE_X86_CPU, "model", "2" },
319 { "qemu32-" TYPE_X86_CPU, "model", "3" },
320 { "i440FX-pcihost", "short_root_bus", "1" },
321 { "q35-pcihost", "short_root_bus", "1" },
322 };
323 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
324
325 GlobalProperty pc_compat_1_5[] = {
326 PC_CPU_MODEL_IDS("1.5.0")
327 { "Conroe-" TYPE_X86_CPU, "model", "2" },
328 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
329 { "Penryn-" TYPE_X86_CPU, "model", "2" },
330 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
331 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
332 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
333 { "virtio-net-pci", "any_layout", "off" },
334 { TYPE_X86_CPU, "pmu", "on" },
335 { "i440FX-pcihost", "short_root_bus", "0" },
336 { "q35-pcihost", "short_root_bus", "0" },
337 };
338 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
339
340 GlobalProperty pc_compat_1_4[] = {
341 PC_CPU_MODEL_IDS("1.4.0")
342 { "scsi-hd", "discard_granularity", "0" },
343 { "scsi-cd", "discard_granularity", "0" },
344 { "ide-hd", "discard_granularity", "0" },
345 { "ide-cd", "discard_granularity", "0" },
346 { "virtio-blk-pci", "discard_granularity", "0" },
347 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
348 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
349 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
350 { "e1000", "romfile", "pxe-e1000.rom" },
351 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
352 { "pcnet", "romfile", "pxe-pcnet.rom" },
353 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
354 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
355 { "486-" TYPE_X86_CPU, "model", "0" },
356 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
357 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
358 };
359 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
360
361 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
362 {
363 GSIState *s;
364
365 s = g_new0(GSIState, 1);
366 if (kvm_ioapic_in_kernel()) {
367 kvm_pc_setup_irq_routing(pci_enabled);
368 }
369 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
370
371 return s;
372 }
373
374 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
375 unsigned size)
376 {
377 }
378
379 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
380 {
381 return 0xffffffffffffffffULL;
382 }
383
384 /* MSDOS compatibility mode FPU exception support */
385 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
386 unsigned size)
387 {
388 if (tcg_enabled()) {
389 cpu_set_ignne();
390 }
391 }
392
393 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
394 {
395 return 0xffffffffffffffffULL;
396 }
397
398 /* PC cmos mappings */
399
400 #define REG_EQUIPMENT_BYTE 0x14
401
402 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
403 int16_t cylinders, int8_t heads, int8_t sectors)
404 {
405 rtc_set_memory(s, type_ofs, 47);
406 rtc_set_memory(s, info_ofs, cylinders);
407 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
408 rtc_set_memory(s, info_ofs + 2, heads);
409 rtc_set_memory(s, info_ofs + 3, 0xff);
410 rtc_set_memory(s, info_ofs + 4, 0xff);
411 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
412 rtc_set_memory(s, info_ofs + 6, cylinders);
413 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
414 rtc_set_memory(s, info_ofs + 8, sectors);
415 }
416
417 /* convert boot_device letter to something recognizable by the bios */
418 static int boot_device2nibble(char boot_device)
419 {
420 switch(boot_device) {
421 case 'a':
422 case 'b':
423 return 0x01; /* floppy boot */
424 case 'c':
425 return 0x02; /* hard drive boot */
426 case 'd':
427 return 0x03; /* CD-ROM boot */
428 case 'n':
429 return 0x04; /* Network boot */
430 }
431 return 0;
432 }
433
434 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
435 {
436 #define PC_MAX_BOOT_DEVICES 3
437 int nbds, bds[3] = { 0, };
438 int i;
439
440 nbds = strlen(boot_device);
441 if (nbds > PC_MAX_BOOT_DEVICES) {
442 error_setg(errp, "Too many boot devices for PC");
443 return;
444 }
445 for (i = 0; i < nbds; i++) {
446 bds[i] = boot_device2nibble(boot_device[i]);
447 if (bds[i] == 0) {
448 error_setg(errp, "Invalid boot device for PC: '%c'",
449 boot_device[i]);
450 return;
451 }
452 }
453 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
454 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
455 }
456
457 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
458 {
459 set_boot_dev(opaque, boot_device, errp);
460 }
461
462 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
463 {
464 int val, nb, i;
465 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
466 FLOPPY_DRIVE_TYPE_NONE };
467
468 /* floppy type */
469 if (floppy) {
470 for (i = 0; i < 2; i++) {
471 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
472 }
473 }
474 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
475 cmos_get_fd_drive_type(fd_type[1]);
476 rtc_set_memory(rtc_state, 0x10, val);
477
478 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
479 nb = 0;
480 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
481 nb++;
482 }
483 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
484 nb++;
485 }
486 switch (nb) {
487 case 0:
488 break;
489 case 1:
490 val |= 0x01; /* 1 drive, ready for boot */
491 break;
492 case 2:
493 val |= 0x41; /* 2 drives, ready for boot */
494 break;
495 }
496 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
497 }
498
499 typedef struct pc_cmos_init_late_arg {
500 ISADevice *rtc_state;
501 BusState *idebus[2];
502 } pc_cmos_init_late_arg;
503
504 typedef struct check_fdc_state {
505 ISADevice *floppy;
506 bool multiple;
507 } CheckFdcState;
508
509 static int check_fdc(Object *obj, void *opaque)
510 {
511 CheckFdcState *state = opaque;
512 Object *fdc;
513 uint32_t iobase;
514 Error *local_err = NULL;
515
516 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
517 if (!fdc) {
518 return 0;
519 }
520
521 iobase = object_property_get_uint(obj, "iobase", &local_err);
522 if (local_err || iobase != 0x3f0) {
523 error_free(local_err);
524 return 0;
525 }
526
527 if (state->floppy) {
528 state->multiple = true;
529 } else {
530 state->floppy = ISA_DEVICE(obj);
531 }
532 return 0;
533 }
534
535 static const char * const fdc_container_path[] = {
536 "/unattached", "/peripheral", "/peripheral-anon"
537 };
538
539 /*
540 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
541 * and ACPI objects.
542 */
543 ISADevice *pc_find_fdc0(void)
544 {
545 int i;
546 Object *container;
547 CheckFdcState state = { 0 };
548
549 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
550 container = container_get(qdev_get_machine(), fdc_container_path[i]);
551 object_child_foreach(container, check_fdc, &state);
552 }
553
554 if (state.multiple) {
555 warn_report("multiple floppy disk controllers with "
556 "iobase=0x3f0 have been found");
557 error_printf("the one being picked for CMOS setup might not reflect "
558 "your intent");
559 }
560
561 return state.floppy;
562 }
563
564 static void pc_cmos_init_late(void *opaque)
565 {
566 pc_cmos_init_late_arg *arg = opaque;
567 ISADevice *s = arg->rtc_state;
568 int16_t cylinders;
569 int8_t heads, sectors;
570 int val;
571 int i, trans;
572
573 val = 0;
574 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
575 &cylinders, &heads, &sectors) >= 0) {
576 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
577 val |= 0xf0;
578 }
579 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
580 &cylinders, &heads, &sectors) >= 0) {
581 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
582 val |= 0x0f;
583 }
584 rtc_set_memory(s, 0x12, val);
585
586 val = 0;
587 for (i = 0; i < 4; i++) {
588 /* NOTE: ide_get_geometry() returns the physical
589 geometry. It is always such that: 1 <= sects <= 63, 1
590 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
591 geometry can be different if a translation is done. */
592 if (arg->idebus[i / 2] &&
593 ide_get_geometry(arg->idebus[i / 2], i % 2,
594 &cylinders, &heads, &sectors) >= 0) {
595 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
596 assert((trans & ~3) == 0);
597 val |= trans << (i * 2);
598 }
599 }
600 rtc_set_memory(s, 0x39, val);
601
602 pc_cmos_init_floppy(s, pc_find_fdc0());
603
604 qemu_unregister_reset(pc_cmos_init_late, opaque);
605 }
606
607 void pc_cmos_init(PCMachineState *pcms,
608 BusState *idebus0, BusState *idebus1,
609 ISADevice *s)
610 {
611 int val;
612 static pc_cmos_init_late_arg arg;
613 X86MachineState *x86ms = X86_MACHINE(pcms);
614
615 /* various important CMOS locations needed by PC/Bochs bios */
616
617 /* memory size */
618 /* base memory (first MiB) */
619 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
620 rtc_set_memory(s, 0x15, val);
621 rtc_set_memory(s, 0x16, val >> 8);
622 /* extended memory (next 64MiB) */
623 if (x86ms->below_4g_mem_size > 1 * MiB) {
624 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
625 } else {
626 val = 0;
627 }
628 if (val > 65535)
629 val = 65535;
630 rtc_set_memory(s, 0x17, val);
631 rtc_set_memory(s, 0x18, val >> 8);
632 rtc_set_memory(s, 0x30, val);
633 rtc_set_memory(s, 0x31, val >> 8);
634 /* memory between 16MiB and 4GiB */
635 if (x86ms->below_4g_mem_size > 16 * MiB) {
636 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
637 } else {
638 val = 0;
639 }
640 if (val > 65535)
641 val = 65535;
642 rtc_set_memory(s, 0x34, val);
643 rtc_set_memory(s, 0x35, val >> 8);
644 /* memory above 4GiB */
645 val = x86ms->above_4g_mem_size / 65536;
646 rtc_set_memory(s, 0x5b, val);
647 rtc_set_memory(s, 0x5c, val >> 8);
648 rtc_set_memory(s, 0x5d, val >> 16);
649
650 object_property_add_link(OBJECT(pcms), "rtc_state",
651 TYPE_ISA_DEVICE,
652 (Object **)&x86ms->rtc,
653 object_property_allow_set_link,
654 OBJ_PROP_LINK_STRONG);
655 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
656 &error_abort);
657
658 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
659
660 val = 0;
661 val |= 0x02; /* FPU is there */
662 val |= 0x04; /* PS/2 mouse installed */
663 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
664
665 /* hard drives and FDC */
666 arg.rtc_state = s;
667 arg.idebus[0] = idebus0;
668 arg.idebus[1] = idebus1;
669 qemu_register_reset(pc_cmos_init_late, &arg);
670 }
671
672 static void handle_a20_line_change(void *opaque, int irq, int level)
673 {
674 X86CPU *cpu = opaque;
675
676 /* XXX: send to all CPUs ? */
677 /* XXX: add logic to handle multiple A20 line sources */
678 x86_cpu_set_a20(cpu, level);
679 }
680
681 #define NE2000_NB_MAX 6
682
683 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
684 0x280, 0x380 };
685 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
686
687 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
688 {
689 static int nb_ne2k = 0;
690
691 if (nb_ne2k == NE2000_NB_MAX)
692 return;
693 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
694 ne2000_irq[nb_ne2k], nd);
695 nb_ne2k++;
696 }
697
698 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
699 {
700 X86CPU *cpu = opaque;
701
702 if (level) {
703 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
704 }
705 }
706
707 /*
708 * This function is very similar to smp_parse()
709 * in hw/core/machine.c but includes CPU die support.
710 */
711 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
712 {
713 X86MachineState *x86ms = X86_MACHINE(ms);
714
715 if (opts) {
716 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
717 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
718 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
719 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
720 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
721
722 /* compute missing values, prefer sockets over cores over threads */
723 if (cpus == 0 || sockets == 0) {
724 cores = cores > 0 ? cores : 1;
725 threads = threads > 0 ? threads : 1;
726 if (cpus == 0) {
727 sockets = sockets > 0 ? sockets : 1;
728 cpus = cores * threads * dies * sockets;
729 } else {
730 ms->smp.max_cpus =
731 qemu_opt_get_number(opts, "maxcpus", cpus);
732 sockets = ms->smp.max_cpus / (cores * threads * dies);
733 }
734 } else if (cores == 0) {
735 threads = threads > 0 ? threads : 1;
736 cores = cpus / (sockets * dies * threads);
737 cores = cores > 0 ? cores : 1;
738 } else if (threads == 0) {
739 threads = cpus / (cores * dies * sockets);
740 threads = threads > 0 ? threads : 1;
741 } else if (sockets * dies * cores * threads < cpus) {
742 error_report("cpu topology: "
743 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
744 "smp_cpus (%u)",
745 sockets, dies, cores, threads, cpus);
746 exit(1);
747 }
748
749 ms->smp.max_cpus =
750 qemu_opt_get_number(opts, "maxcpus", cpus);
751
752 if (ms->smp.max_cpus < cpus) {
753 error_report("maxcpus must be equal to or greater than smp");
754 exit(1);
755 }
756
757 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
758 error_report("Invalid CPU topology deprecated: "
759 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
760 "!= maxcpus (%u)",
761 sockets, dies, cores, threads,
762 ms->smp.max_cpus);
763 exit(1);
764 }
765
766 ms->smp.cpus = cpus;
767 ms->smp.cores = cores;
768 ms->smp.threads = threads;
769 ms->smp.sockets = sockets;
770 x86ms->smp_dies = dies;
771 }
772
773 if (ms->smp.cpus > 1) {
774 Error *blocker = NULL;
775 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
776 replay_add_blocker(blocker);
777 }
778 }
779
780 static
781 void pc_machine_done(Notifier *notifier, void *data)
782 {
783 PCMachineState *pcms = container_of(notifier,
784 PCMachineState, machine_done);
785 X86MachineState *x86ms = X86_MACHINE(pcms);
786
787 /* set the number of CPUs */
788 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
789
790 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
791
792 acpi_setup();
793 if (x86ms->fw_cfg) {
794 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
795 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
796 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
797 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
798 }
799
800
801 if (x86ms->apic_id_limit > 255 && !xen_enabled() &&
802 !kvm_irqchip_in_kernel()) {
803 error_report("current -smp configuration requires kernel "
804 "irqchip support.");
805 exit(EXIT_FAILURE);
806 }
807 }
808
809 void pc_guest_info_init(PCMachineState *pcms)
810 {
811 int i;
812 MachineState *ms = MACHINE(pcms);
813 X86MachineState *x86ms = X86_MACHINE(pcms);
814
815 x86ms->apic_xrupt_override = true;
816 pcms->numa_nodes = ms->numa_state->num_nodes;
817 pcms->node_mem = g_malloc0(pcms->numa_nodes *
818 sizeof *pcms->node_mem);
819 for (i = 0; i < ms->numa_state->num_nodes; i++) {
820 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
821 }
822
823 pcms->machine_done.notify = pc_machine_done;
824 qemu_add_machine_init_done_notifier(&pcms->machine_done);
825 }
826
827 /* setup pci memory address space mapping into system address space */
828 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
829 MemoryRegion *pci_address_space)
830 {
831 /* Set to lower priority than RAM */
832 memory_region_add_subregion_overlap(system_memory, 0x0,
833 pci_address_space, -1);
834 }
835
836 void xen_load_linux(PCMachineState *pcms)
837 {
838 int i;
839 FWCfgState *fw_cfg;
840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
841 X86MachineState *x86ms = X86_MACHINE(pcms);
842
843 assert(MACHINE(pcms)->kernel_filename != NULL);
844
845 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
846 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
847 rom_set_fw(fw_cfg);
848
849 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
850 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
851 for (i = 0; i < nb_option_roms; i++) {
852 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
853 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
854 !strcmp(option_rom[i].name, "pvh.bin") ||
855 !strcmp(option_rom[i].name, "multiboot.bin"));
856 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
857 }
858 x86ms->fw_cfg = fw_cfg;
859 }
860
861 void pc_memory_init(PCMachineState *pcms,
862 MemoryRegion *system_memory,
863 MemoryRegion *rom_memory,
864 MemoryRegion **ram_memory)
865 {
866 int linux_boot, i;
867 MemoryRegion *option_rom_mr;
868 MemoryRegion *ram_below_4g, *ram_above_4g;
869 FWCfgState *fw_cfg;
870 MachineState *machine = MACHINE(pcms);
871 MachineClass *mc = MACHINE_GET_CLASS(machine);
872 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
873 X86MachineState *x86ms = X86_MACHINE(pcms);
874
875 assert(machine->ram_size == x86ms->below_4g_mem_size +
876 x86ms->above_4g_mem_size);
877
878 linux_boot = (machine->kernel_filename != NULL);
879
880 /*
881 * Split single memory region and use aliases to address portions of it,
882 * done for backwards compatibility with older qemus.
883 */
884 *ram_memory = machine->ram;
885 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
886 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
887 0, x86ms->below_4g_mem_size);
888 memory_region_add_subregion(system_memory, 0, ram_below_4g);
889 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
890 if (x86ms->above_4g_mem_size > 0) {
891 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
892 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
893 machine->ram,
894 x86ms->below_4g_mem_size,
895 x86ms->above_4g_mem_size);
896 memory_region_add_subregion(system_memory, 0x100000000ULL,
897 ram_above_4g);
898 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
899 }
900
901 if (!pcmc->has_reserved_memory &&
902 (machine->ram_slots ||
903 (machine->maxram_size > machine->ram_size))) {
904
905 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
906 mc->name);
907 exit(EXIT_FAILURE);
908 }
909
910 /* always allocate the device memory information */
911 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
912
913 /* initialize device memory address space */
914 if (pcmc->has_reserved_memory &&
915 (machine->ram_size < machine->maxram_size)) {
916 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
917
918 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
919 error_report("unsupported amount of memory slots: %"PRIu64,
920 machine->ram_slots);
921 exit(EXIT_FAILURE);
922 }
923
924 if (QEMU_ALIGN_UP(machine->maxram_size,
925 TARGET_PAGE_SIZE) != machine->maxram_size) {
926 error_report("maximum memory size must by aligned to multiple of "
927 "%d bytes", TARGET_PAGE_SIZE);
928 exit(EXIT_FAILURE);
929 }
930
931 machine->device_memory->base =
932 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
933
934 if (pcmc->enforce_aligned_dimm) {
935 /* size device region assuming 1G page max alignment per slot */
936 device_mem_size += (1 * GiB) * machine->ram_slots;
937 }
938
939 if ((machine->device_memory->base + device_mem_size) <
940 device_mem_size) {
941 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
942 machine->maxram_size);
943 exit(EXIT_FAILURE);
944 }
945
946 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
947 "device-memory", device_mem_size);
948 memory_region_add_subregion(system_memory, machine->device_memory->base,
949 &machine->device_memory->mr);
950 }
951
952 /* Initialize PC system firmware */
953 pc_system_firmware_init(pcms, rom_memory);
954
955 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
956 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
957 &error_fatal);
958 if (pcmc->pci_enabled) {
959 memory_region_set_readonly(option_rom_mr, true);
960 }
961 memory_region_add_subregion_overlap(rom_memory,
962 PC_ROM_MIN_VGA,
963 option_rom_mr,
964 1);
965
966 fw_cfg = fw_cfg_arch_create(machine,
967 x86ms->boot_cpus, x86ms->apic_id_limit);
968
969 rom_set_fw(fw_cfg);
970
971 if (pcmc->has_reserved_memory && machine->device_memory->base) {
972 uint64_t *val = g_malloc(sizeof(*val));
973 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
974 uint64_t res_mem_end = machine->device_memory->base;
975
976 if (!pcmc->broken_reserved_end) {
977 res_mem_end += memory_region_size(&machine->device_memory->mr);
978 }
979 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
980 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
981 }
982
983 if (linux_boot) {
984 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
985 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
986 }
987
988 for (i = 0; i < nb_option_roms; i++) {
989 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
990 }
991 x86ms->fw_cfg = fw_cfg;
992
993 /* Init default IOAPIC address space */
994 x86ms->ioapic_as = &address_space_memory;
995
996 /* Init ACPI memory hotplug IO base address */
997 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
998 }
999
1000 /*
1001 * The 64bit pci hole starts after "above 4G RAM" and
1002 * potentially the space reserved for memory hotplug.
1003 */
1004 uint64_t pc_pci_hole64_start(void)
1005 {
1006 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1007 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1008 MachineState *ms = MACHINE(pcms);
1009 X86MachineState *x86ms = X86_MACHINE(pcms);
1010 uint64_t hole64_start = 0;
1011
1012 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1013 hole64_start = ms->device_memory->base;
1014 if (!pcmc->broken_reserved_end) {
1015 hole64_start += memory_region_size(&ms->device_memory->mr);
1016 }
1017 } else {
1018 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1019 }
1020
1021 return ROUND_UP(hole64_start, 1 * GiB);
1022 }
1023
1024 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1025 {
1026 DeviceState *dev = NULL;
1027
1028 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1029 if (pci_bus) {
1030 PCIDevice *pcidev = pci_vga_init(pci_bus);
1031 dev = pcidev ? &pcidev->qdev : NULL;
1032 } else if (isa_bus) {
1033 ISADevice *isadev = isa_vga_init(isa_bus);
1034 dev = isadev ? DEVICE(isadev) : NULL;
1035 }
1036 rom_reset_order_override();
1037 return dev;
1038 }
1039
1040 static const MemoryRegionOps ioport80_io_ops = {
1041 .write = ioport80_write,
1042 .read = ioport80_read,
1043 .endianness = DEVICE_NATIVE_ENDIAN,
1044 .impl = {
1045 .min_access_size = 1,
1046 .max_access_size = 1,
1047 },
1048 };
1049
1050 static const MemoryRegionOps ioportF0_io_ops = {
1051 .write = ioportF0_write,
1052 .read = ioportF0_read,
1053 .endianness = DEVICE_NATIVE_ENDIAN,
1054 .impl = {
1055 .min_access_size = 1,
1056 .max_access_size = 1,
1057 },
1058 };
1059
1060 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1061 {
1062 int i;
1063 DriveInfo *fd[MAX_FD];
1064 qemu_irq *a20_line;
1065 ISADevice *fdc, *i8042, *port92, *vmmouse;
1066
1067 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1068 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1069
1070 for (i = 0; i < MAX_FD; i++) {
1071 fd[i] = drive_get(IF_FLOPPY, 0, i);
1072 create_fdctrl |= !!fd[i];
1073 }
1074 if (create_fdctrl) {
1075 fdc = isa_new(TYPE_ISA_FDC);
1076 if (fdc) {
1077 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1078 isa_fdc_init_drives(fdc, fd);
1079 }
1080 }
1081
1082 i8042 = isa_create_simple(isa_bus, "i8042");
1083 if (!no_vmport) {
1084 isa_create_simple(isa_bus, TYPE_VMPORT);
1085 vmmouse = isa_try_new("vmmouse");
1086 } else {
1087 vmmouse = NULL;
1088 }
1089 if (vmmouse) {
1090 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1091 &error_abort);
1092 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1093 }
1094 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1095
1096 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1097 i8042_setup_a20_line(i8042, a20_line[0]);
1098 qdev_connect_gpio_out_named(DEVICE(port92),
1099 PORT92_A20_LINE, 0, a20_line[1]);
1100 g_free(a20_line);
1101 }
1102
1103 void pc_basic_device_init(struct PCMachineState *pcms,
1104 ISABus *isa_bus, qemu_irq *gsi,
1105 ISADevice **rtc_state,
1106 bool create_fdctrl,
1107 uint32_t hpet_irqs)
1108 {
1109 int i;
1110 DeviceState *hpet = NULL;
1111 int pit_isa_irq = 0;
1112 qemu_irq pit_alt_irq = NULL;
1113 qemu_irq rtc_irq = NULL;
1114 ISADevice *pit = NULL;
1115 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1116 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1117
1118 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1119 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1120
1121 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1122 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1123
1124 /*
1125 * Check if an HPET shall be created.
1126 *
1127 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1128 * when the HPET wants to take over. Thus we have to disable the latter.
1129 */
1130 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1131 kvm_has_pit_state2())) {
1132 hpet = qdev_try_new(TYPE_HPET);
1133 if (!hpet) {
1134 error_report("couldn't create HPET device");
1135 exit(1);
1136 }
1137 /*
1138 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1139 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1140 * IRQ2.
1141 */
1142 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1143 HPET_INTCAP, NULL);
1144 if (!compat) {
1145 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1146 }
1147 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1148 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1149
1150 for (i = 0; i < GSI_NUM_PINS; i++) {
1151 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1152 }
1153 pit_isa_irq = -1;
1154 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1155 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1156 }
1157 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1158
1159 qemu_register_boot_set(pc_boot_set, *rtc_state);
1160
1161 if (!xen_enabled() && pcms->pit_enabled) {
1162 if (kvm_pit_in_kernel()) {
1163 pit = kvm_pit_init(isa_bus, 0x40);
1164 } else {
1165 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1166 }
1167 if (hpet) {
1168 /* connect PIT to output control line of the HPET */
1169 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1170 }
1171 pcspk_init(pcms->pcspk, isa_bus, pit);
1172 }
1173
1174 i8257_dma_init(isa_bus, 0);
1175
1176 /* Super I/O */
1177 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
1178 }
1179
1180 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1181 {
1182 int i;
1183
1184 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1185 for (i = 0; i < nb_nics; i++) {
1186 NICInfo *nd = &nd_table[i];
1187 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1188
1189 if (g_str_equal(model, "ne2k_isa")) {
1190 pc_init_ne2k_isa(isa_bus, nd);
1191 } else {
1192 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1193 }
1194 }
1195 rom_reset_order_override();
1196 }
1197
1198 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1199 {
1200 qemu_irq *i8259;
1201
1202 if (kvm_pic_in_kernel()) {
1203 i8259 = kvm_i8259_init(isa_bus);
1204 } else if (xen_enabled()) {
1205 i8259 = xen_interrupt_controller_init();
1206 } else {
1207 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1208 }
1209
1210 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1211 i8259_irqs[i] = i8259[i];
1212 }
1213
1214 g_free(i8259);
1215 }
1216
1217 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1218 Error **errp)
1219 {
1220 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1221 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1222 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1223 const MachineState *ms = MACHINE(hotplug_dev);
1224 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1225 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1226 Error *local_err = NULL;
1227
1228 /*
1229 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1230 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1231 * addition to cover this case.
1232 */
1233 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1234 error_setg(errp,
1235 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1236 return;
1237 }
1238
1239 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1240 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1241 return;
1242 }
1243
1244 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1245 if (local_err) {
1246 error_propagate(errp, local_err);
1247 return;
1248 }
1249
1250 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1251 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1252 }
1253
1254 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1255 DeviceState *dev, Error **errp)
1256 {
1257 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1258 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1259 MachineState *ms = MACHINE(hotplug_dev);
1260 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1261
1262 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1263
1264 if (is_nvdimm) {
1265 nvdimm_plug(ms->nvdimms_state);
1266 }
1267
1268 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1269 }
1270
1271 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1272 DeviceState *dev, Error **errp)
1273 {
1274 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1275
1276 /*
1277 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1278 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1279 * addition to cover this case.
1280 */
1281 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1282 error_setg(errp,
1283 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1284 return;
1285 }
1286
1287 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1288 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1289 return;
1290 }
1291
1292 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1293 errp);
1294 }
1295
1296 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1297 DeviceState *dev, Error **errp)
1298 {
1299 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1300 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1301 Error *local_err = NULL;
1302
1303 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1304 if (local_err) {
1305 goto out;
1306 }
1307
1308 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1309 qdev_unrealize(dev);
1310 out:
1311 error_propagate(errp, local_err);
1312 }
1313
1314 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1315 DeviceState *dev, Error **errp)
1316 {
1317 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1318 Error *local_err = NULL;
1319
1320 if (!hotplug_dev2 && dev->hotplugged) {
1321 /*
1322 * Without a bus hotplug handler, we cannot control the plug/unplug
1323 * order. We should never reach this point when hotplugging on x86,
1324 * however, better add a safety net.
1325 */
1326 error_setg(errp, "hotplug of virtio based memory devices not supported"
1327 " on this bus.");
1328 return;
1329 }
1330 /*
1331 * First, see if we can plug this memory device at all. If that
1332 * succeeds, branch of to the actual hotplug handler.
1333 */
1334 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1335 &local_err);
1336 if (!local_err && hotplug_dev2) {
1337 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1338 }
1339 error_propagate(errp, local_err);
1340 }
1341
1342 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1343 DeviceState *dev, Error **errp)
1344 {
1345 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1346 Error *local_err = NULL;
1347
1348 /*
1349 * Plug the memory device first and then branch off to the actual
1350 * hotplug handler. If that one fails, we can easily undo the memory
1351 * device bits.
1352 */
1353 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1354 if (hotplug_dev2) {
1355 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1356 if (local_err) {
1357 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1358 }
1359 }
1360 error_propagate(errp, local_err);
1361 }
1362
1363 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1364 DeviceState *dev, Error **errp)
1365 {
1366 /* We don't support hot unplug of virtio based memory devices */
1367 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1368 }
1369
1370 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1371 DeviceState *dev, Error **errp)
1372 {
1373 /* We don't support hot unplug of virtio based memory devices */
1374 }
1375
1376 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1377 DeviceState *dev, Error **errp)
1378 {
1379 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1380 pc_memory_pre_plug(hotplug_dev, dev, errp);
1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1382 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1383 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1384 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1385 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1386 }
1387 }
1388
1389 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1390 DeviceState *dev, Error **errp)
1391 {
1392 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1393 pc_memory_plug(hotplug_dev, dev, errp);
1394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1395 x86_cpu_plug(hotplug_dev, dev, errp);
1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1397 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1398 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1399 }
1400 }
1401
1402 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1403 DeviceState *dev, Error **errp)
1404 {
1405 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1406 pc_memory_unplug_request(hotplug_dev, dev, errp);
1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1408 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1410 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1411 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1412 } else {
1413 error_setg(errp, "acpi: device unplug request for not supported device"
1414 " type: %s", object_get_typename(OBJECT(dev)));
1415 }
1416 }
1417
1418 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1419 DeviceState *dev, Error **errp)
1420 {
1421 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1422 pc_memory_unplug(hotplug_dev, dev, errp);
1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1424 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1426 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1427 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1428 } else {
1429 error_setg(errp, "acpi: device unplug for not supported device"
1430 " type: %s", object_get_typename(OBJECT(dev)));
1431 }
1432 }
1433
1434 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1435 DeviceState *dev)
1436 {
1437 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1438 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1439 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1440 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1441 return HOTPLUG_HANDLER(machine);
1442 }
1443
1444 return NULL;
1445 }
1446
1447 static void
1448 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1449 const char *name, void *opaque,
1450 Error **errp)
1451 {
1452 MachineState *ms = MACHINE(obj);
1453 int64_t value = 0;
1454
1455 if (ms->device_memory) {
1456 value = memory_region_size(&ms->device_memory->mr);
1457 }
1458
1459 visit_type_int(v, name, &value, errp);
1460 }
1461
1462 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1463 void *opaque, Error **errp)
1464 {
1465 PCMachineState *pcms = PC_MACHINE(obj);
1466 OnOffAuto vmport = pcms->vmport;
1467
1468 visit_type_OnOffAuto(v, name, &vmport, errp);
1469 }
1470
1471 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1472 void *opaque, Error **errp)
1473 {
1474 PCMachineState *pcms = PC_MACHINE(obj);
1475
1476 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1477 }
1478
1479 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1480 {
1481 PCMachineState *pcms = PC_MACHINE(obj);
1482
1483 return pcms->smbus_enabled;
1484 }
1485
1486 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1487 {
1488 PCMachineState *pcms = PC_MACHINE(obj);
1489
1490 pcms->smbus_enabled = value;
1491 }
1492
1493 static bool pc_machine_get_sata(Object *obj, Error **errp)
1494 {
1495 PCMachineState *pcms = PC_MACHINE(obj);
1496
1497 return pcms->sata_enabled;
1498 }
1499
1500 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1501 {
1502 PCMachineState *pcms = PC_MACHINE(obj);
1503
1504 pcms->sata_enabled = value;
1505 }
1506
1507 static bool pc_machine_get_pit(Object *obj, Error **errp)
1508 {
1509 PCMachineState *pcms = PC_MACHINE(obj);
1510
1511 return pcms->pit_enabled;
1512 }
1513
1514 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1515 {
1516 PCMachineState *pcms = PC_MACHINE(obj);
1517
1518 pcms->pit_enabled = value;
1519 }
1520
1521 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1522 {
1523 PCMachineState *pcms = PC_MACHINE(obj);
1524
1525 return pcms->hpet_enabled;
1526 }
1527
1528 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1529 {
1530 PCMachineState *pcms = PC_MACHINE(obj);
1531
1532 pcms->hpet_enabled = value;
1533 }
1534
1535 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1536 const char *name, void *opaque,
1537 Error **errp)
1538 {
1539 PCMachineState *pcms = PC_MACHINE(obj);
1540 uint64_t value = pcms->max_ram_below_4g;
1541
1542 visit_type_size(v, name, &value, errp);
1543 }
1544
1545 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1546 const char *name, void *opaque,
1547 Error **errp)
1548 {
1549 PCMachineState *pcms = PC_MACHINE(obj);
1550 uint64_t value;
1551
1552 if (!visit_type_size(v, name, &value, errp)) {
1553 return;
1554 }
1555 if (value > 4 * GiB) {
1556 error_setg(errp,
1557 "Machine option 'max-ram-below-4g=%"PRIu64
1558 "' expects size less than or equal to 4G", value);
1559 return;
1560 }
1561
1562 if (value < 1 * MiB) {
1563 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1564 "BIOS may not work with less than 1MiB", value);
1565 }
1566
1567 pcms->max_ram_below_4g = value;
1568 }
1569
1570 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1571 const char *name, void *opaque,
1572 Error **errp)
1573 {
1574 PCMachineState *pcms = PC_MACHINE(obj);
1575 uint64_t value = pcms->max_fw_size;
1576
1577 visit_type_size(v, name, &value, errp);
1578 }
1579
1580 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1581 const char *name, void *opaque,
1582 Error **errp)
1583 {
1584 PCMachineState *pcms = PC_MACHINE(obj);
1585 Error *error = NULL;
1586 uint64_t value;
1587
1588 visit_type_size(v, name, &value, &error);
1589 if (error) {
1590 error_propagate(errp, error);
1591 return;
1592 }
1593
1594 /*
1595 * We don't have a theoretically justifiable exact lower bound on the base
1596 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1597 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1598 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1599 * size.
1600 */
1601 if (value > 16 * MiB) {
1602 error_setg(errp,
1603 "User specified max allowed firmware size %" PRIu64 " is "
1604 "greater than 16MiB. If combined firwmare size exceeds "
1605 "16MiB the system may not boot, or experience intermittent"
1606 "stability issues.",
1607 value);
1608 return;
1609 }
1610
1611 pcms->max_fw_size = value;
1612 }
1613
1614
1615 static void pc_machine_initfn(Object *obj)
1616 {
1617 PCMachineState *pcms = PC_MACHINE(obj);
1618
1619 #ifdef CONFIG_VMPORT
1620 pcms->vmport = ON_OFF_AUTO_AUTO;
1621 #else
1622 pcms->vmport = ON_OFF_AUTO_OFF;
1623 #endif /* CONFIG_VMPORT */
1624 pcms->max_ram_below_4g = 0; /* use default */
1625 /* acpi build is enabled by default if machine supports it */
1626 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1627 pcms->smbus_enabled = true;
1628 pcms->sata_enabled = true;
1629 pcms->pit_enabled = true;
1630 pcms->max_fw_size = 8 * MiB;
1631 #ifdef CONFIG_HPET
1632 pcms->hpet_enabled = true;
1633 #endif
1634
1635 pc_system_flash_create(pcms);
1636 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1637 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1638 OBJECT(pcms->pcspk), "audiodev");
1639 }
1640
1641 static void pc_machine_reset(MachineState *machine)
1642 {
1643 CPUState *cs;
1644 X86CPU *cpu;
1645
1646 qemu_devices_reset();
1647
1648 /* Reset APIC after devices have been reset to cancel
1649 * any changes that qemu_devices_reset() might have done.
1650 */
1651 CPU_FOREACH(cs) {
1652 cpu = X86_CPU(cs);
1653
1654 if (cpu->apic_state) {
1655 device_legacy_reset(cpu->apic_state);
1656 }
1657 }
1658 }
1659
1660 static void pc_machine_wakeup(MachineState *machine)
1661 {
1662 cpu_synchronize_all_states();
1663 pc_machine_reset(machine);
1664 cpu_synchronize_all_post_reset();
1665 }
1666
1667 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1668 {
1669 X86IOMMUState *iommu = x86_iommu_get_default();
1670 IntelIOMMUState *intel_iommu;
1671
1672 if (iommu &&
1673 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1674 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1675 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1676 if (!intel_iommu->caching_mode) {
1677 error_setg(errp, "Device assignment is not allowed without "
1678 "enabling caching-mode=on for Intel IOMMU.");
1679 return false;
1680 }
1681 }
1682
1683 return true;
1684 }
1685
1686 static void pc_machine_class_init(ObjectClass *oc, void *data)
1687 {
1688 MachineClass *mc = MACHINE_CLASS(oc);
1689 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1690 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1691
1692 pcmc->pci_enabled = true;
1693 pcmc->has_acpi_build = true;
1694 pcmc->rsdp_in_ram = true;
1695 pcmc->smbios_defaults = true;
1696 pcmc->smbios_uuid_encoded = true;
1697 pcmc->gigabyte_align = true;
1698 pcmc->has_reserved_memory = true;
1699 pcmc->kvmclock_enabled = true;
1700 pcmc->enforce_aligned_dimm = true;
1701 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1702 * to be used at the moment, 32K should be enough for a while. */
1703 pcmc->acpi_data_size = 0x20000 + 0x8000;
1704 pcmc->linuxboot_dma_enabled = true;
1705 pcmc->pvh_enabled = true;
1706 pcmc->kvmclock_create_always = true;
1707 assert(!mc->get_hotplug_handler);
1708 mc->get_hotplug_handler = pc_get_hotplug_handler;
1709 mc->hotplug_allowed = pc_hotplug_allowed;
1710 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1711 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1712 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1713 mc->auto_enable_numa_with_memhp = true;
1714 mc->auto_enable_numa_with_memdev = true;
1715 mc->has_hotpluggable_cpus = true;
1716 mc->default_boot_order = "cad";
1717 mc->smp_parse = pc_smp_parse;
1718 mc->block_default_type = IF_IDE;
1719 mc->max_cpus = 255;
1720 mc->reset = pc_machine_reset;
1721 mc->wakeup = pc_machine_wakeup;
1722 hc->pre_plug = pc_machine_device_pre_plug_cb;
1723 hc->plug = pc_machine_device_plug_cb;
1724 hc->unplug_request = pc_machine_device_unplug_request_cb;
1725 hc->unplug = pc_machine_device_unplug_cb;
1726 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1727 mc->nvdimm_supported = true;
1728 mc->default_ram_id = "pc.ram";
1729
1730 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1731 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1732 NULL, NULL);
1733 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1734 "Maximum ram below the 4G boundary (32bit boundary)");
1735
1736 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1737 pc_machine_get_device_memory_region_size, NULL,
1738 NULL, NULL);
1739
1740 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1741 pc_machine_get_vmport, pc_machine_set_vmport,
1742 NULL, NULL);
1743 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1744 "Enable vmport (pc & q35)");
1745
1746 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1747 pc_machine_get_smbus, pc_machine_set_smbus);
1748
1749 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1750 pc_machine_get_sata, pc_machine_set_sata);
1751
1752 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1753 pc_machine_get_pit, pc_machine_set_pit);
1754
1755 object_class_property_add_bool(oc, "hpet",
1756 pc_machine_get_hpet, pc_machine_set_hpet);
1757
1758 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1759 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1760 NULL, NULL);
1761 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1762 "Maximum combined firmware size");
1763 }
1764
1765 static const TypeInfo pc_machine_info = {
1766 .name = TYPE_PC_MACHINE,
1767 .parent = TYPE_X86_MACHINE,
1768 .abstract = true,
1769 .instance_size = sizeof(PCMachineState),
1770 .instance_init = pc_machine_initfn,
1771 .class_size = sizeof(PCMachineClass),
1772 .class_init = pc_machine_class_init,
1773 .interfaces = (InterfaceInfo[]) {
1774 { TYPE_HOTPLUG_HANDLER },
1775 { }
1776 },
1777 };
1778
1779 static void pc_machine_register_types(void)
1780 {
1781 type_register_static(&pc_machine_info);
1782 }
1783
1784 type_init(pc_machine_register_types)
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