hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/char/serial.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/block/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "hw/timer/hpet.h"
  34 #include "hw/i386/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "hw/timer/mc146818rtc.h"
  39 #include "hw/timer/i8254.h"
  40 #include "hw/audio/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block/block.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54 #include "qemu/config-file.h"
  55 #include "hw/acpi/acpi.h"
  56 #include "hw/cpu/icc_bus.h"
  57 #include "hw/boards.h"
  58
  59 /* debug PC/ISA interrupts */
  60 //#define DEBUG_IRQ
  61
  62 #ifdef DEBUG_IRQ
  63 #define DPRINTF(fmt, ...)                                       \
  64     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  65 #else
  66 #define DPRINTF(fmt, ...)
  67 #endif
  68
  69 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  70 #define ACPI_DATA_SIZE       0x10000
  71 #define BIOS_CFG_IOPORT 0x510
  72 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  73 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  74 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  75 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  76 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  77
  78 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000
  79
  80 #define E820_NR_ENTRIES         16
  81
  82 struct e820_entry {
  83     uint64_t address;
  84     uint64_t length;
  85     uint32_t type;
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 struct e820_table {
  89     uint32_t count;
  90     struct e820_entry entry[E820_NR_ENTRIES];
  91 } QEMU_PACKED __attribute((__aligned__(4)));
  92
  93 static struct e820_table e820_table;
  94 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  95
  96 void gsi_handler(void *opaque, int n, int level)
  97 {
  98     GSIState *s = opaque;
  99
 100     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 101     if (n < ISA_NUM_IRQS) {
 102         qemu_set_irq(s->i8259_irq[n], level);
 103     }
 104     qemu_set_irq(s->ioapic_irq[n], level);
 105 }
 106
 107 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 108                            unsigned size)
 109 {
 110 }
 111
 112 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 113 {
 114     return 0xffffffffffffffffULL;
 115 }
 116
 117 /* MSDOS compatibility mode FPU exception support */
 118 static qemu_irq ferr_irq;
 119
 120 void pc_register_ferr_irq(qemu_irq irq)
 121 {
 122     ferr_irq = irq;
 123 }
 124
 125 /* XXX: add IGNNE support */
 126 void cpu_set_ferr(CPUX86State *s)
 127 {
 128     qemu_irq_raise(ferr_irq);
 129 }
 130
 131 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 132                            unsigned size)
 133 {
 134     qemu_irq_lower(ferr_irq);
 135 }
 136
 137 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 138 {
 139     return 0xffffffffffffffffULL;
 140 }
 141
 142 /* TSC handling */
 143 uint64_t cpu_get_tsc(CPUX86State *env)
 144 {
 145     return cpu_get_ticks();
 146 }
 147
 148 /* SMM support */
 149
 150 static cpu_set_smm_t smm_set;
 151 static void *smm_arg;
 152
 153 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 154 {
 155     assert(smm_set == NULL);
 156     assert(smm_arg == NULL);
 157     smm_set = callback;
 158     smm_arg = arg;
 159 }
 160
 161 void cpu_smm_update(CPUX86State *env)
 162 {
 163     if (smm_set && smm_arg && env == first_cpu)
 164         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 165 }
 166
 167
 168 /* IRQ handling */
 169 int cpu_get_pic_interrupt(CPUX86State *env)
 170 {
 171     int intno;
 172
 173     intno = apic_get_interrupt(env->apic_state);
 174     if (intno >= 0) {
 175         return intno;
 176     }
 177     /* read the irq from the PIC */
 178     if (!apic_accept_pic_intr(env->apic_state)) {
 179         return -1;
 180     }
 181
 182     intno = pic_read_irq(isa_pic);
 183     return intno;
 184 }
 185
 186 static void pic_irq_request(void *opaque, int irq, int level)
 187 {
 188     CPUX86State *env = first_cpu;
 189
 190     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 191     if (env->apic_state) {
 192         while (env) {
 193             if (apic_accept_pic_intr(env->apic_state)) {
 194                 apic_deliver_pic_intr(env->apic_state, level);
 195             }
 196             env = env->next_cpu;
 197         }
 198     } else {
 199         CPUState *cs = CPU(x86_env_get_cpu(env));
 200         if (level) {
 201             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 202         } else {
 203             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 204         }
 205     }
 206 }
 207
 208 /* PC cmos mappings */
 209
 210 #define REG_EQUIPMENT_BYTE          0x14
 211
 212 static int cmos_get_fd_drive_type(FDriveType fd0)
 213 {
 214     int val;
 215
 216     switch (fd0) {
 217     case FDRIVE_DRV_144:
 218         /* 1.44 Mb 3"5 drive */
 219         val = 4;
 220         break;
 221     case FDRIVE_DRV_288:
 222         /* 2.88 Mb 3"5 drive */
 223         val = 5;
 224         break;
 225     case FDRIVE_DRV_120:
 226         /* 1.2 Mb 5"5 drive */
 227         val = 2;
 228         break;
 229     case FDRIVE_DRV_NONE:
 230     default:
 231         val = 0;
 232         break;
 233     }
 234     return val;
 235 }
 236
 237 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 238                          int16_t cylinders, int8_t heads, int8_t sectors)
 239 {
 240     rtc_set_memory(s, type_ofs, 47);
 241     rtc_set_memory(s, info_ofs, cylinders);
 242     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 243     rtc_set_memory(s, info_ofs + 2, heads);
 244     rtc_set_memory(s, info_ofs + 3, 0xff);
 245     rtc_set_memory(s, info_ofs + 4, 0xff);
 246     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 247     rtc_set_memory(s, info_ofs + 6, cylinders);
 248     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 249     rtc_set_memory(s, info_ofs + 8, sectors);
 250 }
 251
 252 /* convert boot_device letter to something recognizable by the bios */
 253 static int boot_device2nibble(char boot_device)
 254 {
 255     switch(boot_device) {
 256     case 'a':
 257     case 'b':
 258         return 0x01; /* floppy boot */
 259     case 'c':
 260         return 0x02; /* hard drive boot */
 261     case 'd':
 262         return 0x03; /* CD-ROM boot */
 263     case 'n':
 264         return 0x04; /* Network boot */
 265     }
 266     return 0;
 267 }
 268
 269 static int set_boot_dev(ISADevice *s, const char *boot_device)
 270 {
 271 #define PC_MAX_BOOT_DEVICES 3
 272     int nbds, bds[3] = { 0, };
 273     int i;
 274
 275     nbds = strlen(boot_device);
 276     if (nbds > PC_MAX_BOOT_DEVICES) {
 277         error_report("Too many boot devices for PC");
 278         return(1);
 279     }
 280     for (i = 0; i < nbds; i++) {
 281         bds[i] = boot_device2nibble(boot_device[i]);
 282         if (bds[i] == 0) {
 283             error_report("Invalid boot device for PC: '%c'",
 284                          boot_device[i]);
 285             return(1);
 286         }
 287     }
 288     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 289     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 290     return(0);
 291 }
 292
 293 static int pc_boot_set(void *opaque, const char *boot_device)
 294 {
 295     return set_boot_dev(opaque, boot_device);
 296 }
 297
 298 typedef struct pc_cmos_init_late_arg {
 299     ISADevice *rtc_state;
 300     BusState *idebus[2];
 301 } pc_cmos_init_late_arg;
 302
 303 static void pc_cmos_init_late(void *opaque)
 304 {
 305     pc_cmos_init_late_arg *arg = opaque;
 306     ISADevice *s = arg->rtc_state;
 307     int16_t cylinders;
 308     int8_t heads, sectors;
 309     int val;
 310     int i, trans;
 311
 312     val = 0;
 313     if (ide_get_geometry(arg->idebus[0], 0,
 314                          &cylinders, &heads, &sectors) >= 0) {
 315         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 316         val |= 0xf0;
 317     }
 318     if (ide_get_geometry(arg->idebus[0], 1,
 319                          &cylinders, &heads, &sectors) >= 0) {
 320         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 321         val |= 0x0f;
 322     }
 323     rtc_set_memory(s, 0x12, val);
 324
 325     val = 0;
 326     for (i = 0; i < 4; i++) {
 327         /* NOTE: ide_get_geometry() returns the physical
 328            geometry.  It is always such that: 1 <= sects <= 63, 1
 329            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 330            geometry can be different if a translation is done. */
 331         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 332                              &cylinders, &heads, &sectors) >= 0) {
 333             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 334             assert((trans & ~3) == 0);
 335             val |= trans << (i * 2);
 336         }
 337     }
 338     rtc_set_memory(s, 0x39, val);
 339
 340     qemu_unregister_reset(pc_cmos_init_late, opaque);
 341 }
 342
 343 typedef struct RTCCPUHotplugArg {
 344     Notifier cpu_added_notifier;
 345     ISADevice *rtc_state;
 346 } RTCCPUHotplugArg;
 347
 348 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
 349 {
 350     RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
 351                                          cpu_added_notifier);
 352     ISADevice *s = arg->rtc_state;
 353
 354     /* increment the number of CPUs */
 355     rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
 356 }
 357
 358 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 359                   const char *boot_device,
 360                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 361                   ISADevice *s)
 362 {
 363     int val, nb, i;
 364     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 365     static pc_cmos_init_late_arg arg;
 366     static RTCCPUHotplugArg cpu_hotplug_cb;
 367
 368     /* various important CMOS locations needed by PC/Bochs bios */
 369
 370     /* memory size */
 371     /* base memory (first MiB) */
 372     val = MIN(ram_size / 1024, 640);
 373     rtc_set_memory(s, 0x15, val);
 374     rtc_set_memory(s, 0x16, val >> 8);
 375     /* extended memory (next 64MiB) */
 376     if (ram_size > 1024 * 1024) {
 377         val = (ram_size - 1024 * 1024) / 1024;
 378     } else {
 379         val = 0;
 380     }
 381     if (val > 65535)
 382         val = 65535;
 383     rtc_set_memory(s, 0x17, val);
 384     rtc_set_memory(s, 0x18, val >> 8);
 385     rtc_set_memory(s, 0x30, val);
 386     rtc_set_memory(s, 0x31, val >> 8);
 387     /* memory between 16MiB and 4GiB */
 388     if (ram_size > 16 * 1024 * 1024) {
 389         val = (ram_size - 16 * 1024 * 1024) / 65536;
 390     } else {
 391         val = 0;
 392     }
 393     if (val > 65535)
 394         val = 65535;
 395     rtc_set_memory(s, 0x34, val);
 396     rtc_set_memory(s, 0x35, val >> 8);
 397     /* memory above 4GiB */
 398     val = above_4g_mem_size / 65536;
 399     rtc_set_memory(s, 0x5b, val);
 400     rtc_set_memory(s, 0x5c, val >> 8);
 401     rtc_set_memory(s, 0x5d, val >> 16);
 402
 403     /* set the number of CPU */
 404     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 405     /* init CPU hotplug notifier */
 406     cpu_hotplug_cb.rtc_state = s;
 407     cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
 408     qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
 409
 410     if (set_boot_dev(s, boot_device)) {
 411         exit(1);
 412     }
 413
 414     /* floppy type */
 415     if (floppy) {
 416         for (i = 0; i < 2; i++) {
 417             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 418         }
 419     }
 420     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 421         cmos_get_fd_drive_type(fd_type[1]);
 422     rtc_set_memory(s, 0x10, val);
 423
 424     val = 0;
 425     nb = 0;
 426     if (fd_type[0] < FDRIVE_DRV_NONE) {
 427         nb++;
 428     }
 429     if (fd_type[1] < FDRIVE_DRV_NONE) {
 430         nb++;
 431     }
 432     switch (nb) {
 433     case 0:
 434         break;
 435     case 1:
 436         val |= 0x01; /* 1 drive, ready for boot */
 437         break;
 438     case 2:
 439         val |= 0x41; /* 2 drives, ready for boot */
 440         break;
 441     }
 442     val |= 0x02; /* FPU is there */
 443     val |= 0x04; /* PS/2 mouse installed */
 444     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 445
 446     /* hard drives */
 447     arg.rtc_state = s;
 448     arg.idebus[0] = idebus0;
 449     arg.idebus[1] = idebus1;
 450     qemu_register_reset(pc_cmos_init_late, &arg);
 451 }
 452
 453 #define TYPE_PORT92 "port92"
 454 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 455
 456 /* port 92 stuff: could be split off */
 457 typedef struct Port92State {
 458     ISADevice parent_obj;
 459
 460     MemoryRegion io;
 461     uint8_t outport;
 462     qemu_irq *a20_out;
 463 } Port92State;
 464
 465 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 466                          unsigned size)
 467 {
 468     Port92State *s = opaque;
 469
 470     DPRINTF("port92: write 0x%02x\n", val);
 471     s->outport = val;
 472     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 473     if (val & 1) {
 474         qemu_system_reset_request();
 475     }
 476 }
 477
 478 static uint64_t port92_read(void *opaque, hwaddr addr,
 479                             unsigned size)
 480 {
 481     Port92State *s = opaque;
 482     uint32_t ret;
 483
 484     ret = s->outport;
 485     DPRINTF("port92: read 0x%02x\n", ret);
 486     return ret;
 487 }
 488
 489 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 490 {
 491     Port92State *s = PORT92(dev);
 492
 493     s->a20_out = a20_out;
 494 }
 495
 496 static const VMStateDescription vmstate_port92_isa = {
 497     .name = "port92",
 498     .version_id = 1,
 499     .minimum_version_id = 1,
 500     .minimum_version_id_old = 1,
 501     .fields      = (VMStateField []) {
 502         VMSTATE_UINT8(outport, Port92State),
 503         VMSTATE_END_OF_LIST()
 504     }
 505 };
 506
 507 static void port92_reset(DeviceState *d)
 508 {
 509     Port92State *s = PORT92(d);
 510
 511     s->outport &= ~1;
 512 }
 513
 514 static const MemoryRegionOps port92_ops = {
 515     .read = port92_read,
 516     .write = port92_write,
 517     .impl = {
 518         .min_access_size = 1,
 519         .max_access_size = 1,
 520     },
 521     .endianness = DEVICE_LITTLE_ENDIAN,
 522 };
 523
 524 static void port92_initfn(Object *obj)
 525 {
 526     Port92State *s = PORT92(obj);
 527
 528     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 529
 530     s->outport = 0;
 531 }
 532
 533 static void port92_realizefn(DeviceState *dev, Error **errp)
 534 {
 535     ISADevice *isadev = ISA_DEVICE(dev);
 536     Port92State *s = PORT92(dev);
 537
 538     isa_register_ioport(isadev, &s->io, 0x92);
 539 }
 540
 541 static void port92_class_initfn(ObjectClass *klass, void *data)
 542 {
 543     DeviceClass *dc = DEVICE_CLASS(klass);
 544
 545     dc->no_user = 1;
 546     dc->realize = port92_realizefn;
 547     dc->reset = port92_reset;
 548     dc->vmsd = &vmstate_port92_isa;
 549 }
 550
 551 static const TypeInfo port92_info = {
 552     .name          = TYPE_PORT92,
 553     .parent        = TYPE_ISA_DEVICE,
 554     .instance_size = sizeof(Port92State),
 555     .instance_init = port92_initfn,
 556     .class_init    = port92_class_initfn,
 557 };
 558
 559 static void port92_register_types(void)
 560 {
 561     type_register_static(&port92_info);
 562 }
 563
 564 type_init(port92_register_types)
 565
 566 static void handle_a20_line_change(void *opaque, int irq, int level)
 567 {
 568     X86CPU *cpu = opaque;
 569
 570     /* XXX: send to all CPUs ? */
 571     /* XXX: add logic to handle multiple A20 line sources */
 572     x86_cpu_set_a20(cpu, level);
 573 }
 574
 575 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 576 {
 577     int index = le32_to_cpu(e820_table.count);
 578     struct e820_entry *entry;
 579
 580     if (index >= E820_NR_ENTRIES)
 581         return -EBUSY;
 582     entry = &e820_table.entry[index++];
 583
 584     entry->address = cpu_to_le64(address);
 585     entry->length = cpu_to_le64(length);
 586     entry->type = cpu_to_le32(type);
 587
 588     e820_table.count = cpu_to_le32(index);
 589     return index;
 590 }
 591
 592 /* Calculates the limit to CPU APIC ID values
 593  *
 594  * This function returns the limit for the APIC ID value, so that all
 595  * CPU APIC IDs are < pc_apic_id_limit().
 596  *
 597  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 598  */
 599 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 600 {
 601     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 602 }
 603
 604 static FWCfgState *bochs_bios_init(void)
 605 {
 606     FWCfgState *fw_cfg;
 607     uint8_t *smbios_table;
 608     size_t smbios_len;
 609     uint64_t *numa_fw_cfg;
 610     int i, j;
 611     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 612
 613     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 614     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 615      *
 616      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 617      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 618      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 619      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 620      * may see".
 621      *
 622      * So, this means we must not use max_cpus, here, but the maximum possible
 623      * APIC ID value, plus one.
 624      *
 625      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 626      *     the APIC ID, not the "CPU index"
 627      */
 628     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 629     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 630     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 631     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 632                      acpi_tables, acpi_tables_len);
 633     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 634
 635     smbios_table = smbios_get_table(&smbios_len);
 636     if (smbios_table)
 637         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 638                          smbios_table, smbios_len);
 639     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 640                      &e820_table, sizeof(e820_table));
 641
 642     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 643     /* allocate memory for the NUMA channel: one (64bit) word for the number
 644      * of nodes, one word for each VCPU->node and one word for each node to
 645      * hold the amount of memory.
 646      */
 647     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 648     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 649     for (i = 0; i < max_cpus; i++) {
 650         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 651         assert(apic_id < apic_id_limit);
 652         for (j = 0; j < nb_numa_nodes; j++) {
 653             if (test_bit(i, node_cpumask[j])) {
 654                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 655                 break;
 656             }
 657         }
 658     }
 659     for (i = 0; i < nb_numa_nodes; i++) {
 660         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 661     }
 662     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 663                      (1 + apic_id_limit + nb_numa_nodes) *
 664                      sizeof(*numa_fw_cfg));
 665
 666     return fw_cfg;
 667 }
 668
 669 static long get_file_size(FILE *f)
 670 {
 671     long where, size;
 672
 673     /* XXX: on Unix systems, using fstat() probably makes more sense */
 674
 675     where = ftell(f);
 676     fseek(f, 0, SEEK_END);
 677     size = ftell(f);
 678     fseek(f, where, SEEK_SET);
 679
 680     return size;
 681 }
 682
 683 static void load_linux(FWCfgState *fw_cfg,
 684                        const char *kernel_filename,
 685                        const char *initrd_filename,
 686                        const char *kernel_cmdline,
 687                        hwaddr max_ram_size)
 688 {
 689     uint16_t protocol;
 690     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 691     uint32_t initrd_max;
 692     uint8_t header[8192], *setup, *kernel, *initrd_data;
 693     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 694     FILE *f;
 695     char *vmode;
 696
 697     /* Align to 16 bytes as a paranoia measure */
 698     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 699
 700     /* load the kernel header */
 701     f = fopen(kernel_filename, "rb");
 702     if (!f || !(kernel_size = get_file_size(f)) ||
 703         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 704         MIN(ARRAY_SIZE(header), kernel_size)) {
 705         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 706                 kernel_filename, strerror(errno));
 707         exit(1);
 708     }
 709
 710     /* kernel protocol version */
 711 #if 0
 712     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 713 #endif
 714     if (ldl_p(header+0x202) == 0x53726448) {
 715         protocol = lduw_p(header+0x206);
 716     } else {
 717         /* This looks like a multiboot kernel. If it is, let's stop
 718            treating it like a Linux kernel. */
 719         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 720                            kernel_cmdline, kernel_size, header)) {
 721             return;
 722         }
 723         protocol = 0;
 724     }
 725
 726     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 727         /* Low kernel */
 728         real_addr    = 0x90000;
 729         cmdline_addr = 0x9a000 - cmdline_size;
 730         prot_addr    = 0x10000;
 731     } else if (protocol < 0x202) {
 732         /* High but ancient kernel */
 733         real_addr    = 0x90000;
 734         cmdline_addr = 0x9a000 - cmdline_size;
 735         prot_addr    = 0x100000;
 736     } else {
 737         /* High and recent kernel */
 738         real_addr    = 0x10000;
 739         cmdline_addr = 0x20000;
 740         prot_addr    = 0x100000;
 741     }
 742
 743 #if 0
 744     fprintf(stderr,
 745             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 746             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 747             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 748             real_addr,
 749             cmdline_addr,
 750             prot_addr);
 751 #endif
 752
 753     /* highest address for loading the initrd */
 754     if (protocol >= 0x203) {
 755         initrd_max = ldl_p(header+0x22c);
 756     } else {
 757         initrd_max = 0x37ffffff;
 758     }
 759
 760     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 761         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 762
 763     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 764     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 765     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 766
 767     if (protocol >= 0x202) {
 768         stl_p(header+0x228, cmdline_addr);
 769     } else {
 770         stw_p(header+0x20, 0xA33F);
 771         stw_p(header+0x22, cmdline_addr-real_addr);
 772     }
 773
 774     /* handle vga= parameter */
 775     vmode = strstr(kernel_cmdline, "vga=");
 776     if (vmode) {
 777         unsigned int video_mode;
 778         /* skip "vga=" */
 779         vmode += 4;
 780         if (!strncmp(vmode, "normal", 6)) {
 781             video_mode = 0xffff;
 782         } else if (!strncmp(vmode, "ext", 3)) {
 783             video_mode = 0xfffe;
 784         } else if (!strncmp(vmode, "ask", 3)) {
 785             video_mode = 0xfffd;
 786         } else {
 787             video_mode = strtol(vmode, NULL, 0);
 788         }
 789         stw_p(header+0x1fa, video_mode);
 790     }
 791
 792     /* loader type */
 793     /* High nybble = B reserved for QEMU; low nybble is revision number.
 794        If this code is substantially changed, you may want to consider
 795        incrementing the revision. */
 796     if (protocol >= 0x200) {
 797         header[0x210] = 0xB0;
 798     }
 799     /* heap */
 800     if (protocol >= 0x201) {
 801         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 802         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 803     }
 804
 805     /* load initrd */
 806     if (initrd_filename) {
 807         if (protocol < 0x200) {
 808             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 809             exit(1);
 810         }
 811
 812         initrd_size = get_image_size(initrd_filename);
 813         if (initrd_size < 0) {
 814             fprintf(stderr, "qemu: error reading initrd %s\n",
 815                     initrd_filename);
 816             exit(1);
 817         }
 818
 819         initrd_addr = (initrd_max-initrd_size) & ~4095;
 820
 821         initrd_data = g_malloc(initrd_size);
 822         load_image(initrd_filename, initrd_data);
 823
 824         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 825         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 826         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 827
 828         stl_p(header+0x218, initrd_addr);
 829         stl_p(header+0x21c, initrd_size);
 830     }
 831
 832     /* load kernel and setup */
 833     setup_size = header[0x1f1];
 834     if (setup_size == 0) {
 835         setup_size = 4;
 836     }
 837     setup_size = (setup_size+1)*512;
 838     kernel_size -= setup_size;
 839
 840     setup  = g_malloc(setup_size);
 841     kernel = g_malloc(kernel_size);
 842     fseek(f, 0, SEEK_SET);
 843     if (fread(setup, 1, setup_size, f) != setup_size) {
 844         fprintf(stderr, "fread() failed\n");
 845         exit(1);
 846     }
 847     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 848         fprintf(stderr, "fread() failed\n");
 849         exit(1);
 850     }
 851     fclose(f);
 852     memcpy(setup, header, MIN(sizeof(header), setup_size));
 853
 854     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 855     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 856     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 857
 858     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 859     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 860     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 861
 862     option_rom[nb_option_roms].name = "linuxboot.bin";
 863     option_rom[nb_option_roms].bootindex = 0;
 864     nb_option_roms++;
 865 }
 866
 867 #define NE2000_NB_MAX 6
 868
 869 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 870                                               0x280, 0x380 };
 871 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 872
 873 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 874 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 875
 876 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 877 {
 878     static int nb_ne2k = 0;
 879
 880     if (nb_ne2k == NE2000_NB_MAX)
 881         return;
 882     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 883                     ne2000_irq[nb_ne2k], nd);
 884     nb_ne2k++;
 885 }
 886
 887 DeviceState *cpu_get_current_apic(void)
 888 {
 889     if (current_cpu) {
 890         X86CPU *cpu = X86_CPU(current_cpu);
 891         return cpu->env.apic_state;
 892     } else {
 893         return NULL;
 894     }
 895 }
 896
 897 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 898 {
 899     X86CPU *cpu = opaque;
 900
 901     if (level) {
 902         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 903     }
 904 }
 905
 906 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
 907                           DeviceState *icc_bridge, Error **errp)
 908 {
 909     X86CPU *cpu;
 910     Error *local_err = NULL;
 911
 912     cpu = cpu_x86_create(cpu_model, icc_bridge, errp);
 913     if (!cpu) {
 914         return cpu;
 915     }
 916
 917     object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
 918     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 919
 920     if (local_err) {
 921         if (cpu != NULL) {
 922             object_unref(OBJECT(cpu));
 923             cpu = NULL;
 924         }
 925         error_propagate(errp, local_err);
 926     }
 927     return cpu;
 928 }
 929
 930 static const char *current_cpu_model;
 931
 932 void pc_hot_add_cpu(const int64_t id, Error **errp)
 933 {
 934     DeviceState *icc_bridge;
 935     int64_t apic_id = x86_cpu_apic_id_from_index(id);
 936
 937     if (id < 0) {
 938         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
 939         return;
 940     }
 941
 942     if (cpu_exists(apic_id)) {
 943         error_setg(errp, "Unable to add CPU: %" PRIi64
 944                    ", it already exists", id);
 945         return;
 946     }
 947
 948     if (id >= max_cpus) {
 949         error_setg(errp, "Unable to add CPU: %" PRIi64
 950                    ", max allowed: %d", id, max_cpus - 1);
 951         return;
 952     }
 953
 954     icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
 955                                                  TYPE_ICC_BRIDGE, NULL));
 956     pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
 957 }
 958
 959 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
 960 {
 961     int i;
 962     X86CPU *cpu = NULL;
 963     Error *error = NULL;
 964
 965     /* init CPUs */
 966     if (cpu_model == NULL) {
 967 #ifdef TARGET_X86_64
 968         cpu_model = "qemu64";
 969 #else
 970         cpu_model = "qemu32";
 971 #endif
 972     }
 973     current_cpu_model = cpu_model;
 974
 975     for (i = 0; i < smp_cpus; i++) {
 976         cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
 977                          icc_bridge, &error);
 978         if (error) {
 979             fprintf(stderr, "%s\n", error_get_pretty(error));
 980             error_free(error);
 981             exit(1);
 982         }
 983     }
 984
 985     /* map APIC MMIO area if CPU has APIC */
 986     if (cpu && cpu->env.apic_state) {
 987         /* XXX: what if the base changes? */
 988         sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
 989                                 APIC_DEFAULT_ADDRESS, 0x1000);
 990     }
 991 }
 992
 993 /* pci-info ROM file. Little endian format */
 994 typedef struct PcRomPciInfo {
 995     uint64_t w32_min;
 996     uint64_t w32_max;
 997     uint64_t w64_min;
 998     uint64_t w64_max;
 999 } PcRomPciInfo;
1000
1001 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1002 {
1003     PcRomPciInfo *info;
1004     if (!guest_info->has_pci_info) {
1005         return;
1006     }
1007
1008     info = g_malloc(sizeof *info);
1009     info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin);
1010     info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end);
1011     info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin);
1012     info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end);
1013     /* Pass PCI hole info to guest via a side channel.
1014      * Required so guest PCI enumeration does the right thing. */
1015     fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1016 }
1017
1018 typedef struct PcGuestInfoState {
1019     PcGuestInfo info;
1020     Notifier machine_done;
1021 } PcGuestInfoState;
1022
1023 static
1024 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1025 {
1026     PcGuestInfoState *guest_info_state = container_of(notifier,
1027                                                       PcGuestInfoState,
1028                                                       machine_done);
1029     pc_fw_cfg_guest_info(&guest_info_state->info);
1030 }
1031
1032 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1033                                 ram_addr_t above_4g_mem_size)
1034 {
1035     PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1036     PcGuestInfo *guest_info = &guest_info_state->info;
1037
1038     guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
1039     if (sizeof(hwaddr) == 4) {
1040         guest_info->pci_info.w64.begin = 0;
1041         guest_info->pci_info.w64.end = 0;
1042     } else {
1043         /*
1044          * BIOS does not set MTRR entries for the 64 bit window, so no need to
1045          * align address to power of two.  Align address at 1G, this makes sure
1046          * it can be exactly covered with a PAT entry even when using huge
1047          * pages.
1048          */
1049         guest_info->pci_info.w64.begin =
1050             ROUND_UP((0x1ULL << 32) + above_4g_mem_size, 0x1ULL << 30);
1051         guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin +
1052             (0x1ULL << 62);
1053         assert(guest_info->pci_info.w64.begin <= guest_info->pci_info.w64.end);
1054     }
1055
1056     guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1057     qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1058     return guest_info;
1059 }
1060
1061 void pc_acpi_init(const char *default_dsdt)
1062 {
1063     char *filename;
1064
1065     if (acpi_tables != NULL) {
1066         /* manually set via -acpitable, leave it alone */
1067         return;
1068     }
1069
1070     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1071     if (filename == NULL) {
1072         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1073     } else {
1074         char *arg;
1075         QemuOpts *opts;
1076         Error *err = NULL;
1077
1078         arg = g_strdup_printf("file=%s", filename);
1079
1080         /* creates a deep copy of "arg" */
1081         opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1082         g_assert(opts != NULL);
1083
1084         acpi_table_add(opts, &err);
1085         if (err) {
1086             fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
1087                     error_get_pretty(err));
1088             error_free(err);
1089         }
1090         g_free(arg);
1091         g_free(filename);
1092     }
1093 }
1094
1095 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1096                            const char *kernel_filename,
1097                            const char *kernel_cmdline,
1098                            const char *initrd_filename,
1099                            ram_addr_t below_4g_mem_size,
1100                            ram_addr_t above_4g_mem_size,
1101                            MemoryRegion *rom_memory,
1102                            MemoryRegion **ram_memory,
1103                            PcGuestInfo *guest_info)
1104 {
1105     int linux_boot, i;
1106     MemoryRegion *ram, *option_rom_mr;
1107     MemoryRegion *ram_below_4g, *ram_above_4g;
1108     FWCfgState *fw_cfg;
1109
1110     linux_boot = (kernel_filename != NULL);
1111
1112     /* Allocate RAM.  We allocate it as a single memory region and use
1113      * aliases to address portions of it, mostly for backwards compatibility
1114      * with older qemus that used qemu_ram_alloc().
1115      */
1116     ram = g_malloc(sizeof(*ram));
1117     memory_region_init_ram(ram, NULL, "pc.ram",
1118                            below_4g_mem_size + above_4g_mem_size);
1119     vmstate_register_ram_global(ram);
1120     *ram_memory = ram;
1121     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1122     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1123                              0, below_4g_mem_size);
1124     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1125     if (above_4g_mem_size > 0) {
1126         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1127         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1128                                  below_4g_mem_size, above_4g_mem_size);
1129         memory_region_add_subregion(system_memory, 0x100000000ULL,
1130                                     ram_above_4g);
1131     }
1132
1133
1134     /* Initialize PC system firmware */
1135     pc_system_firmware_init(rom_memory);
1136
1137     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1138     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1139     vmstate_register_ram_global(option_rom_mr);
1140     memory_region_add_subregion_overlap(rom_memory,
1141                                         PC_ROM_MIN_VGA,
1142                                         option_rom_mr,
1143                                         1);
1144
1145     fw_cfg = bochs_bios_init();
1146     rom_set_fw(fw_cfg);
1147
1148     if (linux_boot) {
1149         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1150     }
1151
1152     for (i = 0; i < nb_option_roms; i++) {
1153         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1154     }
1155     guest_info->fw_cfg = fw_cfg;
1156     return fw_cfg;
1157 }
1158
1159 qemu_irq *pc_allocate_cpu_irq(void)
1160 {
1161     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1162 }
1163
1164 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1165 {
1166     DeviceState *dev = NULL;
1167
1168     if (pci_bus) {
1169         PCIDevice *pcidev = pci_vga_init(pci_bus);
1170         dev = pcidev ? &pcidev->qdev : NULL;
1171     } else if (isa_bus) {
1172         ISADevice *isadev = isa_vga_init(isa_bus);
1173         dev = isadev ? DEVICE(isadev) : NULL;
1174     }
1175     return dev;
1176 }
1177
1178 static void cpu_request_exit(void *opaque, int irq, int level)
1179 {
1180     CPUState *cpu = current_cpu;
1181
1182     if (cpu && level) {
1183         cpu_exit(cpu);
1184     }
1185 }
1186
1187 static const MemoryRegionOps ioport80_io_ops = {
1188     .write = ioport80_write,
1189     .read = ioport80_read,
1190     .endianness = DEVICE_NATIVE_ENDIAN,
1191     .impl = {
1192         .min_access_size = 1,
1193         .max_access_size = 1,
1194     },
1195 };
1196
1197 static const MemoryRegionOps ioportF0_io_ops = {
1198     .write = ioportF0_write,
1199     .read = ioportF0_read,
1200     .endianness = DEVICE_NATIVE_ENDIAN,
1201     .impl = {
1202         .min_access_size = 1,
1203         .max_access_size = 1,
1204     },
1205 };
1206
1207 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1208                           ISADevice **rtc_state,
1209                           ISADevice **floppy,
1210                           bool no_vmport)
1211 {
1212     int i;
1213     DriveInfo *fd[MAX_FD];
1214     DeviceState *hpet = NULL;
1215     int pit_isa_irq = 0;
1216     qemu_irq pit_alt_irq = NULL;
1217     qemu_irq rtc_irq = NULL;
1218     qemu_irq *a20_line;
1219     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1220     qemu_irq *cpu_exit_irq;
1221     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1222     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1223
1224     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1225     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1226
1227     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1228     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1229
1230     /*
1231      * Check if an HPET shall be created.
1232      *
1233      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1234      * when the HPET wants to take over. Thus we have to disable the latter.
1235      */
1236     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1237         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1238
1239         if (hpet) {
1240             for (i = 0; i < GSI_NUM_PINS; i++) {
1241                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1242             }
1243             pit_isa_irq = -1;
1244             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1245             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1246         }
1247     }
1248     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1249
1250     qemu_register_boot_set(pc_boot_set, *rtc_state);
1251
1252     if (!xen_enabled()) {
1253         if (kvm_irqchip_in_kernel()) {
1254             pit = kvm_pit_init(isa_bus, 0x40);
1255         } else {
1256             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1257         }
1258         if (hpet) {
1259             /* connect PIT to output control line of the HPET */
1260             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1261         }
1262         pcspk_init(isa_bus, pit);
1263     }
1264
1265     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1266         if (serial_hds[i]) {
1267             serial_isa_init(isa_bus, i, serial_hds[i]);
1268         }
1269     }
1270
1271     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1272         if (parallel_hds[i]) {
1273             parallel_init(isa_bus, i, parallel_hds[i]);
1274         }
1275     }
1276
1277     a20_line = qemu_allocate_irqs(handle_a20_line_change,
1278                                   x86_env_get_cpu(first_cpu), 2);
1279     i8042 = isa_create_simple(isa_bus, "i8042");
1280     i8042_setup_a20_line(i8042, &a20_line[0]);
1281     if (!no_vmport) {
1282         vmport_init(isa_bus);
1283         vmmouse = isa_try_create(isa_bus, "vmmouse");
1284     } else {
1285         vmmouse = NULL;
1286     }
1287     if (vmmouse) {
1288         DeviceState *dev = DEVICE(vmmouse);
1289         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1290         qdev_init_nofail(dev);
1291     }
1292     port92 = isa_create_simple(isa_bus, "port92");
1293     port92_init(port92, &a20_line[1]);
1294
1295     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1296     DMA_init(0, cpu_exit_irq);
1297
1298     for(i = 0; i < MAX_FD; i++) {
1299         fd[i] = drive_get(IF_FLOPPY, 0, i);
1300     }
1301     *floppy = fdctrl_init_isa(isa_bus, fd);
1302 }
1303
1304 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1305 {
1306     int i;
1307
1308     for (i = 0; i < nb_nics; i++) {
1309         NICInfo *nd = &nd_table[i];
1310
1311         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1312             pc_init_ne2k_isa(isa_bus, nd);
1313         } else {
1314             pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1315         }
1316     }
1317 }
1318
1319 void pc_pci_device_init(PCIBus *pci_bus)
1320 {
1321     int max_bus;
1322     int bus;
1323
1324     max_bus = drive_get_max_bus(IF_SCSI);
1325     for (bus = 0; bus <= max_bus; bus++) {
1326         pci_create_simple(pci_bus, -1, "lsi53c895a");
1327     }
1328 }
1329
1330 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1331 {
1332     DeviceState *dev;
1333     SysBusDevice *d;
1334     unsigned int i;
1335
1336     if (kvm_irqchip_in_kernel()) {
1337         dev = qdev_create(NULL, "kvm-ioapic");
1338     } else {
1339         dev = qdev_create(NULL, "ioapic");
1340     }
1341     if (parent_name) {
1342         object_property_add_child(object_resolve_path(parent_name, NULL),
1343                                   "ioapic", OBJECT(dev), NULL);
1344     }
1345     qdev_init_nofail(dev);
1346     d = SYS_BUS_DEVICE(dev);
1347     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1348
1349     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1350         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1351     }
1352 }