2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/net/ne2000-isa.h"
78 /* debug PC/ISA interrupts */
82 #define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85 #define DPRINTF(fmt, ...)
88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94 #define E820_NR_ENTRIES 16
100 } QEMU_PACKED
__attribute((__aligned__(4)));
104 struct e820_entry entry
[E820_NR_ENTRIES
];
105 } QEMU_PACKED
__attribute((__aligned__(4)));
107 static struct e820_table e820_reserve
;
108 static struct e820_entry
*e820_table
;
109 static unsigned e820_entries
;
110 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
112 GlobalProperty pc_compat_3_1
[] = {
114 .driver
= "intel-iommu",
115 .property
= "dma-drain",
119 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
121 GlobalProperty pc_compat_3_0
[] = {
123 .driver
= TYPE_X86_CPU
,
124 .property
= "x-hv-synic-kvm-only",
127 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
131 .driver
= "Skylake-Server-IBRS" "-" TYPE_X86_CPU
,
136 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
138 void gsi_handler(void *opaque
, int n
, int level
)
140 GSIState
*s
= opaque
;
142 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
143 if (n
< ISA_NUM_IRQS
) {
144 qemu_set_irq(s
->i8259_irq
[n
], level
);
146 qemu_set_irq(s
->ioapic_irq
[n
], level
);
149 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
154 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
156 return 0xffffffffffffffffULL
;
159 /* MSDOS compatibility mode FPU exception support */
160 static qemu_irq ferr_irq
;
162 void pc_register_ferr_irq(qemu_irq irq
)
167 /* XXX: add IGNNE support */
168 void cpu_set_ferr(CPUX86State
*s
)
170 qemu_irq_raise(ferr_irq
);
173 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
176 qemu_irq_lower(ferr_irq
);
179 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
181 return 0xffffffffffffffffULL
;
185 uint64_t cpu_get_tsc(CPUX86State
*env
)
187 return cpu_get_ticks();
191 int cpu_get_pic_interrupt(CPUX86State
*env
)
193 X86CPU
*cpu
= x86_env_get_cpu(env
);
196 if (!kvm_irqchip_in_kernel()) {
197 intno
= apic_get_interrupt(cpu
->apic_state
);
201 /* read the irq from the PIC */
202 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
207 intno
= pic_read_irq(isa_pic
);
211 static void pic_irq_request(void *opaque
, int irq
, int level
)
213 CPUState
*cs
= first_cpu
;
214 X86CPU
*cpu
= X86_CPU(cs
);
216 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
217 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
220 if (apic_accept_pic_intr(cpu
->apic_state
)) {
221 apic_deliver_pic_intr(cpu
->apic_state
, level
);
226 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
228 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
233 /* PC cmos mappings */
235 #define REG_EQUIPMENT_BYTE 0x14
237 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
242 case FLOPPY_DRIVE_TYPE_144
:
243 /* 1.44 Mb 3"5 drive */
246 case FLOPPY_DRIVE_TYPE_288
:
247 /* 2.88 Mb 3"5 drive */
250 case FLOPPY_DRIVE_TYPE_120
:
251 /* 1.2 Mb 5"5 drive */
254 case FLOPPY_DRIVE_TYPE_NONE
:
262 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
263 int16_t cylinders
, int8_t heads
, int8_t sectors
)
265 rtc_set_memory(s
, type_ofs
, 47);
266 rtc_set_memory(s
, info_ofs
, cylinders
);
267 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
268 rtc_set_memory(s
, info_ofs
+ 2, heads
);
269 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
270 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
271 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
272 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
273 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
274 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
277 /* convert boot_device letter to something recognizable by the bios */
278 static int boot_device2nibble(char boot_device
)
280 switch(boot_device
) {
283 return 0x01; /* floppy boot */
285 return 0x02; /* hard drive boot */
287 return 0x03; /* CD-ROM boot */
289 return 0x04; /* Network boot */
294 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
296 #define PC_MAX_BOOT_DEVICES 3
297 int nbds
, bds
[3] = { 0, };
300 nbds
= strlen(boot_device
);
301 if (nbds
> PC_MAX_BOOT_DEVICES
) {
302 error_setg(errp
, "Too many boot devices for PC");
305 for (i
= 0; i
< nbds
; i
++) {
306 bds
[i
] = boot_device2nibble(boot_device
[i
]);
308 error_setg(errp
, "Invalid boot device for PC: '%c'",
313 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
314 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
317 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
319 set_boot_dev(opaque
, boot_device
, errp
);
322 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
325 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
326 FLOPPY_DRIVE_TYPE_NONE
};
330 for (i
= 0; i
< 2; i
++) {
331 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
334 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
335 cmos_get_fd_drive_type(fd_type
[1]);
336 rtc_set_memory(rtc_state
, 0x10, val
);
338 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
340 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
343 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
350 val
|= 0x01; /* 1 drive, ready for boot */
353 val
|= 0x41; /* 2 drives, ready for boot */
356 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
359 typedef struct pc_cmos_init_late_arg
{
360 ISADevice
*rtc_state
;
362 } pc_cmos_init_late_arg
;
364 typedef struct check_fdc_state
{
369 static int check_fdc(Object
*obj
, void *opaque
)
371 CheckFdcState
*state
= opaque
;
374 Error
*local_err
= NULL
;
376 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
381 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
382 if (local_err
|| iobase
!= 0x3f0) {
383 error_free(local_err
);
388 state
->multiple
= true;
390 state
->floppy
= ISA_DEVICE(obj
);
395 static const char * const fdc_container_path
[] = {
396 "/unattached", "/peripheral", "/peripheral-anon"
400 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
403 ISADevice
*pc_find_fdc0(void)
407 CheckFdcState state
= { 0 };
409 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
410 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
411 object_child_foreach(container
, check_fdc
, &state
);
414 if (state
.multiple
) {
415 warn_report("multiple floppy disk controllers with "
416 "iobase=0x3f0 have been found");
417 error_printf("the one being picked for CMOS setup might not reflect "
424 static void pc_cmos_init_late(void *opaque
)
426 pc_cmos_init_late_arg
*arg
= opaque
;
427 ISADevice
*s
= arg
->rtc_state
;
429 int8_t heads
, sectors
;
434 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
435 &cylinders
, &heads
, §ors
) >= 0) {
436 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
439 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
440 &cylinders
, &heads
, §ors
) >= 0) {
441 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
444 rtc_set_memory(s
, 0x12, val
);
447 for (i
= 0; i
< 4; i
++) {
448 /* NOTE: ide_get_geometry() returns the physical
449 geometry. It is always such that: 1 <= sects <= 63, 1
450 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
451 geometry can be different if a translation is done. */
452 if (arg
->idebus
[i
/ 2] &&
453 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
454 &cylinders
, &heads
, §ors
) >= 0) {
455 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
456 assert((trans
& ~3) == 0);
457 val
|= trans
<< (i
* 2);
460 rtc_set_memory(s
, 0x39, val
);
462 pc_cmos_init_floppy(s
, pc_find_fdc0());
464 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
467 void pc_cmos_init(PCMachineState
*pcms
,
468 BusState
*idebus0
, BusState
*idebus1
,
472 static pc_cmos_init_late_arg arg
;
474 /* various important CMOS locations needed by PC/Bochs bios */
477 /* base memory (first MiB) */
478 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
479 rtc_set_memory(s
, 0x15, val
);
480 rtc_set_memory(s
, 0x16, val
>> 8);
481 /* extended memory (next 64MiB) */
482 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
483 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
489 rtc_set_memory(s
, 0x17, val
);
490 rtc_set_memory(s
, 0x18, val
>> 8);
491 rtc_set_memory(s
, 0x30, val
);
492 rtc_set_memory(s
, 0x31, val
>> 8);
493 /* memory between 16MiB and 4GiB */
494 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
495 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
501 rtc_set_memory(s
, 0x34, val
);
502 rtc_set_memory(s
, 0x35, val
>> 8);
503 /* memory above 4GiB */
504 val
= pcms
->above_4g_mem_size
/ 65536;
505 rtc_set_memory(s
, 0x5b, val
);
506 rtc_set_memory(s
, 0x5c, val
>> 8);
507 rtc_set_memory(s
, 0x5d, val
>> 16);
509 object_property_add_link(OBJECT(pcms
), "rtc_state",
511 (Object
**)&pcms
->rtc
,
512 object_property_allow_set_link
,
513 OBJ_PROP_LINK_STRONG
, &error_abort
);
514 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
515 "rtc_state", &error_abort
);
517 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
520 val
|= 0x02; /* FPU is there */
521 val
|= 0x04; /* PS/2 mouse installed */
522 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
524 /* hard drives and FDC */
526 arg
.idebus
[0] = idebus0
;
527 arg
.idebus
[1] = idebus1
;
528 qemu_register_reset(pc_cmos_init_late
, &arg
);
531 #define TYPE_PORT92 "port92"
532 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
534 /* port 92 stuff: could be split off */
535 typedef struct Port92State
{
536 ISADevice parent_obj
;
543 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
546 Port92State
*s
= opaque
;
547 int oldval
= s
->outport
;
549 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
551 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
552 if ((val
& 1) && !(oldval
& 1)) {
553 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
557 static uint64_t port92_read(void *opaque
, hwaddr addr
,
560 Port92State
*s
= opaque
;
564 DPRINTF("port92: read 0x%02x\n", ret
);
568 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
570 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
573 static const VMStateDescription vmstate_port92_isa
= {
576 .minimum_version_id
= 1,
577 .fields
= (VMStateField
[]) {
578 VMSTATE_UINT8(outport
, Port92State
),
579 VMSTATE_END_OF_LIST()
583 static void port92_reset(DeviceState
*d
)
585 Port92State
*s
= PORT92(d
);
590 static const MemoryRegionOps port92_ops
= {
592 .write
= port92_write
,
594 .min_access_size
= 1,
595 .max_access_size
= 1,
597 .endianness
= DEVICE_LITTLE_ENDIAN
,
600 static void port92_initfn(Object
*obj
)
602 Port92State
*s
= PORT92(obj
);
604 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
608 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
611 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
613 ISADevice
*isadev
= ISA_DEVICE(dev
);
614 Port92State
*s
= PORT92(dev
);
616 isa_register_ioport(isadev
, &s
->io
, 0x92);
619 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
621 DeviceClass
*dc
= DEVICE_CLASS(klass
);
623 dc
->realize
= port92_realizefn
;
624 dc
->reset
= port92_reset
;
625 dc
->vmsd
= &vmstate_port92_isa
;
627 * Reason: unlike ordinary ISA devices, this one needs additional
628 * wiring: its A20 output line needs to be wired up by
631 dc
->user_creatable
= false;
634 static const TypeInfo port92_info
= {
636 .parent
= TYPE_ISA_DEVICE
,
637 .instance_size
= sizeof(Port92State
),
638 .instance_init
= port92_initfn
,
639 .class_init
= port92_class_initfn
,
642 static void port92_register_types(void)
644 type_register_static(&port92_info
);
647 type_init(port92_register_types
)
649 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
651 X86CPU
*cpu
= opaque
;
653 /* XXX: send to all CPUs ? */
654 /* XXX: add logic to handle multiple A20 line sources */
655 x86_cpu_set_a20(cpu
, level
);
658 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
660 int index
= le32_to_cpu(e820_reserve
.count
);
661 struct e820_entry
*entry
;
663 if (type
!= E820_RAM
) {
664 /* old FW_CFG_E820_TABLE entry -- reservations only */
665 if (index
>= E820_NR_ENTRIES
) {
668 entry
= &e820_reserve
.entry
[index
++];
670 entry
->address
= cpu_to_le64(address
);
671 entry
->length
= cpu_to_le64(length
);
672 entry
->type
= cpu_to_le32(type
);
674 e820_reserve
.count
= cpu_to_le32(index
);
677 /* new "etc/e820" file -- include ram too */
678 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
679 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
680 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
681 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
687 int e820_get_num_entries(void)
692 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
694 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
695 *address
= le64_to_cpu(e820_table
[idx
].address
);
696 *length
= le64_to_cpu(e820_table
[idx
].length
);
702 /* Enables contiguous-apic-ID mode, for compatibility */
703 static bool compat_apic_id_mode
;
705 void enable_compat_apic_id_mode(void)
707 compat_apic_id_mode
= true;
710 /* Calculates initial APIC ID for a specific CPU index
712 * Currently we need to be able to calculate the APIC ID from the CPU index
713 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
714 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
715 * all CPUs up to max_cpus.
717 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
722 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
723 if (compat_apic_id_mode
) {
724 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
725 error_report("APIC IDs set in compatibility mode, "
726 "CPU topology won't match the configuration");
735 static void pc_build_smbios(PCMachineState
*pcms
)
737 uint8_t *smbios_tables
, *smbios_anchor
;
738 size_t smbios_tables_len
, smbios_anchor_len
;
739 struct smbios_phys_mem_area
*mem_array
;
740 unsigned i
, array_count
;
741 MachineState
*ms
= MACHINE(pcms
);
742 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
744 /* tell smbios about cpuid version and features */
745 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
747 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
749 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
750 smbios_tables
, smbios_tables_len
);
753 /* build the array of physical mem area from e820 table */
754 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
755 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
758 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
759 mem_array
[array_count
].address
= addr
;
760 mem_array
[array_count
].length
= len
;
764 smbios_get_tables(mem_array
, array_count
,
765 &smbios_tables
, &smbios_tables_len
,
766 &smbios_anchor
, &smbios_anchor_len
);
770 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
771 smbios_tables
, smbios_tables_len
);
772 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
773 smbios_anchor
, smbios_anchor_len
);
777 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
780 uint64_t *numa_fw_cfg
;
782 const CPUArchIdList
*cpus
;
783 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
785 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
786 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
788 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
790 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
791 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
792 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
793 * for CPU hotplug also uses APIC ID and not "CPU index".
794 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
795 * but the "limit to the APIC ID values SeaBIOS may see".
797 * So for compatibility reasons with old BIOSes we are stuck with
798 * "etc/max-cpus" actually being apic_id_limit
800 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
801 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
802 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
803 acpi_tables
, acpi_tables_len
);
804 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
806 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
807 &e820_reserve
, sizeof(e820_reserve
));
808 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
809 sizeof(struct e820_entry
) * e820_entries
);
811 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
812 /* allocate memory for the NUMA channel: one (64bit) word for the number
813 * of nodes, one word for each VCPU->node and one word for each node to
814 * hold the amount of memory.
816 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
817 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
818 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
819 for (i
= 0; i
< cpus
->len
; i
++) {
820 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
821 assert(apic_id
< pcms
->apic_id_limit
);
822 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
824 for (i
= 0; i
< nb_numa_nodes
; i
++) {
825 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
826 cpu_to_le64(numa_info
[i
].node_mem
);
828 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
829 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
830 sizeof(*numa_fw_cfg
));
835 static long get_file_size(FILE *f
)
839 /* XXX: on Unix systems, using fstat() probably makes more sense */
842 fseek(f
, 0, SEEK_END
);
844 fseek(f
, where
, SEEK_SET
);
849 /* setup_data types */
851 #define SETUP_E820_EXT 1
861 } __attribute__((packed
));
863 static void load_linux(PCMachineState
*pcms
,
867 int setup_size
, kernel_size
, cmdline_size
;
868 int dtb_size
, setup_data_offset
;
870 uint8_t header
[8192], *setup
, *kernel
;
871 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
874 MachineState
*machine
= MACHINE(pcms
);
875 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
876 struct setup_data
*setup_data
;
877 const char *kernel_filename
= machine
->kernel_filename
;
878 const char *initrd_filename
= machine
->initrd_filename
;
879 const char *dtb_filename
= machine
->dtb
;
880 const char *kernel_cmdline
= machine
->kernel_cmdline
;
882 /* Align to 16 bytes as a paranoia measure */
883 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
885 /* load the kernel header */
886 f
= fopen(kernel_filename
, "rb");
887 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
888 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
889 MIN(ARRAY_SIZE(header
), kernel_size
)) {
890 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
891 kernel_filename
, strerror(errno
));
895 /* kernel protocol version */
897 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
899 if (ldl_p(header
+0x202) == 0x53726448) {
900 protocol
= lduw_p(header
+0x206);
902 /* This looks like a multiboot kernel. If it is, let's stop
903 treating it like a Linux kernel. */
904 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
905 kernel_cmdline
, kernel_size
, header
)) {
911 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
914 cmdline_addr
= 0x9a000 - cmdline_size
;
916 } else if (protocol
< 0x202) {
917 /* High but ancient kernel */
919 cmdline_addr
= 0x9a000 - cmdline_size
;
920 prot_addr
= 0x100000;
922 /* High and recent kernel */
924 cmdline_addr
= 0x20000;
925 prot_addr
= 0x100000;
930 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
931 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
932 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
938 /* highest address for loading the initrd */
939 if (protocol
>= 0x203) {
940 initrd_max
= ldl_p(header
+0x22c);
942 initrd_max
= 0x37ffffff;
945 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
946 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
949 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
950 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
951 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
953 if (protocol
>= 0x202) {
954 stl_p(header
+0x228, cmdline_addr
);
956 stw_p(header
+0x20, 0xA33F);
957 stw_p(header
+0x22, cmdline_addr
-real_addr
);
960 /* handle vga= parameter */
961 vmode
= strstr(kernel_cmdline
, "vga=");
963 unsigned int video_mode
;
966 if (!strncmp(vmode
, "normal", 6)) {
968 } else if (!strncmp(vmode
, "ext", 3)) {
970 } else if (!strncmp(vmode
, "ask", 3)) {
973 video_mode
= strtol(vmode
, NULL
, 0);
975 stw_p(header
+0x1fa, video_mode
);
979 /* High nybble = B reserved for QEMU; low nybble is revision number.
980 If this code is substantially changed, you may want to consider
981 incrementing the revision. */
982 if (protocol
>= 0x200) {
983 header
[0x210] = 0xB0;
986 if (protocol
>= 0x201) {
987 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
988 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
992 if (initrd_filename
) {
997 if (protocol
< 0x200) {
998 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1002 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1003 &initrd_size
, &gerr
)) {
1004 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1005 initrd_filename
, gerr
->message
);
1008 if (initrd_size
>= initrd_max
) {
1009 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1010 "(max: %"PRIu32
", need %"PRId64
")\n",
1011 initrd_max
, (uint64_t)initrd_size
);
1015 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1017 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1018 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1019 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1021 stl_p(header
+0x218, initrd_addr
);
1022 stl_p(header
+0x21c, initrd_size
);
1025 /* load kernel and setup */
1026 setup_size
= header
[0x1f1];
1027 if (setup_size
== 0) {
1030 setup_size
= (setup_size
+1)*512;
1031 if (setup_size
> kernel_size
) {
1032 fprintf(stderr
, "qemu: invalid kernel header\n");
1035 kernel_size
-= setup_size
;
1037 setup
= g_malloc(setup_size
);
1038 kernel
= g_malloc(kernel_size
);
1039 fseek(f
, 0, SEEK_SET
);
1040 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1041 fprintf(stderr
, "fread() failed\n");
1044 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1045 fprintf(stderr
, "fread() failed\n");
1050 /* append dtb to kernel */
1052 if (protocol
< 0x209) {
1053 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1057 dtb_size
= get_image_size(dtb_filename
);
1058 if (dtb_size
<= 0) {
1059 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1060 dtb_filename
, strerror(errno
));
1064 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1065 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1066 kernel
= g_realloc(kernel
, kernel_size
);
1068 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1070 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1071 setup_data
->next
= 0;
1072 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1073 setup_data
->len
= cpu_to_le32(dtb_size
);
1075 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1078 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1080 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1081 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1082 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1084 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1085 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1086 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1088 option_rom
[nb_option_roms
].bootindex
= 0;
1089 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1090 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1091 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1096 #define NE2000_NB_MAX 6
1098 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1100 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1102 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1104 static int nb_ne2k
= 0;
1106 if (nb_ne2k
== NE2000_NB_MAX
)
1108 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1109 ne2000_irq
[nb_ne2k
], nd
);
1113 DeviceState
*cpu_get_current_apic(void)
1116 X86CPU
*cpu
= X86_CPU(current_cpu
);
1117 return cpu
->apic_state
;
1123 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1125 X86CPU
*cpu
= opaque
;
1128 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1132 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1135 Error
*local_err
= NULL
;
1137 cpu
= object_new(typename
);
1139 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1140 object_property_set_bool(cpu
, true, "realized", &local_err
);
1143 error_propagate(errp
, local_err
);
1146 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1148 MachineState
*ms
= MACHINE(qdev_get_machine());
1149 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1150 Error
*local_err
= NULL
;
1153 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1157 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1158 error_setg(errp
, "Unable to add CPU: %" PRIi64
1159 ", resulting APIC ID (%" PRIi64
") is too large",
1164 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1166 error_propagate(errp
, local_err
);
1171 void pc_cpus_init(PCMachineState
*pcms
)
1174 const CPUArchIdList
*possible_cpus
;
1175 MachineState
*ms
= MACHINE(pcms
);
1176 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1178 /* Calculates the limit to CPU APIC ID values
1180 * Limit for the APIC ID value, so that all
1181 * CPU APIC IDs are < pcms->apic_id_limit.
1183 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1185 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1186 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1187 for (i
= 0; i
< smp_cpus
; i
++) {
1188 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1193 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1195 MachineState
*ms
= MACHINE(pcms
);
1196 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1197 CPUX86State
*env
= &cpu
->env
;
1198 uint32_t unused
, ecx
, edx
;
1199 uint64_t feature_control_bits
= 0;
1202 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1203 if (ecx
& CPUID_EXT_VMX
) {
1204 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1207 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1208 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1209 (env
->mcg_cap
& MCG_LMCE_P
)) {
1210 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1213 if (!feature_control_bits
) {
1217 val
= g_malloc(sizeof(*val
));
1218 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1219 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1222 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1224 if (cpus_count
> 0xff) {
1225 /* If the number of CPUs can't be represented in 8 bits, the
1226 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1227 * to make old BIOSes fail more predictably.
1229 rtc_set_memory(rtc
, 0x5f, 0);
1231 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1236 void pc_machine_done(Notifier
*notifier
, void *data
)
1238 PCMachineState
*pcms
= container_of(notifier
,
1239 PCMachineState
, machine_done
);
1240 PCIBus
*bus
= pcms
->bus
;
1242 /* set the number of CPUs */
1243 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1246 int extra_hosts
= 0;
1248 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1249 /* look for expander root buses */
1250 if (pci_bus_is_root(bus
)) {
1254 if (extra_hosts
&& pcms
->fw_cfg
) {
1255 uint64_t *val
= g_malloc(sizeof(*val
));
1256 *val
= cpu_to_le64(extra_hosts
);
1257 fw_cfg_add_file(pcms
->fw_cfg
,
1258 "etc/extra-pci-roots", val
, sizeof(*val
));
1264 pc_build_smbios(pcms
);
1265 pc_build_feature_control_file(pcms
);
1266 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1267 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1270 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1271 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1273 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1274 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1275 error_report("current -smp configuration requires "
1276 "Extended Interrupt Mode enabled. "
1277 "You can add an IOMMU using: "
1278 "-device intel-iommu,intremap=on,eim=on");
1284 void pc_guest_info_init(PCMachineState
*pcms
)
1288 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1289 pcms
->numa_nodes
= nb_numa_nodes
;
1290 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1291 sizeof *pcms
->node_mem
);
1292 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1293 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1296 pcms
->machine_done
.notify
= pc_machine_done
;
1297 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1300 /* setup pci memory address space mapping into system address space */
1301 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1302 MemoryRegion
*pci_address_space
)
1304 /* Set to lower priority than RAM */
1305 memory_region_add_subregion_overlap(system_memory
, 0x0,
1306 pci_address_space
, -1);
1309 void pc_acpi_init(const char *default_dsdt
)
1313 if (acpi_tables
!= NULL
) {
1314 /* manually set via -acpitable, leave it alone */
1318 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1319 if (filename
== NULL
) {
1320 warn_report("failed to find %s", default_dsdt
);
1322 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1326 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1328 acpi_table_add_builtin(opts
, &err
);
1330 warn_reportf_err(err
, "failed to load %s: ", filename
);
1336 void xen_load_linux(PCMachineState
*pcms
)
1341 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1343 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1344 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1347 load_linux(pcms
, fw_cfg
);
1348 for (i
= 0; i
< nb_option_roms
; i
++) {
1349 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1350 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1351 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1352 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1354 pcms
->fw_cfg
= fw_cfg
;
1357 void pc_memory_init(PCMachineState
*pcms
,
1358 MemoryRegion
*system_memory
,
1359 MemoryRegion
*rom_memory
,
1360 MemoryRegion
**ram_memory
)
1363 MemoryRegion
*ram
, *option_rom_mr
;
1364 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1366 MachineState
*machine
= MACHINE(pcms
);
1367 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1369 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1370 pcms
->above_4g_mem_size
);
1372 linux_boot
= (machine
->kernel_filename
!= NULL
);
1374 /* Allocate RAM. We allocate it as a single memory region and use
1375 * aliases to address portions of it, mostly for backwards compatibility
1376 * with older qemus that used qemu_ram_alloc().
1378 ram
= g_malloc(sizeof(*ram
));
1379 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1382 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1383 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1384 0, pcms
->below_4g_mem_size
);
1385 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1386 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1387 if (pcms
->above_4g_mem_size
> 0) {
1388 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1389 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1390 pcms
->below_4g_mem_size
,
1391 pcms
->above_4g_mem_size
);
1392 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1394 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1397 if (!pcmc
->has_reserved_memory
&&
1398 (machine
->ram_slots
||
1399 (machine
->maxram_size
> machine
->ram_size
))) {
1400 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1402 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1407 /* always allocate the device memory information */
1408 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1410 /* initialize device memory address space */
1411 if (pcmc
->has_reserved_memory
&&
1412 (machine
->ram_size
< machine
->maxram_size
)) {
1413 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1415 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1416 error_report("unsupported amount of memory slots: %"PRIu64
,
1417 machine
->ram_slots
);
1421 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1422 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1423 error_report("maximum memory size must by aligned to multiple of "
1424 "%d bytes", TARGET_PAGE_SIZE
);
1428 machine
->device_memory
->base
=
1429 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1431 if (pcmc
->enforce_aligned_dimm
) {
1432 /* size device region assuming 1G page max alignment per slot */
1433 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1436 if ((machine
->device_memory
->base
+ device_mem_size
) <
1438 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1439 machine
->maxram_size
);
1443 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1444 "device-memory", device_mem_size
);
1445 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1446 &machine
->device_memory
->mr
);
1449 /* Initialize PC system firmware */
1450 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
1452 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1453 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1455 if (pcmc
->pci_enabled
) {
1456 memory_region_set_readonly(option_rom_mr
, true);
1458 memory_region_add_subregion_overlap(rom_memory
,
1463 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1467 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1468 uint64_t *val
= g_malloc(sizeof(*val
));
1469 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1470 uint64_t res_mem_end
= machine
->device_memory
->base
;
1472 if (!pcmc
->broken_reserved_end
) {
1473 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1475 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1476 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1480 load_linux(pcms
, fw_cfg
);
1483 for (i
= 0; i
< nb_option_roms
; i
++) {
1484 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1486 pcms
->fw_cfg
= fw_cfg
;
1488 /* Init default IOAPIC address space */
1489 pcms
->ioapic_as
= &address_space_memory
;
1493 * The 64bit pci hole starts after "above 4G RAM" and
1494 * potentially the space reserved for memory hotplug.
1496 uint64_t pc_pci_hole64_start(void)
1498 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1499 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1500 MachineState
*ms
= MACHINE(pcms
);
1501 uint64_t hole64_start
= 0;
1503 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1504 hole64_start
= ms
->device_memory
->base
;
1505 if (!pcmc
->broken_reserved_end
) {
1506 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1509 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1512 return ROUND_UP(hole64_start
, 1 * GiB
);
1515 qemu_irq
pc_allocate_cpu_irq(void)
1517 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1520 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1522 DeviceState
*dev
= NULL
;
1524 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1526 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1527 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1528 } else if (isa_bus
) {
1529 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1530 dev
= isadev
? DEVICE(isadev
) : NULL
;
1532 rom_reset_order_override();
1536 static const MemoryRegionOps ioport80_io_ops
= {
1537 .write
= ioport80_write
,
1538 .read
= ioport80_read
,
1539 .endianness
= DEVICE_NATIVE_ENDIAN
,
1541 .min_access_size
= 1,
1542 .max_access_size
= 1,
1546 static const MemoryRegionOps ioportF0_io_ops
= {
1547 .write
= ioportF0_write
,
1548 .read
= ioportF0_read
,
1549 .endianness
= DEVICE_NATIVE_ENDIAN
,
1551 .min_access_size
= 1,
1552 .max_access_size
= 1,
1556 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
1559 DriveInfo
*fd
[MAX_FD
];
1561 ISADevice
*i8042
, *port92
, *vmmouse
;
1563 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1564 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1566 for (i
= 0; i
< MAX_FD
; i
++) {
1567 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1568 create_fdctrl
|= !!fd
[i
];
1570 if (create_fdctrl
) {
1571 fdctrl_init_isa(isa_bus
, fd
);
1574 i8042
= isa_create_simple(isa_bus
, "i8042");
1576 vmport_init(isa_bus
);
1577 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1582 DeviceState
*dev
= DEVICE(vmmouse
);
1583 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1584 qdev_init_nofail(dev
);
1586 port92
= isa_create_simple(isa_bus
, "port92");
1588 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1589 i8042_setup_a20_line(i8042
, a20_line
[0]);
1590 port92_init(port92
, a20_line
[1]);
1594 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1595 ISADevice
**rtc_state
,
1602 DeviceState
*hpet
= NULL
;
1603 int pit_isa_irq
= 0;
1604 qemu_irq pit_alt_irq
= NULL
;
1605 qemu_irq rtc_irq
= NULL
;
1606 ISADevice
*pit
= NULL
;
1607 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1608 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1610 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1611 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1613 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1614 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1617 * Check if an HPET shall be created.
1619 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1620 * when the HPET wants to take over. Thus we have to disable the latter.
1622 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1623 /* In order to set property, here not using sysbus_try_create_simple */
1624 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1626 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1627 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1630 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1633 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1635 qdev_init_nofail(hpet
);
1636 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1638 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1639 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1642 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1643 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1646 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
1648 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1650 if (!xen_enabled() && has_pit
) {
1651 if (kvm_pit_in_kernel()) {
1652 pit
= kvm_pit_init(isa_bus
, 0x40);
1654 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1657 /* connect PIT to output control line of the HPET */
1658 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1660 pcspk_init(isa_bus
, pit
);
1663 i8257_dma_init(isa_bus
, 0);
1666 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
1669 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1673 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1674 for (i
= 0; i
< nb_nics
; i
++) {
1675 NICInfo
*nd
= &nd_table
[i
];
1676 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1678 if (g_str_equal(model
, "ne2k_isa")) {
1679 pc_init_ne2k_isa(isa_bus
, nd
);
1681 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1684 rom_reset_order_override();
1687 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1693 if (kvm_ioapic_in_kernel()) {
1694 dev
= qdev_create(NULL
, "kvm-ioapic");
1696 dev
= qdev_create(NULL
, "ioapic");
1699 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1700 "ioapic", OBJECT(dev
), NULL
);
1702 qdev_init_nofail(dev
);
1703 d
= SYS_BUS_DEVICE(dev
);
1704 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1706 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1707 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1711 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1714 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1715 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1716 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1717 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
1720 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1721 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1722 * addition to cover this case.
1724 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1726 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1730 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
1731 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1735 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
1736 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
1739 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1740 DeviceState
*dev
, Error
**errp
)
1742 HotplugHandlerClass
*hhc
;
1743 Error
*local_err
= NULL
;
1744 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1745 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1747 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
1753 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
1756 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1757 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
1759 error_propagate(errp
, local_err
);
1762 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1763 DeviceState
*dev
, Error
**errp
)
1765 HotplugHandlerClass
*hhc
;
1766 Error
*local_err
= NULL
;
1767 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1770 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1771 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1772 * addition to cover this case.
1774 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1775 error_setg(&local_err
,
1776 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1780 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1781 error_setg(&local_err
,
1782 "nvdimm device hot unplug is not supported yet.");
1786 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1787 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1790 error_propagate(errp
, local_err
);
1793 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
1794 DeviceState
*dev
, Error
**errp
)
1796 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1797 HotplugHandlerClass
*hhc
;
1798 Error
*local_err
= NULL
;
1800 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1801 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1807 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
1808 object_unparent(OBJECT(dev
));
1811 error_propagate(errp
, local_err
);
1814 static int pc_apic_cmp(const void *a
, const void *b
)
1816 CPUArchId
*apic_a
= (CPUArchId
*)a
;
1817 CPUArchId
*apic_b
= (CPUArchId
*)b
;
1819 return apic_a
->arch_id
- apic_b
->arch_id
;
1822 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1823 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1824 * entry corresponding to CPU's apic_id returns NULL.
1826 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1828 CPUArchId apic_id
, *found_cpu
;
1830 apic_id
.arch_id
= id
;
1831 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
1832 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
1834 if (found_cpu
&& idx
) {
1835 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
1840 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
1841 DeviceState
*dev
, Error
**errp
)
1843 CPUArchId
*found_cpu
;
1844 HotplugHandlerClass
*hhc
;
1845 Error
*local_err
= NULL
;
1846 X86CPU
*cpu
= X86_CPU(dev
);
1847 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1849 if (pcms
->acpi_dev
) {
1850 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1851 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1857 /* increment the number of CPUs */
1860 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1863 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1866 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1867 found_cpu
->cpu
= OBJECT(dev
);
1869 error_propagate(errp
, local_err
);
1871 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1872 DeviceState
*dev
, Error
**errp
)
1875 HotplugHandlerClass
*hhc
;
1876 Error
*local_err
= NULL
;
1877 X86CPU
*cpu
= X86_CPU(dev
);
1878 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1880 if (!pcms
->acpi_dev
) {
1881 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
1885 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1888 error_setg(&local_err
, "Boot CPU is unpluggable");
1892 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1893 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1900 error_propagate(errp
, local_err
);
1904 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
1905 DeviceState
*dev
, Error
**errp
)
1907 CPUArchId
*found_cpu
;
1908 HotplugHandlerClass
*hhc
;
1909 Error
*local_err
= NULL
;
1910 X86CPU
*cpu
= X86_CPU(dev
);
1911 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1913 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1914 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1920 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
1921 found_cpu
->cpu
= NULL
;
1922 object_unparent(OBJECT(dev
));
1924 /* decrement the number of CPUs */
1926 /* Update the number of CPUs in CMOS */
1927 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1928 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1930 error_propagate(errp
, local_err
);
1933 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
1934 DeviceState
*dev
, Error
**errp
)
1938 CPUArchId
*cpu_slot
;
1939 X86CPUTopoInfo topo
;
1940 X86CPU
*cpu
= X86_CPU(dev
);
1941 MachineState
*ms
= MACHINE(hotplug_dev
);
1942 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1944 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
1945 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
1950 /* if APIC ID is not set, set it based on socket/core/thread properties */
1951 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
1952 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
1954 if (cpu
->socket_id
< 0) {
1955 error_setg(errp
, "CPU socket-id is not set");
1957 } else if (cpu
->socket_id
> max_socket
) {
1958 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
1959 cpu
->socket_id
, max_socket
);
1962 if (cpu
->core_id
< 0) {
1963 error_setg(errp
, "CPU core-id is not set");
1965 } else if (cpu
->core_id
> (smp_cores
- 1)) {
1966 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
1967 cpu
->core_id
, smp_cores
- 1);
1970 if (cpu
->thread_id
< 0) {
1971 error_setg(errp
, "CPU thread-id is not set");
1973 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
1974 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
1975 cpu
->thread_id
, smp_threads
- 1);
1979 topo
.pkg_id
= cpu
->socket_id
;
1980 topo
.core_id
= cpu
->core_id
;
1981 topo
.smt_id
= cpu
->thread_id
;
1982 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
1985 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
1987 MachineState
*ms
= MACHINE(pcms
);
1989 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
1990 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1991 " APIC ID %" PRIu32
", valid index range 0:%d",
1992 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
1993 ms
->possible_cpus
->len
- 1);
1997 if (cpu_slot
->cpu
) {
1998 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2003 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2004 * so that machine_query_hotpluggable_cpus would show correct values
2006 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2007 * once -smp refactoring is complete and there will be CPU private
2008 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2009 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2010 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2011 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2012 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2015 cpu
->socket_id
= topo
.pkg_id
;
2017 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2018 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2019 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2022 cpu
->core_id
= topo
.core_id
;
2024 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2025 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2026 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2029 cpu
->thread_id
= topo
.smt_id
;
2031 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2032 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2037 cs
->cpu_index
= idx
;
2039 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2042 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2043 DeviceState
*dev
, Error
**errp
)
2045 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2046 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2047 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2048 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2052 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2053 DeviceState
*dev
, Error
**errp
)
2055 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2056 pc_memory_plug(hotplug_dev
, dev
, errp
);
2057 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2058 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2062 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2063 DeviceState
*dev
, Error
**errp
)
2065 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2066 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2067 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2068 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2070 error_setg(errp
, "acpi: device unplug request for not supported device"
2071 " type: %s", object_get_typename(OBJECT(dev
)));
2075 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2076 DeviceState
*dev
, Error
**errp
)
2078 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2079 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2080 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2081 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2083 error_setg(errp
, "acpi: device unplug for not supported device"
2084 " type: %s", object_get_typename(OBJECT(dev
)));
2088 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2091 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2092 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2093 return HOTPLUG_HANDLER(machine
);
2100 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2101 const char *name
, void *opaque
,
2104 MachineState
*ms
= MACHINE(obj
);
2105 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2107 visit_type_int(v
, name
, &value
, errp
);
2110 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2111 const char *name
, void *opaque
,
2114 PCMachineState
*pcms
= PC_MACHINE(obj
);
2115 uint64_t value
= pcms
->max_ram_below_4g
;
2117 visit_type_size(v
, name
, &value
, errp
);
2120 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2121 const char *name
, void *opaque
,
2124 PCMachineState
*pcms
= PC_MACHINE(obj
);
2125 Error
*error
= NULL
;
2128 visit_type_size(v
, name
, &value
, &error
);
2130 error_propagate(errp
, error
);
2133 if (value
> 4 * GiB
) {
2135 "Machine option 'max-ram-below-4g=%"PRIu64
2136 "' expects size less than or equal to 4G", value
);
2137 error_propagate(errp
, error
);
2141 if (value
< 1 * MiB
) {
2142 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2143 "BIOS may not work with less than 1MiB", value
);
2146 pcms
->max_ram_below_4g
= value
;
2149 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2150 void *opaque
, Error
**errp
)
2152 PCMachineState
*pcms
= PC_MACHINE(obj
);
2153 OnOffAuto vmport
= pcms
->vmport
;
2155 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2158 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2159 void *opaque
, Error
**errp
)
2161 PCMachineState
*pcms
= PC_MACHINE(obj
);
2163 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2166 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2168 bool smm_available
= false;
2170 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2174 if (tcg_enabled() || qtest_enabled()) {
2175 smm_available
= true;
2176 } else if (kvm_enabled()) {
2177 smm_available
= kvm_has_smm();
2180 if (smm_available
) {
2184 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2185 error_report("System Management Mode not supported by this hypervisor.");
2191 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2192 void *opaque
, Error
**errp
)
2194 PCMachineState
*pcms
= PC_MACHINE(obj
);
2195 OnOffAuto smm
= pcms
->smm
;
2197 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2200 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2201 void *opaque
, Error
**errp
)
2203 PCMachineState
*pcms
= PC_MACHINE(obj
);
2205 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2208 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2210 PCMachineState
*pcms
= PC_MACHINE(obj
);
2212 return pcms
->acpi_nvdimm_state
.is_enabled
;
2215 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2217 PCMachineState
*pcms
= PC_MACHINE(obj
);
2219 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2222 static char *pc_machine_get_nvdimm_persistence(Object
*obj
, Error
**errp
)
2224 PCMachineState
*pcms
= PC_MACHINE(obj
);
2226 return g_strdup(pcms
->acpi_nvdimm_state
.persistence_string
);
2229 static void pc_machine_set_nvdimm_persistence(Object
*obj
, const char *value
,
2232 PCMachineState
*pcms
= PC_MACHINE(obj
);
2233 AcpiNVDIMMState
*nvdimm_state
= &pcms
->acpi_nvdimm_state
;
2235 if (strcmp(value
, "cpu") == 0)
2236 nvdimm_state
->persistence
= 3;
2237 else if (strcmp(value
, "mem-ctrl") == 0)
2238 nvdimm_state
->persistence
= 2;
2240 error_setg(errp
, "-machine nvdimm-persistence=%s: unsupported option",
2245 g_free(nvdimm_state
->persistence_string
);
2246 nvdimm_state
->persistence_string
= g_strdup(value
);
2249 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2251 PCMachineState
*pcms
= PC_MACHINE(obj
);
2253 return pcms
->smbus_enabled
;
2256 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2258 PCMachineState
*pcms
= PC_MACHINE(obj
);
2260 pcms
->smbus_enabled
= value
;
2263 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2265 PCMachineState
*pcms
= PC_MACHINE(obj
);
2267 return pcms
->sata_enabled
;
2270 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2272 PCMachineState
*pcms
= PC_MACHINE(obj
);
2274 pcms
->sata_enabled
= value
;
2277 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2279 PCMachineState
*pcms
= PC_MACHINE(obj
);
2281 return pcms
->pit_enabled
;
2284 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2286 PCMachineState
*pcms
= PC_MACHINE(obj
);
2288 pcms
->pit_enabled
= value
;
2291 static void pc_machine_initfn(Object
*obj
)
2293 PCMachineState
*pcms
= PC_MACHINE(obj
);
2295 pcms
->max_ram_below_4g
= 0; /* use default */
2296 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2297 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2298 /* nvdimm is disabled on default. */
2299 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2300 /* acpi build is enabled by default if machine supports it */
2301 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2302 pcms
->smbus_enabled
= true;
2303 pcms
->sata_enabled
= true;
2304 pcms
->pit_enabled
= true;
2307 static void pc_machine_reset(void)
2312 qemu_devices_reset();
2314 /* Reset APIC after devices have been reset to cancel
2315 * any changes that qemu_devices_reset() might have done.
2320 if (cpu
->apic_state
) {
2321 device_reset(cpu
->apic_state
);
2326 static CpuInstanceProperties
2327 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2329 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2330 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2332 assert(cpu_index
< possible_cpus
->len
);
2333 return possible_cpus
->cpus
[cpu_index
].props
;
2336 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2338 X86CPUTopoInfo topo
;
2340 assert(idx
< ms
->possible_cpus
->len
);
2341 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2342 smp_cores
, smp_threads
, &topo
);
2343 return topo
.pkg_id
% nb_numa_nodes
;
2346 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2350 if (ms
->possible_cpus
) {
2352 * make sure that max_cpus hasn't changed since the first use, i.e.
2353 * -smp hasn't been parsed after it
2355 assert(ms
->possible_cpus
->len
== max_cpus
);
2356 return ms
->possible_cpus
;
2359 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2360 sizeof(CPUArchId
) * max_cpus
);
2361 ms
->possible_cpus
->len
= max_cpus
;
2362 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2363 X86CPUTopoInfo topo
;
2365 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2366 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2367 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2368 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2369 smp_cores
, smp_threads
, &topo
);
2370 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2371 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2372 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2373 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2374 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2375 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2377 return ms
->possible_cpus
;
2380 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2382 /* cpu index isn't used */
2386 X86CPU
*cpu
= X86_CPU(cs
);
2388 if (!cpu
->apic_state
) {
2389 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2391 apic_deliver_nmi(cpu
->apic_state
);
2396 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2398 MachineClass
*mc
= MACHINE_CLASS(oc
);
2399 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2400 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2401 NMIClass
*nc
= NMI_CLASS(oc
);
2403 pcmc
->pci_enabled
= true;
2404 pcmc
->has_acpi_build
= true;
2405 pcmc
->rsdp_in_ram
= true;
2406 pcmc
->smbios_defaults
= true;
2407 pcmc
->smbios_uuid_encoded
= true;
2408 pcmc
->gigabyte_align
= true;
2409 pcmc
->has_reserved_memory
= true;
2410 pcmc
->kvmclock_enabled
= true;
2411 pcmc
->enforce_aligned_dimm
= true;
2412 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2413 * to be used at the moment, 32K should be enough for a while. */
2414 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2415 pcmc
->save_tsc_khz
= true;
2416 pcmc
->linuxboot_dma_enabled
= true;
2417 assert(!mc
->get_hotplug_handler
);
2418 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
2419 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2420 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2421 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2422 mc
->auto_enable_numa_with_memhp
= true;
2423 mc
->has_hotpluggable_cpus
= true;
2424 mc
->default_boot_order
= "cad";
2425 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2426 mc
->block_default_type
= IF_IDE
;
2428 mc
->reset
= pc_machine_reset
;
2429 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2430 hc
->plug
= pc_machine_device_plug_cb
;
2431 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2432 hc
->unplug
= pc_machine_device_unplug_cb
;
2433 nc
->nmi_monitor_handler
= x86_nmi
;
2434 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2436 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2437 pc_machine_get_device_memory_region_size
, NULL
,
2438 NULL
, NULL
, &error_abort
);
2440 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2441 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2442 NULL
, NULL
, &error_abort
);
2444 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2445 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2447 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2448 pc_machine_get_smm
, pc_machine_set_smm
,
2449 NULL
, NULL
, &error_abort
);
2450 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2451 "Enable SMM (pc & q35)", &error_abort
);
2453 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2454 pc_machine_get_vmport
, pc_machine_set_vmport
,
2455 NULL
, NULL
, &error_abort
);
2456 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2457 "Enable vmport (pc & q35)", &error_abort
);
2459 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
2460 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
2462 object_class_property_add_str(oc
, PC_MACHINE_NVDIMM_PERSIST
,
2463 pc_machine_get_nvdimm_persistence
,
2464 pc_machine_set_nvdimm_persistence
, &error_abort
);
2466 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2467 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2469 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2470 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2472 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2473 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2476 static const TypeInfo pc_machine_info
= {
2477 .name
= TYPE_PC_MACHINE
,
2478 .parent
= TYPE_MACHINE
,
2480 .instance_size
= sizeof(PCMachineState
),
2481 .instance_init
= pc_machine_initfn
,
2482 .class_size
= sizeof(PCMachineClass
),
2483 .class_init
= pc_machine_class_init
,
2484 .interfaces
= (InterfaceInfo
[]) {
2485 { TYPE_HOTPLUG_HANDLER
},
2491 static void pc_machine_register_types(void)
2493 type_register_static(&pc_machine_info
);
2496 type_init(pc_machine_register_types
)