2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/cpu/icc_bus.h"
57 #include "hw/boards.h"
58 #include "hw/pci/pci_host.h"
60 /* debug PC/ISA interrupts */
64 #define DPRINTF(fmt, ...) \
65 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
67 #define DPRINTF(fmt, ...)
70 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
71 #define ACPI_DATA_SIZE 0x10000
72 #define BIOS_CFG_IOPORT 0x510
73 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
74 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
75 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
76 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
77 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
79 #define E820_NR_ENTRIES 16
85 } QEMU_PACKED
__attribute((__aligned__(4)));
89 struct e820_entry entry
[E820_NR_ENTRIES
];
90 } QEMU_PACKED
__attribute((__aligned__(4)));
92 static struct e820_table e820_table
;
93 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
95 void gsi_handler(void *opaque
, int n
, int level
)
99 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
100 if (n
< ISA_NUM_IRQS
) {
101 qemu_set_irq(s
->i8259_irq
[n
], level
);
103 qemu_set_irq(s
->ioapic_irq
[n
], level
);
106 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
111 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
113 return 0xffffffffffffffffULL
;
116 /* MSDOS compatibility mode FPU exception support */
117 static qemu_irq ferr_irq
;
119 void pc_register_ferr_irq(qemu_irq irq
)
124 /* XXX: add IGNNE support */
125 void cpu_set_ferr(CPUX86State
*s
)
127 qemu_irq_raise(ferr_irq
);
130 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
133 qemu_irq_lower(ferr_irq
);
136 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
138 return 0xffffffffffffffffULL
;
142 uint64_t cpu_get_tsc(CPUX86State
*env
)
144 return cpu_get_ticks();
149 static cpu_set_smm_t smm_set
;
150 static void *smm_arg
;
152 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
154 assert(smm_set
== NULL
);
155 assert(smm_arg
== NULL
);
160 void cpu_smm_update(CPUX86State
*env
)
162 if (smm_set
&& smm_arg
&& CPU(x86_env_get_cpu(env
)) == first_cpu
) {
163 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
169 int cpu_get_pic_interrupt(CPUX86State
*env
)
173 intno
= apic_get_interrupt(env
->apic_state
);
177 /* read the irq from the PIC */
178 if (!apic_accept_pic_intr(env
->apic_state
)) {
182 intno
= pic_read_irq(isa_pic
);
186 static void pic_irq_request(void *opaque
, int irq
, int level
)
188 CPUState
*cs
= first_cpu
;
189 X86CPU
*cpu
= X86_CPU(cs
);
190 CPUX86State
*env
= &cpu
->env
;
192 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
193 if (env
->apic_state
) {
197 if (apic_accept_pic_intr(env
->apic_state
)) {
198 apic_deliver_pic_intr(env
->apic_state
, level
);
203 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
205 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
210 /* PC cmos mappings */
212 #define REG_EQUIPMENT_BYTE 0x14
214 static int cmos_get_fd_drive_type(FDriveType fd0
)
220 /* 1.44 Mb 3"5 drive */
224 /* 2.88 Mb 3"5 drive */
228 /* 1.2 Mb 5"5 drive */
231 case FDRIVE_DRV_NONE
:
239 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
240 int16_t cylinders
, int8_t heads
, int8_t sectors
)
242 rtc_set_memory(s
, type_ofs
, 47);
243 rtc_set_memory(s
, info_ofs
, cylinders
);
244 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
245 rtc_set_memory(s
, info_ofs
+ 2, heads
);
246 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
247 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
248 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
249 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
250 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
251 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
254 /* convert boot_device letter to something recognizable by the bios */
255 static int boot_device2nibble(char boot_device
)
257 switch(boot_device
) {
260 return 0x01; /* floppy boot */
262 return 0x02; /* hard drive boot */
264 return 0x03; /* CD-ROM boot */
266 return 0x04; /* Network boot */
271 static int set_boot_dev(ISADevice
*s
, const char *boot_device
)
273 #define PC_MAX_BOOT_DEVICES 3
274 int nbds
, bds
[3] = { 0, };
277 nbds
= strlen(boot_device
);
278 if (nbds
> PC_MAX_BOOT_DEVICES
) {
279 error_report("Too many boot devices for PC");
282 for (i
= 0; i
< nbds
; i
++) {
283 bds
[i
] = boot_device2nibble(boot_device
[i
]);
285 error_report("Invalid boot device for PC: '%c'",
290 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
291 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
295 static int pc_boot_set(void *opaque
, const char *boot_device
)
297 return set_boot_dev(opaque
, boot_device
);
300 typedef struct pc_cmos_init_late_arg
{
301 ISADevice
*rtc_state
;
303 } pc_cmos_init_late_arg
;
305 static void pc_cmos_init_late(void *opaque
)
307 pc_cmos_init_late_arg
*arg
= opaque
;
308 ISADevice
*s
= arg
->rtc_state
;
310 int8_t heads
, sectors
;
315 if (ide_get_geometry(arg
->idebus
[0], 0,
316 &cylinders
, &heads
, §ors
) >= 0) {
317 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
320 if (ide_get_geometry(arg
->idebus
[0], 1,
321 &cylinders
, &heads
, §ors
) >= 0) {
322 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
325 rtc_set_memory(s
, 0x12, val
);
328 for (i
= 0; i
< 4; i
++) {
329 /* NOTE: ide_get_geometry() returns the physical
330 geometry. It is always such that: 1 <= sects <= 63, 1
331 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
332 geometry can be different if a translation is done. */
333 if (ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
334 &cylinders
, &heads
, §ors
) >= 0) {
335 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
336 assert((trans
& ~3) == 0);
337 val
|= trans
<< (i
* 2);
340 rtc_set_memory(s
, 0x39, val
);
342 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
345 typedef struct RTCCPUHotplugArg
{
346 Notifier cpu_added_notifier
;
347 ISADevice
*rtc_state
;
350 static void rtc_notify_cpu_added(Notifier
*notifier
, void *data
)
352 RTCCPUHotplugArg
*arg
= container_of(notifier
, RTCCPUHotplugArg
,
354 ISADevice
*s
= arg
->rtc_state
;
356 /* increment the number of CPUs */
357 rtc_set_memory(s
, 0x5f, rtc_get_memory(s
, 0x5f) + 1);
360 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
361 const char *boot_device
,
362 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
366 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
367 static pc_cmos_init_late_arg arg
;
368 static RTCCPUHotplugArg cpu_hotplug_cb
;
370 /* various important CMOS locations needed by PC/Bochs bios */
373 /* base memory (first MiB) */
374 val
= MIN(ram_size
/ 1024, 640);
375 rtc_set_memory(s
, 0x15, val
);
376 rtc_set_memory(s
, 0x16, val
>> 8);
377 /* extended memory (next 64MiB) */
378 if (ram_size
> 1024 * 1024) {
379 val
= (ram_size
- 1024 * 1024) / 1024;
385 rtc_set_memory(s
, 0x17, val
);
386 rtc_set_memory(s
, 0x18, val
>> 8);
387 rtc_set_memory(s
, 0x30, val
);
388 rtc_set_memory(s
, 0x31, val
>> 8);
389 /* memory between 16MiB and 4GiB */
390 if (ram_size
> 16 * 1024 * 1024) {
391 val
= (ram_size
- 16 * 1024 * 1024) / 65536;
397 rtc_set_memory(s
, 0x34, val
);
398 rtc_set_memory(s
, 0x35, val
>> 8);
399 /* memory above 4GiB */
400 val
= above_4g_mem_size
/ 65536;
401 rtc_set_memory(s
, 0x5b, val
);
402 rtc_set_memory(s
, 0x5c, val
>> 8);
403 rtc_set_memory(s
, 0x5d, val
>> 16);
405 /* set the number of CPU */
406 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
407 /* init CPU hotplug notifier */
408 cpu_hotplug_cb
.rtc_state
= s
;
409 cpu_hotplug_cb
.cpu_added_notifier
.notify
= rtc_notify_cpu_added
;
410 qemu_register_cpu_added_notifier(&cpu_hotplug_cb
.cpu_added_notifier
);
412 if (set_boot_dev(s
, boot_device
)) {
418 for (i
= 0; i
< 2; i
++) {
419 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
422 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
423 cmos_get_fd_drive_type(fd_type
[1]);
424 rtc_set_memory(s
, 0x10, val
);
428 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
431 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
438 val
|= 0x01; /* 1 drive, ready for boot */
441 val
|= 0x41; /* 2 drives, ready for boot */
444 val
|= 0x02; /* FPU is there */
445 val
|= 0x04; /* PS/2 mouse installed */
446 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
450 arg
.idebus
[0] = idebus0
;
451 arg
.idebus
[1] = idebus1
;
452 qemu_register_reset(pc_cmos_init_late
, &arg
);
455 #define TYPE_PORT92 "port92"
456 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
458 /* port 92 stuff: could be split off */
459 typedef struct Port92State
{
460 ISADevice parent_obj
;
467 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
470 Port92State
*s
= opaque
;
472 DPRINTF("port92: write 0x%02x\n", val
);
474 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
476 qemu_system_reset_request();
480 static uint64_t port92_read(void *opaque
, hwaddr addr
,
483 Port92State
*s
= opaque
;
487 DPRINTF("port92: read 0x%02x\n", ret
);
491 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
493 Port92State
*s
= PORT92(dev
);
495 s
->a20_out
= a20_out
;
498 static const VMStateDescription vmstate_port92_isa
= {
501 .minimum_version_id
= 1,
502 .minimum_version_id_old
= 1,
503 .fields
= (VMStateField
[]) {
504 VMSTATE_UINT8(outport
, Port92State
),
505 VMSTATE_END_OF_LIST()
509 static void port92_reset(DeviceState
*d
)
511 Port92State
*s
= PORT92(d
);
516 static const MemoryRegionOps port92_ops
= {
518 .write
= port92_write
,
520 .min_access_size
= 1,
521 .max_access_size
= 1,
523 .endianness
= DEVICE_LITTLE_ENDIAN
,
526 static void port92_initfn(Object
*obj
)
528 Port92State
*s
= PORT92(obj
);
530 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
535 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
537 ISADevice
*isadev
= ISA_DEVICE(dev
);
538 Port92State
*s
= PORT92(dev
);
540 isa_register_ioport(isadev
, &s
->io
, 0x92);
543 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
545 DeviceClass
*dc
= DEVICE_CLASS(klass
);
548 dc
->realize
= port92_realizefn
;
549 dc
->reset
= port92_reset
;
550 dc
->vmsd
= &vmstate_port92_isa
;
553 static const TypeInfo port92_info
= {
555 .parent
= TYPE_ISA_DEVICE
,
556 .instance_size
= sizeof(Port92State
),
557 .instance_init
= port92_initfn
,
558 .class_init
= port92_class_initfn
,
561 static void port92_register_types(void)
563 type_register_static(&port92_info
);
566 type_init(port92_register_types
)
568 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
570 X86CPU
*cpu
= opaque
;
572 /* XXX: send to all CPUs ? */
573 /* XXX: add logic to handle multiple A20 line sources */
574 x86_cpu_set_a20(cpu
, level
);
577 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
579 int index
= le32_to_cpu(e820_table
.count
);
580 struct e820_entry
*entry
;
582 if (index
>= E820_NR_ENTRIES
)
584 entry
= &e820_table
.entry
[index
++];
586 entry
->address
= cpu_to_le64(address
);
587 entry
->length
= cpu_to_le64(length
);
588 entry
->type
= cpu_to_le32(type
);
590 e820_table
.count
= cpu_to_le32(index
);
594 /* Calculates the limit to CPU APIC ID values
596 * This function returns the limit for the APIC ID value, so that all
597 * CPU APIC IDs are < pc_apic_id_limit().
599 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
601 static unsigned int pc_apic_id_limit(unsigned int max_cpus
)
603 return x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
606 static FWCfgState
*bochs_bios_init(void)
609 uint8_t *smbios_table
;
611 uint64_t *numa_fw_cfg
;
613 unsigned int apic_id_limit
= pc_apic_id_limit(max_cpus
);
615 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
616 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
618 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
619 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
620 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
621 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
624 * So, this means we must not use max_cpus, here, but the maximum possible
625 * APIC ID value, plus one.
627 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
628 * the APIC ID, not the "CPU index"
630 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)apic_id_limit
);
631 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
632 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
633 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
634 acpi_tables
, acpi_tables_len
);
635 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
637 smbios_table
= smbios_get_table(&smbios_len
);
639 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
640 smbios_table
, smbios_len
);
641 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
642 &e820_table
, sizeof(e820_table
));
644 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
645 /* allocate memory for the NUMA channel: one (64bit) word for the number
646 * of nodes, one word for each VCPU->node and one word for each node to
647 * hold the amount of memory.
649 numa_fw_cfg
= g_new0(uint64_t, 1 + apic_id_limit
+ nb_numa_nodes
);
650 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
651 for (i
= 0; i
< max_cpus
; i
++) {
652 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
653 assert(apic_id
< apic_id_limit
);
654 for (j
= 0; j
< nb_numa_nodes
; j
++) {
655 if (test_bit(i
, node_cpumask
[j
])) {
656 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(j
);
661 for (i
= 0; i
< nb_numa_nodes
; i
++) {
662 numa_fw_cfg
[apic_id_limit
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
664 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
665 (1 + apic_id_limit
+ nb_numa_nodes
) *
666 sizeof(*numa_fw_cfg
));
671 static long get_file_size(FILE *f
)
675 /* XXX: on Unix systems, using fstat() probably makes more sense */
678 fseek(f
, 0, SEEK_END
);
680 fseek(f
, where
, SEEK_SET
);
685 static void load_linux(FWCfgState
*fw_cfg
,
686 const char *kernel_filename
,
687 const char *initrd_filename
,
688 const char *kernel_cmdline
,
692 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
694 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
695 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
699 /* Align to 16 bytes as a paranoia measure */
700 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
702 /* load the kernel header */
703 f
= fopen(kernel_filename
, "rb");
704 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
705 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
706 MIN(ARRAY_SIZE(header
), kernel_size
)) {
707 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
708 kernel_filename
, strerror(errno
));
712 /* kernel protocol version */
714 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
716 if (ldl_p(header
+0x202) == 0x53726448) {
717 protocol
= lduw_p(header
+0x206);
719 /* This looks like a multiboot kernel. If it is, let's stop
720 treating it like a Linux kernel. */
721 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
722 kernel_cmdline
, kernel_size
, header
)) {
728 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
731 cmdline_addr
= 0x9a000 - cmdline_size
;
733 } else if (protocol
< 0x202) {
734 /* High but ancient kernel */
736 cmdline_addr
= 0x9a000 - cmdline_size
;
737 prot_addr
= 0x100000;
739 /* High and recent kernel */
741 cmdline_addr
= 0x20000;
742 prot_addr
= 0x100000;
747 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
748 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
749 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
755 /* highest address for loading the initrd */
756 if (protocol
>= 0x203) {
757 initrd_max
= ldl_p(header
+0x22c);
759 initrd_max
= 0x37ffffff;
762 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
763 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
765 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
766 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
767 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
769 if (protocol
>= 0x202) {
770 stl_p(header
+0x228, cmdline_addr
);
772 stw_p(header
+0x20, 0xA33F);
773 stw_p(header
+0x22, cmdline_addr
-real_addr
);
776 /* handle vga= parameter */
777 vmode
= strstr(kernel_cmdline
, "vga=");
779 unsigned int video_mode
;
782 if (!strncmp(vmode
, "normal", 6)) {
784 } else if (!strncmp(vmode
, "ext", 3)) {
786 } else if (!strncmp(vmode
, "ask", 3)) {
789 video_mode
= strtol(vmode
, NULL
, 0);
791 stw_p(header
+0x1fa, video_mode
);
795 /* High nybble = B reserved for QEMU; low nybble is revision number.
796 If this code is substantially changed, you may want to consider
797 incrementing the revision. */
798 if (protocol
>= 0x200) {
799 header
[0x210] = 0xB0;
802 if (protocol
>= 0x201) {
803 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
804 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
808 if (initrd_filename
) {
809 if (protocol
< 0x200) {
810 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
814 initrd_size
= get_image_size(initrd_filename
);
815 if (initrd_size
< 0) {
816 fprintf(stderr
, "qemu: error reading initrd %s\n",
821 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
823 initrd_data
= g_malloc(initrd_size
);
824 load_image(initrd_filename
, initrd_data
);
826 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
827 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
828 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
830 stl_p(header
+0x218, initrd_addr
);
831 stl_p(header
+0x21c, initrd_size
);
834 /* load kernel and setup */
835 setup_size
= header
[0x1f1];
836 if (setup_size
== 0) {
839 setup_size
= (setup_size
+1)*512;
840 kernel_size
-= setup_size
;
842 setup
= g_malloc(setup_size
);
843 kernel
= g_malloc(kernel_size
);
844 fseek(f
, 0, SEEK_SET
);
845 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
846 fprintf(stderr
, "fread() failed\n");
849 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
850 fprintf(stderr
, "fread() failed\n");
854 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
856 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
857 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
858 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
860 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
861 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
862 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
864 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
865 option_rom
[nb_option_roms
].bootindex
= 0;
869 #define NE2000_NB_MAX 6
871 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
873 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
875 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
876 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
878 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
880 static int nb_ne2k
= 0;
882 if (nb_ne2k
== NE2000_NB_MAX
)
884 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
885 ne2000_irq
[nb_ne2k
], nd
);
889 DeviceState
*cpu_get_current_apic(void)
892 X86CPU
*cpu
= X86_CPU(current_cpu
);
893 return cpu
->env
.apic_state
;
899 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
901 X86CPU
*cpu
= opaque
;
904 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
908 static X86CPU
*pc_new_cpu(const char *cpu_model
, int64_t apic_id
,
909 DeviceState
*icc_bridge
, Error
**errp
)
912 Error
*local_err
= NULL
;
914 cpu
= cpu_x86_create(cpu_model
, icc_bridge
, &local_err
);
915 if (local_err
!= NULL
) {
916 error_propagate(errp
, local_err
);
920 object_property_set_int(OBJECT(cpu
), apic_id
, "apic-id", &local_err
);
921 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
924 error_propagate(errp
, local_err
);
925 object_unref(OBJECT(cpu
));
931 static const char *current_cpu_model
;
933 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
935 DeviceState
*icc_bridge
;
936 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
939 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
943 if (cpu_exists(apic_id
)) {
944 error_setg(errp
, "Unable to add CPU: %" PRIi64
945 ", it already exists", id
);
949 if (id
>= max_cpus
) {
950 error_setg(errp
, "Unable to add CPU: %" PRIi64
951 ", max allowed: %d", id
, max_cpus
- 1);
955 icc_bridge
= DEVICE(object_resolve_path_type("icc-bridge",
956 TYPE_ICC_BRIDGE
, NULL
));
957 pc_new_cpu(current_cpu_model
, apic_id
, icc_bridge
, errp
);
960 void pc_cpus_init(const char *cpu_model
, DeviceState
*icc_bridge
)
967 if (cpu_model
== NULL
) {
969 cpu_model
= "qemu64";
971 cpu_model
= "qemu32";
974 current_cpu_model
= cpu_model
;
976 for (i
= 0; i
< smp_cpus
; i
++) {
977 cpu
= pc_new_cpu(cpu_model
, x86_cpu_apic_id_from_index(i
),
980 error_report("%s", error_get_pretty(error
));
986 /* map APIC MMIO area if CPU has APIC */
987 if (cpu
&& cpu
->env
.apic_state
) {
988 /* XXX: what if the base changes? */
989 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge
), 0,
990 APIC_DEFAULT_ADDRESS
, 0x1000);
994 /* pci-info ROM file. Little endian format */
995 typedef struct PcRomPciInfo
{
1002 static void pc_fw_cfg_guest_info(PcGuestInfo
*guest_info
)
1006 bool ambiguous
= false;
1008 if (!guest_info
->has_pci_info
|| !guest_info
->fw_cfg
) {
1011 pci_info
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1012 g_assert(!ambiguous
);
1017 info
= g_malloc(sizeof *info
);
1018 info
->w32_min
= cpu_to_le64(object_property_get_int(pci_info
,
1019 PCI_HOST_PROP_PCI_HOLE_START
, NULL
));
1020 info
->w32_max
= cpu_to_le64(object_property_get_int(pci_info
,
1021 PCI_HOST_PROP_PCI_HOLE_END
, NULL
));
1022 info
->w64_min
= cpu_to_le64(object_property_get_int(pci_info
,
1023 PCI_HOST_PROP_PCI_HOLE64_START
, NULL
));
1024 info
->w64_max
= cpu_to_le64(object_property_get_int(pci_info
,
1025 PCI_HOST_PROP_PCI_HOLE64_END
, NULL
));
1026 /* Pass PCI hole info to guest via a side channel.
1027 * Required so guest PCI enumeration does the right thing. */
1028 fw_cfg_add_file(guest_info
->fw_cfg
, "etc/pci-info", info
, sizeof *info
);
1031 typedef struct PcGuestInfoState
{
1033 Notifier machine_done
;
1037 void pc_guest_info_machine_done(Notifier
*notifier
, void *data
)
1039 PcGuestInfoState
*guest_info_state
= container_of(notifier
,
1042 pc_fw_cfg_guest_info(&guest_info_state
->info
);
1045 PcGuestInfo
*pc_guest_info_init(ram_addr_t below_4g_mem_size
,
1046 ram_addr_t above_4g_mem_size
)
1048 PcGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1049 PcGuestInfo
*guest_info
= &guest_info_state
->info
;
1052 guest_info
->ram_size
= below_4g_mem_size
+ above_4g_mem_size
;
1053 guest_info
->apic_id_limit
= pc_apic_id_limit(max_cpus
);
1054 guest_info
->apic_xrupt_override
= kvm_allows_irq0_override();
1055 guest_info
->numa_nodes
= nb_numa_nodes
;
1056 guest_info
->node_mem
= g_memdup(node_mem
, guest_info
->numa_nodes
*
1057 sizeof *guest_info
->node_mem
);
1058 guest_info
->node_cpu
= g_malloc0(guest_info
->apic_id_limit
*
1059 sizeof *guest_info
->node_cpu
);
1061 for (i
= 0; i
< max_cpus
; i
++) {
1062 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
1063 assert(apic_id
< guest_info
->apic_id_limit
);
1064 for (j
= 0; j
< nb_numa_nodes
; j
++) {
1065 if (test_bit(i
, node_cpumask
[j
])) {
1066 guest_info
->node_cpu
[apic_id
] = j
;
1072 guest_info_state
->machine_done
.notify
= pc_guest_info_machine_done
;
1073 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1077 void pc_init_pci64_hole(PcPciInfo
*pci_info
, uint64_t pci_hole64_start
,
1078 uint64_t pci_hole64_size
)
1080 if ((sizeof(hwaddr
) == 4) || (!pci_hole64_size
)) {
1084 * BIOS does not set MTRR entries for the 64 bit window, so no need to
1085 * align address to power of two. Align address at 1G, this makes sure
1086 * it can be exactly covered with a PAT entry even when using huge
1089 pci_info
->w64
.begin
= ROUND_UP(pci_hole64_start
, 0x1ULL
<< 30);
1090 pci_info
->w64
.end
= pci_info
->w64
.begin
+ pci_hole64_size
;
1091 assert(pci_info
->w64
.begin
<= pci_info
->w64
.end
);
1094 void pc_acpi_init(const char *default_dsdt
)
1098 if (acpi_tables
!= NULL
) {
1099 /* manually set via -acpitable, leave it alone */
1103 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1104 if (filename
== NULL
) {
1105 fprintf(stderr
, "WARNING: failed to find %s\n", default_dsdt
);
1111 arg
= g_strdup_printf("file=%s", filename
);
1113 /* creates a deep copy of "arg" */
1114 opts
= qemu_opts_parse(qemu_find_opts("acpi"), arg
, 0);
1115 g_assert(opts
!= NULL
);
1117 acpi_table_add(opts
, &err
);
1119 error_report("WARNING: failed to load %s: %s", filename
,
1120 error_get_pretty(err
));
1128 FWCfgState
*pc_memory_init(MemoryRegion
*system_memory
,
1129 const char *kernel_filename
,
1130 const char *kernel_cmdline
,
1131 const char *initrd_filename
,
1132 ram_addr_t below_4g_mem_size
,
1133 ram_addr_t above_4g_mem_size
,
1134 MemoryRegion
*rom_memory
,
1135 MemoryRegion
**ram_memory
,
1136 PcGuestInfo
*guest_info
)
1139 MemoryRegion
*ram
, *option_rom_mr
;
1140 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1143 linux_boot
= (kernel_filename
!= NULL
);
1145 /* Allocate RAM. We allocate it as a single memory region and use
1146 * aliases to address portions of it, mostly for backwards compatibility
1147 * with older qemus that used qemu_ram_alloc().
1149 ram
= g_malloc(sizeof(*ram
));
1150 memory_region_init_ram(ram
, NULL
, "pc.ram",
1151 below_4g_mem_size
+ above_4g_mem_size
);
1152 vmstate_register_ram_global(ram
);
1154 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1155 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1156 0, below_4g_mem_size
);
1157 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1158 if (above_4g_mem_size
> 0) {
1159 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1160 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1161 below_4g_mem_size
, above_4g_mem_size
);
1162 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1167 /* Initialize PC system firmware */
1168 pc_system_firmware_init(rom_memory
, guest_info
->isapc_ram_fw
);
1170 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1171 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
);
1172 vmstate_register_ram_global(option_rom_mr
);
1173 memory_region_add_subregion_overlap(rom_memory
,
1178 fw_cfg
= bochs_bios_init();
1182 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
1185 for (i
= 0; i
< nb_option_roms
; i
++) {
1186 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1188 guest_info
->fw_cfg
= fw_cfg
;
1192 qemu_irq
*pc_allocate_cpu_irq(void)
1194 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1197 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1199 DeviceState
*dev
= NULL
;
1202 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1203 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1204 } else if (isa_bus
) {
1205 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1206 dev
= isadev
? DEVICE(isadev
) : NULL
;
1211 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1213 CPUState
*cpu
= current_cpu
;
1220 static const MemoryRegionOps ioport80_io_ops
= {
1221 .write
= ioport80_write
,
1222 .read
= ioport80_read
,
1223 .endianness
= DEVICE_NATIVE_ENDIAN
,
1225 .min_access_size
= 1,
1226 .max_access_size
= 1,
1230 static const MemoryRegionOps ioportF0_io_ops
= {
1231 .write
= ioportF0_write
,
1232 .read
= ioportF0_read
,
1233 .endianness
= DEVICE_NATIVE_ENDIAN
,
1235 .min_access_size
= 1,
1236 .max_access_size
= 1,
1240 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1241 ISADevice
**rtc_state
,
1246 DriveInfo
*fd
[MAX_FD
];
1247 DeviceState
*hpet
= NULL
;
1248 int pit_isa_irq
= 0;
1249 qemu_irq pit_alt_irq
= NULL
;
1250 qemu_irq rtc_irq
= NULL
;
1252 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1253 qemu_irq
*cpu_exit_irq
;
1254 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1255 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1257 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1258 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1260 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1261 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1264 * Check if an HPET shall be created.
1266 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1267 * when the HPET wants to take over. Thus we have to disable the latter.
1269 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1270 hpet
= sysbus_try_create_simple("hpet", HPET_BASE
, NULL
);
1273 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1274 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1277 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1278 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1281 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1283 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1285 if (!xen_enabled()) {
1286 if (kvm_irqchip_in_kernel()) {
1287 pit
= kvm_pit_init(isa_bus
, 0x40);
1289 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1292 /* connect PIT to output control line of the HPET */
1293 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1295 pcspk_init(isa_bus
, pit
);
1298 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1299 if (serial_hds
[i
]) {
1300 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1304 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1305 if (parallel_hds
[i
]) {
1306 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1310 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1311 i8042
= isa_create_simple(isa_bus
, "i8042");
1312 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1314 vmport_init(isa_bus
);
1315 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1320 DeviceState
*dev
= DEVICE(vmmouse
);
1321 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1322 qdev_init_nofail(dev
);
1324 port92
= isa_create_simple(isa_bus
, "port92");
1325 port92_init(port92
, &a20_line
[1]);
1327 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1328 DMA_init(0, cpu_exit_irq
);
1330 for(i
= 0; i
< MAX_FD
; i
++) {
1331 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1333 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1336 void pc_nic_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1340 for (i
= 0; i
< nb_nics
; i
++) {
1341 NICInfo
*nd
= &nd_table
[i
];
1343 if (!pci_bus
|| (nd
->model
&& strcmp(nd
->model
, "ne2k_isa") == 0)) {
1344 pc_init_ne2k_isa(isa_bus
, nd
);
1346 pci_nic_init_nofail(nd
, pci_bus
, "e1000", NULL
);
1351 void pc_pci_device_init(PCIBus
*pci_bus
)
1356 max_bus
= drive_get_max_bus(IF_SCSI
);
1357 for (bus
= 0; bus
<= max_bus
; bus
++) {
1358 pci_create_simple(pci_bus
, -1, "lsi53c895a");
1362 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1368 if (kvm_irqchip_in_kernel()) {
1369 dev
= qdev_create(NULL
, "kvm-ioapic");
1371 dev
= qdev_create(NULL
, "ioapic");
1374 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1375 "ioapic", OBJECT(dev
), NULL
);
1377 qdev_init_nofail(dev
);
1378 d
= SYS_BUS_DEVICE(dev
);
1379 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1381 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1382 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);