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hw: Add compat machines for 8.0
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "qemu/bitmap.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
71 #include "qemu/option.h"
72 #include "qemu/cutils.h"
73 #include "hw/acpi/acpi.h"
74 #include "hw/acpi/cpu_hotplug.h"
75 #include "acpi-build.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/cxl/cxl.h"
79 #include "hw/cxl/cxl_host.h"
80 #include "qapi/error.h"
81 #include "qapi/qapi-visit-common.h"
82 #include "qapi/qapi-visit-machine.h"
83 #include "qapi/visitor.h"
84 #include "hw/core/cpu.h"
85 #include "hw/usb.h"
86 #include "hw/i386/intel_iommu.h"
87 #include "hw/net/ne2000-isa.h"
88 #include "standard-headers/asm-x86/bootparam.h"
89 #include "hw/virtio/virtio-iommu.h"
90 #include "hw/virtio/virtio-pmem-pci.h"
91 #include "hw/virtio/virtio-mem-pci.h"
92 #include "hw/mem/memory-device.h"
93 #include "sysemu/replay.h"
94 #include "target/i386/cpu.h"
95 #include "qapi/qmp/qerror.h"
96 #include "e820_memory_layout.h"
97 #include "fw_cfg.h"
98 #include "trace.h"
99 #include CONFIG_DEVICES
100
101 /*
102 * Helper for setting model-id for CPU models that changed model-id
103 * depending on QEMU versions up to QEMU 2.4.
104 */
105 #define PC_CPU_MODEL_IDS(v) \
106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
109
110 GlobalProperty pc_compat_7_2[] = {};
111 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
112
113 GlobalProperty pc_compat_7_1[] = {};
114 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
115
116 GlobalProperty pc_compat_7_0[] = {};
117 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
118
119 GlobalProperty pc_compat_6_2[] = {
120 { "virtio-mem", "unplugged-inaccessible", "off" },
121 };
122 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
123
124 GlobalProperty pc_compat_6_1[] = {
125 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
126 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
127 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
128 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
129 };
130 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
131
132 GlobalProperty pc_compat_6_0[] = {
133 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
134 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
135 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
136 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
137 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
138 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
139 };
140 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
141
142 GlobalProperty pc_compat_5_2[] = {
143 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
144 };
145 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
146
147 GlobalProperty pc_compat_5_1[] = {
148 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
149 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
150 };
151 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
152
153 GlobalProperty pc_compat_5_0[] = {
154 };
155 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
156
157 GlobalProperty pc_compat_4_2[] = {
158 { "mch", "smbase-smram", "off" },
159 };
160 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
161
162 GlobalProperty pc_compat_4_1[] = {};
163 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
164
165 GlobalProperty pc_compat_4_0[] = {};
166 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
167
168 GlobalProperty pc_compat_3_1[] = {
169 { "intel-iommu", "dma-drain", "off" },
170 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
171 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
172 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
173 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
174 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
175 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
176 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
177 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
178 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
179 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
180 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
181 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
182 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
183 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
184 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
185 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
186 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
187 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
188 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
189 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
190 };
191 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
192
193 GlobalProperty pc_compat_3_0[] = {
194 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
195 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
196 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
197 };
198 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
199
200 GlobalProperty pc_compat_2_12[] = {
201 { TYPE_X86_CPU, "legacy-cache", "on" },
202 { TYPE_X86_CPU, "topoext", "off" },
203 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
204 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
205 };
206 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
207
208 GlobalProperty pc_compat_2_11[] = {
209 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
210 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
211 };
212 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
213
214 GlobalProperty pc_compat_2_10[] = {
215 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
216 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
217 { "q35-pcihost", "x-pci-hole64-fix", "off" },
218 };
219 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
220
221 GlobalProperty pc_compat_2_9[] = {
222 { "mch", "extended-tseg-mbytes", "0" },
223 };
224 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
225
226 GlobalProperty pc_compat_2_8[] = {
227 { TYPE_X86_CPU, "tcg-cpuid", "off" },
228 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
229 { "ICH9-LPC", "x-smi-broadcast", "off" },
230 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
231 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
232 };
233 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
234
235 GlobalProperty pc_compat_2_7[] = {
236 { TYPE_X86_CPU, "l3-cache", "off" },
237 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
238 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
239 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
240 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
241 { "isa-pcspk", "migrate", "off" },
242 };
243 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
244
245 GlobalProperty pc_compat_2_6[] = {
246 { TYPE_X86_CPU, "cpuid-0xb", "off" },
247 { "vmxnet3", "romfile", "" },
248 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
249 { "apic-common", "legacy-instance-id", "on", }
250 };
251 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
252
253 GlobalProperty pc_compat_2_5[] = {};
254 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
255
256 GlobalProperty pc_compat_2_4[] = {
257 PC_CPU_MODEL_IDS("2.4.0")
258 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
259 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
260 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
261 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
262 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
263 { TYPE_X86_CPU, "check", "off" },
264 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
265 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
266 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
267 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
268 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
269 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
270 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
271 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
272 };
273 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
274
275 GlobalProperty pc_compat_2_3[] = {
276 PC_CPU_MODEL_IDS("2.3.0")
277 { TYPE_X86_CPU, "arat", "off" },
278 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
279 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
280 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
281 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
282 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
283 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
284 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
285 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
291 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
292 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
293 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
294 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
295 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
296 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
297 };
298 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
299
300 GlobalProperty pc_compat_2_2[] = {
301 PC_CPU_MODEL_IDS("2.2.0")
302 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
303 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
304 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
305 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
306 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
307 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
308 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
309 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
310 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
311 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
312 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
313 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
314 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
315 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
316 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
317 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
318 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
319 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
320 };
321 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
322
323 GlobalProperty pc_compat_2_1[] = {
324 PC_CPU_MODEL_IDS("2.1.0")
325 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
326 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
327 };
328 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
329
330 GlobalProperty pc_compat_2_0[] = {
331 PC_CPU_MODEL_IDS("2.0.0")
332 { "virtio-scsi-pci", "any_layout", "off" },
333 { "PIIX4_PM", "memory-hotplug-support", "off" },
334 { "apic", "version", "0x11" },
335 { "nec-usb-xhci", "superspeed-ports-first", "off" },
336 { "nec-usb-xhci", "force-pcie-endcap", "on" },
337 { "pci-serial", "prog_if", "0" },
338 { "pci-serial-2x", "prog_if", "0" },
339 { "pci-serial-4x", "prog_if", "0" },
340 { "virtio-net-pci", "guest_announce", "off" },
341 { "ICH9-LPC", "memory-hotplug-support", "off" },
342 };
343 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
344
345 GlobalProperty pc_compat_1_7[] = {
346 PC_CPU_MODEL_IDS("1.7.0")
347 { TYPE_USB_DEVICE, "msos-desc", "no" },
348 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
349 { "hpet", HPET_INTCAP, "4" },
350 };
351 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
352
353 GlobalProperty pc_compat_1_6[] = {
354 PC_CPU_MODEL_IDS("1.6.0")
355 { "e1000", "mitigation", "off" },
356 { "qemu64-" TYPE_X86_CPU, "model", "2" },
357 { "qemu32-" TYPE_X86_CPU, "model", "3" },
358 { "i440FX-pcihost", "short_root_bus", "1" },
359 { "q35-pcihost", "short_root_bus", "1" },
360 };
361 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
362
363 GlobalProperty pc_compat_1_5[] = {
364 PC_CPU_MODEL_IDS("1.5.0")
365 { "Conroe-" TYPE_X86_CPU, "model", "2" },
366 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
367 { "Penryn-" TYPE_X86_CPU, "model", "2" },
368 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
369 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
370 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
371 { "virtio-net-pci", "any_layout", "off" },
372 { TYPE_X86_CPU, "pmu", "on" },
373 { "i440FX-pcihost", "short_root_bus", "0" },
374 { "q35-pcihost", "short_root_bus", "0" },
375 };
376 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
377
378 GlobalProperty pc_compat_1_4[] = {
379 PC_CPU_MODEL_IDS("1.4.0")
380 { "scsi-hd", "discard_granularity", "0" },
381 { "scsi-cd", "discard_granularity", "0" },
382 { "ide-hd", "discard_granularity", "0" },
383 { "ide-cd", "discard_granularity", "0" },
384 { "virtio-blk-pci", "discard_granularity", "0" },
385 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
386 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
387 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
388 { "e1000", "romfile", "pxe-e1000.rom" },
389 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
390 { "pcnet", "romfile", "pxe-pcnet.rom" },
391 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
392 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
393 { "486-" TYPE_X86_CPU, "model", "0" },
394 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
395 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
396 };
397 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
398
399 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
400 {
401 GSIState *s;
402
403 s = g_new0(GSIState, 1);
404 if (kvm_ioapic_in_kernel()) {
405 kvm_pc_setup_irq_routing(pci_enabled);
406 }
407 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
408
409 return s;
410 }
411
412 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
413 unsigned size)
414 {
415 }
416
417 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
418 {
419 return 0xffffffffffffffffULL;
420 }
421
422 /* MSDOS compatibility mode FPU exception support */
423 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
424 unsigned size)
425 {
426 if (tcg_enabled()) {
427 cpu_set_ignne();
428 }
429 }
430
431 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
432 {
433 return 0xffffffffffffffffULL;
434 }
435
436 /* PC cmos mappings */
437
438 #define REG_EQUIPMENT_BYTE 0x14
439
440 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
441 int16_t cylinders, int8_t heads, int8_t sectors)
442 {
443 rtc_set_memory(s, type_ofs, 47);
444 rtc_set_memory(s, info_ofs, cylinders);
445 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
446 rtc_set_memory(s, info_ofs + 2, heads);
447 rtc_set_memory(s, info_ofs + 3, 0xff);
448 rtc_set_memory(s, info_ofs + 4, 0xff);
449 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
450 rtc_set_memory(s, info_ofs + 6, cylinders);
451 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
452 rtc_set_memory(s, info_ofs + 8, sectors);
453 }
454
455 /* convert boot_device letter to something recognizable by the bios */
456 static int boot_device2nibble(char boot_device)
457 {
458 switch(boot_device) {
459 case 'a':
460 case 'b':
461 return 0x01; /* floppy boot */
462 case 'c':
463 return 0x02; /* hard drive boot */
464 case 'd':
465 return 0x03; /* CD-ROM boot */
466 case 'n':
467 return 0x04; /* Network boot */
468 }
469 return 0;
470 }
471
472 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
473 {
474 #define PC_MAX_BOOT_DEVICES 3
475 int nbds, bds[3] = { 0, };
476 int i;
477
478 nbds = strlen(boot_device);
479 if (nbds > PC_MAX_BOOT_DEVICES) {
480 error_setg(errp, "Too many boot devices for PC");
481 return;
482 }
483 for (i = 0; i < nbds; i++) {
484 bds[i] = boot_device2nibble(boot_device[i]);
485 if (bds[i] == 0) {
486 error_setg(errp, "Invalid boot device for PC: '%c'",
487 boot_device[i]);
488 return;
489 }
490 }
491 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
492 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
493 }
494
495 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
496 {
497 set_boot_dev(opaque, boot_device, errp);
498 }
499
500 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
501 {
502 int val, nb, i;
503 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
504 FLOPPY_DRIVE_TYPE_NONE };
505
506 /* floppy type */
507 if (floppy) {
508 for (i = 0; i < 2; i++) {
509 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
510 }
511 }
512 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
513 cmos_get_fd_drive_type(fd_type[1]);
514 rtc_set_memory(rtc_state, 0x10, val);
515
516 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
517 nb = 0;
518 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
519 nb++;
520 }
521 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
522 nb++;
523 }
524 switch (nb) {
525 case 0:
526 break;
527 case 1:
528 val |= 0x01; /* 1 drive, ready for boot */
529 break;
530 case 2:
531 val |= 0x41; /* 2 drives, ready for boot */
532 break;
533 }
534 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
535 }
536
537 typedef struct pc_cmos_init_late_arg {
538 ISADevice *rtc_state;
539 BusState *idebus[2];
540 } pc_cmos_init_late_arg;
541
542 typedef struct check_fdc_state {
543 ISADevice *floppy;
544 bool multiple;
545 } CheckFdcState;
546
547 static int check_fdc(Object *obj, void *opaque)
548 {
549 CheckFdcState *state = opaque;
550 Object *fdc;
551 uint32_t iobase;
552 Error *local_err = NULL;
553
554 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
555 if (!fdc) {
556 return 0;
557 }
558
559 iobase = object_property_get_uint(obj, "iobase", &local_err);
560 if (local_err || iobase != 0x3f0) {
561 error_free(local_err);
562 return 0;
563 }
564
565 if (state->floppy) {
566 state->multiple = true;
567 } else {
568 state->floppy = ISA_DEVICE(obj);
569 }
570 return 0;
571 }
572
573 static const char * const fdc_container_path[] = {
574 "/unattached", "/peripheral", "/peripheral-anon"
575 };
576
577 /*
578 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
579 * and ACPI objects.
580 */
581 static ISADevice *pc_find_fdc0(void)
582 {
583 int i;
584 Object *container;
585 CheckFdcState state = { 0 };
586
587 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
588 container = container_get(qdev_get_machine(), fdc_container_path[i]);
589 object_child_foreach(container, check_fdc, &state);
590 }
591
592 if (state.multiple) {
593 warn_report("multiple floppy disk controllers with "
594 "iobase=0x3f0 have been found");
595 error_printf("the one being picked for CMOS setup might not reflect "
596 "your intent");
597 }
598
599 return state.floppy;
600 }
601
602 static void pc_cmos_init_late(void *opaque)
603 {
604 pc_cmos_init_late_arg *arg = opaque;
605 ISADevice *s = arg->rtc_state;
606 int16_t cylinders;
607 int8_t heads, sectors;
608 int val;
609 int i, trans;
610
611 val = 0;
612 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
613 &cylinders, &heads, &sectors) >= 0) {
614 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
615 val |= 0xf0;
616 }
617 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
618 &cylinders, &heads, &sectors) >= 0) {
619 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
620 val |= 0x0f;
621 }
622 rtc_set_memory(s, 0x12, val);
623
624 val = 0;
625 for (i = 0; i < 4; i++) {
626 /* NOTE: ide_get_geometry() returns the physical
627 geometry. It is always such that: 1 <= sects <= 63, 1
628 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
629 geometry can be different if a translation is done. */
630 if (arg->idebus[i / 2] &&
631 ide_get_geometry(arg->idebus[i / 2], i % 2,
632 &cylinders, &heads, &sectors) >= 0) {
633 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
634 assert((trans & ~3) == 0);
635 val |= trans << (i * 2);
636 }
637 }
638 rtc_set_memory(s, 0x39, val);
639
640 pc_cmos_init_floppy(s, pc_find_fdc0());
641
642 qemu_unregister_reset(pc_cmos_init_late, opaque);
643 }
644
645 void pc_cmos_init(PCMachineState *pcms,
646 BusState *idebus0, BusState *idebus1,
647 ISADevice *s)
648 {
649 int val;
650 static pc_cmos_init_late_arg arg;
651 X86MachineState *x86ms = X86_MACHINE(pcms);
652
653 /* various important CMOS locations needed by PC/Bochs bios */
654
655 /* memory size */
656 /* base memory (first MiB) */
657 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
658 rtc_set_memory(s, 0x15, val);
659 rtc_set_memory(s, 0x16, val >> 8);
660 /* extended memory (next 64MiB) */
661 if (x86ms->below_4g_mem_size > 1 * MiB) {
662 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
663 } else {
664 val = 0;
665 }
666 if (val > 65535)
667 val = 65535;
668 rtc_set_memory(s, 0x17, val);
669 rtc_set_memory(s, 0x18, val >> 8);
670 rtc_set_memory(s, 0x30, val);
671 rtc_set_memory(s, 0x31, val >> 8);
672 /* memory between 16MiB and 4GiB */
673 if (x86ms->below_4g_mem_size > 16 * MiB) {
674 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
675 } else {
676 val = 0;
677 }
678 if (val > 65535)
679 val = 65535;
680 rtc_set_memory(s, 0x34, val);
681 rtc_set_memory(s, 0x35, val >> 8);
682 /* memory above 4GiB */
683 val = x86ms->above_4g_mem_size / 65536;
684 rtc_set_memory(s, 0x5b, val);
685 rtc_set_memory(s, 0x5c, val >> 8);
686 rtc_set_memory(s, 0x5d, val >> 16);
687
688 object_property_add_link(OBJECT(pcms), "rtc_state",
689 TYPE_ISA_DEVICE,
690 (Object **)&x86ms->rtc,
691 object_property_allow_set_link,
692 OBJ_PROP_LINK_STRONG);
693 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
694 &error_abort);
695
696 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
697
698 val = 0;
699 val |= 0x02; /* FPU is there */
700 val |= 0x04; /* PS/2 mouse installed */
701 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
702
703 /* hard drives and FDC */
704 arg.rtc_state = s;
705 arg.idebus[0] = idebus0;
706 arg.idebus[1] = idebus1;
707 qemu_register_reset(pc_cmos_init_late, &arg);
708 }
709
710 static void handle_a20_line_change(void *opaque, int irq, int level)
711 {
712 X86CPU *cpu = opaque;
713
714 /* XXX: send to all CPUs ? */
715 /* XXX: add logic to handle multiple A20 line sources */
716 x86_cpu_set_a20(cpu, level);
717 }
718
719 #define NE2000_NB_MAX 6
720
721 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
722 0x280, 0x380 };
723 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
724
725 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
726 {
727 static int nb_ne2k = 0;
728
729 if (nb_ne2k == NE2000_NB_MAX)
730 return;
731 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
732 ne2000_irq[nb_ne2k], nd);
733 nb_ne2k++;
734 }
735
736 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
737 {
738 X86CPU *cpu = opaque;
739
740 if (level) {
741 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
742 }
743 }
744
745 static
746 void pc_machine_done(Notifier *notifier, void *data)
747 {
748 PCMachineState *pcms = container_of(notifier,
749 PCMachineState, machine_done);
750 X86MachineState *x86ms = X86_MACHINE(pcms);
751
752 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
753 &error_fatal);
754
755 if (pcms->cxl_devices_state.is_enabled) {
756 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
757 }
758
759 /* set the number of CPUs */
760 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
761
762 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
763
764 acpi_setup();
765 if (x86ms->fw_cfg) {
766 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
767 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
768 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
769 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
770 }
771 }
772
773 void pc_guest_info_init(PCMachineState *pcms)
774 {
775 X86MachineState *x86ms = X86_MACHINE(pcms);
776
777 x86ms->apic_xrupt_override = true;
778 pcms->machine_done.notify = pc_machine_done;
779 qemu_add_machine_init_done_notifier(&pcms->machine_done);
780 }
781
782 /* setup pci memory address space mapping into system address space */
783 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
784 MemoryRegion *pci_address_space)
785 {
786 /* Set to lower priority than RAM */
787 memory_region_add_subregion_overlap(system_memory, 0x0,
788 pci_address_space, -1);
789 }
790
791 void xen_load_linux(PCMachineState *pcms)
792 {
793 int i;
794 FWCfgState *fw_cfg;
795 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
796 X86MachineState *x86ms = X86_MACHINE(pcms);
797
798 assert(MACHINE(pcms)->kernel_filename != NULL);
799
800 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
801 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
802 rom_set_fw(fw_cfg);
803
804 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
805 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
806 for (i = 0; i < nb_option_roms; i++) {
807 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
808 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
809 !strcmp(option_rom[i].name, "pvh.bin") ||
810 !strcmp(option_rom[i].name, "multiboot.bin") ||
811 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
812 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
813 }
814 x86ms->fw_cfg = fw_cfg;
815 }
816
817 #define PC_ROM_MIN_VGA 0xc0000
818 #define PC_ROM_MIN_OPTION 0xc8000
819 #define PC_ROM_MAX 0xe0000
820 #define PC_ROM_ALIGN 0x800
821 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
822
823 static hwaddr pc_above_4g_end(PCMachineState *pcms)
824 {
825 X86MachineState *x86ms = X86_MACHINE(pcms);
826
827 if (pcms->sgx_epc.size != 0) {
828 return sgx_epc_above_4g_end(&pcms->sgx_epc);
829 }
830
831 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
832 }
833
834 static void pc_get_device_memory_range(PCMachineState *pcms,
835 hwaddr *base,
836 ram_addr_t *device_mem_size)
837 {
838 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
839 MachineState *machine = MACHINE(pcms);
840 ram_addr_t size;
841 hwaddr addr;
842
843 size = machine->maxram_size - machine->ram_size;
844 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
845
846 if (pcmc->enforce_aligned_dimm) {
847 /* size device region assuming 1G page max alignment per slot */
848 size += (1 * GiB) * machine->ram_slots;
849 }
850
851 *base = addr;
852 *device_mem_size = size;
853 }
854
855 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
856 {
857 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
858 hwaddr cxl_base;
859 ram_addr_t size;
860
861 if (pcmc->has_reserved_memory) {
862 pc_get_device_memory_range(pcms, &cxl_base, &size);
863 cxl_base += size;
864 } else {
865 cxl_base = pc_above_4g_end(pcms);
866 }
867
868 return cxl_base;
869 }
870
871 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
872 {
873 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
874
875 if (pcms->cxl_devices_state.fixed_windows) {
876 GList *it;
877
878 start = ROUND_UP(start, 256 * MiB);
879 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
880 CXLFixedWindow *fw = it->data;
881 start += fw->size;
882 }
883 }
884
885 return start;
886 }
887
888 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
889 {
890 X86CPU *cpu = X86_CPU(first_cpu);
891
892 /* 32-bit systems don't have hole64 thus return max CPU address */
893 if (cpu->phys_bits <= 32) {
894 return ((hwaddr)1 << cpu->phys_bits) - 1;
895 }
896
897 return pc_pci_hole64_start() + pci_hole64_size - 1;
898 }
899
900 /*
901 * AMD systems with an IOMMU have an additional hole close to the
902 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
903 * on kernel version, VFIO may or may not let you DMA map those ranges.
904 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
905 * with certain memory sizes. It's also wrong to use those IOVA ranges
906 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
907 * The ranges reserved for Hyper-Transport are:
908 *
909 * FD_0000_0000h - FF_FFFF_FFFFh
910 *
911 * The ranges represent the following:
912 *
913 * Base Address Top Address Use
914 *
915 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
916 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
917 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
918 * FD_F910_0000h FD_F91F_FFFFh System Management
919 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
920 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
921 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
922 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
923 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
924 * FE_2000_0000h FF_FFFF_FFFFh Reserved
925 *
926 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
927 * Table 3: Special Address Controls (GPA) for more information.
928 */
929 #define AMD_HT_START 0xfd00000000UL
930 #define AMD_HT_END 0xffffffffffUL
931 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
932 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
933
934 void pc_memory_init(PCMachineState *pcms,
935 MemoryRegion *system_memory,
936 MemoryRegion *rom_memory,
937 MemoryRegion **ram_memory,
938 uint64_t pci_hole64_size)
939 {
940 int linux_boot, i;
941 MemoryRegion *option_rom_mr;
942 MemoryRegion *ram_below_4g, *ram_above_4g;
943 FWCfgState *fw_cfg;
944 MachineState *machine = MACHINE(pcms);
945 MachineClass *mc = MACHINE_GET_CLASS(machine);
946 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
947 X86MachineState *x86ms = X86_MACHINE(pcms);
948 hwaddr maxphysaddr, maxusedaddr;
949 hwaddr cxl_base, cxl_resv_end = 0;
950 X86CPU *cpu = X86_CPU(first_cpu);
951
952 assert(machine->ram_size == x86ms->below_4g_mem_size +
953 x86ms->above_4g_mem_size);
954
955 linux_boot = (machine->kernel_filename != NULL);
956
957 /*
958 * The HyperTransport range close to the 1T boundary is unique to AMD
959 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
960 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
961 * older machine types (<= 7.0) for compatibility purposes.
962 */
963 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
964 /* Bail out if max possible address does not cross HT range */
965 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
966 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
967 }
968
969 /*
970 * Advertise the HT region if address space covers the reserved
971 * region or if we relocate.
972 */
973 if (cpu->phys_bits >= 40) {
974 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
975 }
976 }
977
978 /*
979 * phys-bits is required to be appropriately configured
980 * to make sure max used GPA is reachable.
981 */
982 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
983 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
984 if (maxphysaddr < maxusedaddr) {
985 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
986 " phys-bits too low (%u)",
987 maxphysaddr, maxusedaddr, cpu->phys_bits);
988 exit(EXIT_FAILURE);
989 }
990
991 /*
992 * Split single memory region and use aliases to address portions of it,
993 * done for backwards compatibility with older qemus.
994 */
995 *ram_memory = machine->ram;
996 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
997 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
998 0, x86ms->below_4g_mem_size);
999 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1000 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1001 if (x86ms->above_4g_mem_size > 0) {
1002 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1003 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1004 machine->ram,
1005 x86ms->below_4g_mem_size,
1006 x86ms->above_4g_mem_size);
1007 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1008 ram_above_4g);
1009 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1010 E820_RAM);
1011 }
1012
1013 if (pcms->sgx_epc.size != 0) {
1014 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1015 }
1016
1017 if (!pcmc->has_reserved_memory &&
1018 (machine->ram_slots ||
1019 (machine->maxram_size > machine->ram_size))) {
1020
1021 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1022 mc->name);
1023 exit(EXIT_FAILURE);
1024 }
1025
1026 /* always allocate the device memory information */
1027 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1028
1029 /* initialize device memory address space */
1030 if (pcmc->has_reserved_memory &&
1031 (machine->ram_size < machine->maxram_size)) {
1032 ram_addr_t device_mem_size;
1033
1034 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1035 error_report("unsupported amount of memory slots: %"PRIu64,
1036 machine->ram_slots);
1037 exit(EXIT_FAILURE);
1038 }
1039
1040 if (QEMU_ALIGN_UP(machine->maxram_size,
1041 TARGET_PAGE_SIZE) != machine->maxram_size) {
1042 error_report("maximum memory size must by aligned to multiple of "
1043 "%d bytes", TARGET_PAGE_SIZE);
1044 exit(EXIT_FAILURE);
1045 }
1046
1047 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1048
1049 if ((machine->device_memory->base + device_mem_size) <
1050 device_mem_size) {
1051 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1052 machine->maxram_size);
1053 exit(EXIT_FAILURE);
1054 }
1055
1056 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1057 "device-memory", device_mem_size);
1058 memory_region_add_subregion(system_memory, machine->device_memory->base,
1059 &machine->device_memory->mr);
1060 }
1061
1062 if (pcms->cxl_devices_state.is_enabled) {
1063 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1064 hwaddr cxl_size = MiB;
1065
1066 cxl_base = pc_get_cxl_range_start(pcms);
1067 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1068 memory_region_add_subregion(system_memory, cxl_base, mr);
1069 cxl_resv_end = cxl_base + cxl_size;
1070 if (pcms->cxl_devices_state.fixed_windows) {
1071 hwaddr cxl_fmw_base;
1072 GList *it;
1073
1074 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1075 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1076 CXLFixedWindow *fw = it->data;
1077
1078 fw->base = cxl_fmw_base;
1079 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1080 "cxl-fixed-memory-region", fw->size);
1081 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1082 cxl_fmw_base += fw->size;
1083 cxl_resv_end = cxl_fmw_base;
1084 }
1085 }
1086 }
1087
1088 /* Initialize PC system firmware */
1089 pc_system_firmware_init(pcms, rom_memory);
1090
1091 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1092 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1093 &error_fatal);
1094 if (pcmc->pci_enabled) {
1095 memory_region_set_readonly(option_rom_mr, true);
1096 }
1097 memory_region_add_subregion_overlap(rom_memory,
1098 PC_ROM_MIN_VGA,
1099 option_rom_mr,
1100 1);
1101
1102 fw_cfg = fw_cfg_arch_create(machine,
1103 x86ms->boot_cpus, x86ms->apic_id_limit);
1104
1105 rom_set_fw(fw_cfg);
1106
1107 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1108 uint64_t *val = g_malloc(sizeof(*val));
1109 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1110 uint64_t res_mem_end = machine->device_memory->base;
1111
1112 if (!pcmc->broken_reserved_end) {
1113 res_mem_end += memory_region_size(&machine->device_memory->mr);
1114 }
1115
1116 if (pcms->cxl_devices_state.is_enabled) {
1117 res_mem_end = cxl_resv_end;
1118 }
1119 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1120 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1121 }
1122
1123 if (linux_boot) {
1124 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1125 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
1126 }
1127
1128 for (i = 0; i < nb_option_roms; i++) {
1129 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1130 }
1131 x86ms->fw_cfg = fw_cfg;
1132
1133 /* Init default IOAPIC address space */
1134 x86ms->ioapic_as = &address_space_memory;
1135
1136 /* Init ACPI memory hotplug IO base address */
1137 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1138 }
1139
1140 /*
1141 * The 64bit pci hole starts after "above 4G RAM" and
1142 * potentially the space reserved for memory hotplug.
1143 */
1144 uint64_t pc_pci_hole64_start(void)
1145 {
1146 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1147 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1148 MachineState *ms = MACHINE(pcms);
1149 uint64_t hole64_start = 0;
1150 ram_addr_t size = 0;
1151
1152 if (pcms->cxl_devices_state.is_enabled) {
1153 hole64_start = pc_get_cxl_range_end(pcms);
1154 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1155 pc_get_device_memory_range(pcms, &hole64_start, &size);
1156 if (!pcmc->broken_reserved_end) {
1157 hole64_start += size;
1158 }
1159 } else {
1160 hole64_start = pc_above_4g_end(pcms);
1161 }
1162
1163 return ROUND_UP(hole64_start, 1 * GiB);
1164 }
1165
1166 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1167 {
1168 DeviceState *dev = NULL;
1169
1170 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1171 if (pci_bus) {
1172 PCIDevice *pcidev = pci_vga_init(pci_bus);
1173 dev = pcidev ? &pcidev->qdev : NULL;
1174 } else if (isa_bus) {
1175 ISADevice *isadev = isa_vga_init(isa_bus);
1176 dev = isadev ? DEVICE(isadev) : NULL;
1177 }
1178 rom_reset_order_override();
1179 return dev;
1180 }
1181
1182 static const MemoryRegionOps ioport80_io_ops = {
1183 .write = ioport80_write,
1184 .read = ioport80_read,
1185 .endianness = DEVICE_NATIVE_ENDIAN,
1186 .impl = {
1187 .min_access_size = 1,
1188 .max_access_size = 1,
1189 },
1190 };
1191
1192 static const MemoryRegionOps ioportF0_io_ops = {
1193 .write = ioportF0_write,
1194 .read = ioportF0_read,
1195 .endianness = DEVICE_NATIVE_ENDIAN,
1196 .impl = {
1197 .min_access_size = 1,
1198 .max_access_size = 1,
1199 },
1200 };
1201
1202 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1203 bool create_i8042, bool no_vmport)
1204 {
1205 int i;
1206 DriveInfo *fd[MAX_FD];
1207 qemu_irq *a20_line;
1208 ISADevice *fdc, *i8042, *port92, *vmmouse;
1209
1210 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1211 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1212
1213 for (i = 0; i < MAX_FD; i++) {
1214 fd[i] = drive_get(IF_FLOPPY, 0, i);
1215 create_fdctrl |= !!fd[i];
1216 }
1217 if (create_fdctrl) {
1218 fdc = isa_new(TYPE_ISA_FDC);
1219 if (fdc) {
1220 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1221 isa_fdc_init_drives(fdc, fd);
1222 }
1223 }
1224
1225 if (!create_i8042) {
1226 return;
1227 }
1228
1229 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1230 if (!no_vmport) {
1231 isa_create_simple(isa_bus, TYPE_VMPORT);
1232 vmmouse = isa_try_new("vmmouse");
1233 } else {
1234 vmmouse = NULL;
1235 }
1236 if (vmmouse) {
1237 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1238 &error_abort);
1239 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1240 }
1241 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1242
1243 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1244 i8042_setup_a20_line(i8042, a20_line[0]);
1245 qdev_connect_gpio_out_named(DEVICE(port92),
1246 PORT92_A20_LINE, 0, a20_line[1]);
1247 g_free(a20_line);
1248 }
1249
1250 void pc_basic_device_init(struct PCMachineState *pcms,
1251 ISABus *isa_bus, qemu_irq *gsi,
1252 ISADevice **rtc_state,
1253 bool create_fdctrl,
1254 uint32_t hpet_irqs)
1255 {
1256 int i;
1257 DeviceState *hpet = NULL;
1258 int pit_isa_irq = 0;
1259 qemu_irq pit_alt_irq = NULL;
1260 qemu_irq rtc_irq = NULL;
1261 ISADevice *pit = NULL;
1262 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1263 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1264 X86MachineState *x86ms = X86_MACHINE(pcms);
1265
1266 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1267 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1268
1269 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1270 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1271
1272 /*
1273 * Check if an HPET shall be created.
1274 *
1275 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1276 * when the HPET wants to take over. Thus we have to disable the latter.
1277 */
1278 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1279 kvm_has_pit_state2())) {
1280 hpet = qdev_try_new(TYPE_HPET);
1281 if (!hpet) {
1282 error_report("couldn't create HPET device");
1283 exit(1);
1284 }
1285 /*
1286 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1287 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1288 * IRQ2.
1289 */
1290 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1291 HPET_INTCAP, NULL);
1292 if (!compat) {
1293 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1294 }
1295 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1296 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1297
1298 for (i = 0; i < GSI_NUM_PINS; i++) {
1299 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1300 }
1301 pit_isa_irq = -1;
1302 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1303 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1304 }
1305 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1306
1307 qemu_register_boot_set(pc_boot_set, *rtc_state);
1308
1309 if (!xen_enabled() &&
1310 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1311 if (kvm_pit_in_kernel()) {
1312 pit = kvm_pit_init(isa_bus, 0x40);
1313 } else {
1314 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1315 }
1316 if (hpet) {
1317 /* connect PIT to output control line of the HPET */
1318 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1319 }
1320 pcspk_init(pcms->pcspk, isa_bus, pit);
1321 }
1322
1323 /* Super I/O */
1324 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1325 pcms->vmport != ON_OFF_AUTO_ON);
1326 }
1327
1328 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1329 {
1330 int i;
1331
1332 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1333 for (i = 0; i < nb_nics; i++) {
1334 NICInfo *nd = &nd_table[i];
1335 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1336
1337 if (g_str_equal(model, "ne2k_isa")) {
1338 pc_init_ne2k_isa(isa_bus, nd);
1339 } else {
1340 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1341 }
1342 }
1343 rom_reset_order_override();
1344 }
1345
1346 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1347 {
1348 qemu_irq *i8259;
1349
1350 if (kvm_pic_in_kernel()) {
1351 i8259 = kvm_i8259_init(isa_bus);
1352 } else if (xen_enabled()) {
1353 i8259 = xen_interrupt_controller_init();
1354 } else {
1355 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1356 }
1357
1358 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1359 i8259_irqs[i] = i8259[i];
1360 }
1361
1362 g_free(i8259);
1363 }
1364
1365 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1366 Error **errp)
1367 {
1368 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1369 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1370 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1371 const MachineState *ms = MACHINE(hotplug_dev);
1372 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1373 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1374 Error *local_err = NULL;
1375
1376 /*
1377 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1378 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1379 * addition to cover this case.
1380 */
1381 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1382 error_setg(errp,
1383 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1384 return;
1385 }
1386
1387 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1388 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1389 return;
1390 }
1391
1392 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1393 if (local_err) {
1394 error_propagate(errp, local_err);
1395 return;
1396 }
1397
1398 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1399 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1400 }
1401
1402 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1403 DeviceState *dev, Error **errp)
1404 {
1405 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1406 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1407 MachineState *ms = MACHINE(hotplug_dev);
1408 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1409
1410 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1411
1412 if (is_nvdimm) {
1413 nvdimm_plug(ms->nvdimms_state);
1414 }
1415
1416 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1417 }
1418
1419 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1420 DeviceState *dev, Error **errp)
1421 {
1422 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1423
1424 /*
1425 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1426 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1427 * addition to cover this case.
1428 */
1429 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1430 error_setg(errp,
1431 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1432 return;
1433 }
1434
1435 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1436 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1437 return;
1438 }
1439
1440 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1441 errp);
1442 }
1443
1444 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1445 DeviceState *dev, Error **errp)
1446 {
1447 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1448 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1449 Error *local_err = NULL;
1450
1451 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1452 if (local_err) {
1453 goto out;
1454 }
1455
1456 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1457 qdev_unrealize(dev);
1458 out:
1459 error_propagate(errp, local_err);
1460 }
1461
1462 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1463 DeviceState *dev, Error **errp)
1464 {
1465 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1466 Error *local_err = NULL;
1467
1468 if (!hotplug_dev2 && dev->hotplugged) {
1469 /*
1470 * Without a bus hotplug handler, we cannot control the plug/unplug
1471 * order. We should never reach this point when hotplugging on x86,
1472 * however, better add a safety net.
1473 */
1474 error_setg(errp, "hotplug of virtio based memory devices not supported"
1475 " on this bus.");
1476 return;
1477 }
1478 /*
1479 * First, see if we can plug this memory device at all. If that
1480 * succeeds, branch of to the actual hotplug handler.
1481 */
1482 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1483 &local_err);
1484 if (!local_err && hotplug_dev2) {
1485 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1486 }
1487 error_propagate(errp, local_err);
1488 }
1489
1490 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1491 DeviceState *dev, Error **errp)
1492 {
1493 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1494 Error *local_err = NULL;
1495
1496 /*
1497 * Plug the memory device first and then branch off to the actual
1498 * hotplug handler. If that one fails, we can easily undo the memory
1499 * device bits.
1500 */
1501 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1502 if (hotplug_dev2) {
1503 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1504 if (local_err) {
1505 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1506 }
1507 }
1508 error_propagate(errp, local_err);
1509 }
1510
1511 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1512 DeviceState *dev, Error **errp)
1513 {
1514 /* We don't support hot unplug of virtio based memory devices */
1515 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1516 }
1517
1518 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1519 DeviceState *dev, Error **errp)
1520 {
1521 /* We don't support hot unplug of virtio based memory devices */
1522 }
1523
1524 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1525 DeviceState *dev, Error **errp)
1526 {
1527 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1528 pc_memory_pre_plug(hotplug_dev, dev, errp);
1529 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1530 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1531 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1532 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1533 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1534 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1535 /* Declare the APIC range as the reserved MSI region */
1536 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1537 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1538
1539 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1540 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1541 resv_prop_str, errp);
1542 g_free(resv_prop_str);
1543 }
1544
1545 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1546 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1547 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1548
1549 if (pcms->iommu) {
1550 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1551 "for x86 yet.");
1552 return;
1553 }
1554 pcms->iommu = dev;
1555 }
1556 }
1557
1558 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1559 DeviceState *dev, Error **errp)
1560 {
1561 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1562 pc_memory_plug(hotplug_dev, dev, errp);
1563 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1564 x86_cpu_plug(hotplug_dev, dev, errp);
1565 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1566 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1567 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1568 }
1569 }
1570
1571 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1572 DeviceState *dev, Error **errp)
1573 {
1574 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1575 pc_memory_unplug_request(hotplug_dev, dev, errp);
1576 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1577 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1578 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1579 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1580 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1581 } else {
1582 error_setg(errp, "acpi: device unplug request for not supported device"
1583 " type: %s", object_get_typename(OBJECT(dev)));
1584 }
1585 }
1586
1587 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1588 DeviceState *dev, Error **errp)
1589 {
1590 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1591 pc_memory_unplug(hotplug_dev, dev, errp);
1592 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1593 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1594 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1595 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1596 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1597 } else {
1598 error_setg(errp, "acpi: device unplug for not supported device"
1599 " type: %s", object_get_typename(OBJECT(dev)));
1600 }
1601 }
1602
1603 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1604 DeviceState *dev)
1605 {
1606 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1607 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1608 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1609 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1610 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1611 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1612 return HOTPLUG_HANDLER(machine);
1613 }
1614
1615 return NULL;
1616 }
1617
1618 static void
1619 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1620 const char *name, void *opaque,
1621 Error **errp)
1622 {
1623 MachineState *ms = MACHINE(obj);
1624 int64_t value = 0;
1625
1626 if (ms->device_memory) {
1627 value = memory_region_size(&ms->device_memory->mr);
1628 }
1629
1630 visit_type_int(v, name, &value, errp);
1631 }
1632
1633 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1634 void *opaque, Error **errp)
1635 {
1636 PCMachineState *pcms = PC_MACHINE(obj);
1637 OnOffAuto vmport = pcms->vmport;
1638
1639 visit_type_OnOffAuto(v, name, &vmport, errp);
1640 }
1641
1642 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1643 void *opaque, Error **errp)
1644 {
1645 PCMachineState *pcms = PC_MACHINE(obj);
1646
1647 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1648 }
1649
1650 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1651 {
1652 PCMachineState *pcms = PC_MACHINE(obj);
1653
1654 return pcms->smbus_enabled;
1655 }
1656
1657 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1658 {
1659 PCMachineState *pcms = PC_MACHINE(obj);
1660
1661 pcms->smbus_enabled = value;
1662 }
1663
1664 static bool pc_machine_get_sata(Object *obj, Error **errp)
1665 {
1666 PCMachineState *pcms = PC_MACHINE(obj);
1667
1668 return pcms->sata_enabled;
1669 }
1670
1671 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1672 {
1673 PCMachineState *pcms = PC_MACHINE(obj);
1674
1675 pcms->sata_enabled = value;
1676 }
1677
1678 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1679 {
1680 PCMachineState *pcms = PC_MACHINE(obj);
1681
1682 return pcms->hpet_enabled;
1683 }
1684
1685 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1686 {
1687 PCMachineState *pcms = PC_MACHINE(obj);
1688
1689 pcms->hpet_enabled = value;
1690 }
1691
1692 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1693 {
1694 PCMachineState *pcms = PC_MACHINE(obj);
1695
1696 return pcms->i8042_enabled;
1697 }
1698
1699 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1700 {
1701 PCMachineState *pcms = PC_MACHINE(obj);
1702
1703 pcms->i8042_enabled = value;
1704 }
1705
1706 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1707 {
1708 PCMachineState *pcms = PC_MACHINE(obj);
1709
1710 return pcms->default_bus_bypass_iommu;
1711 }
1712
1713 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1714 Error **errp)
1715 {
1716 PCMachineState *pcms = PC_MACHINE(obj);
1717
1718 pcms->default_bus_bypass_iommu = value;
1719 }
1720
1721 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1722 void *opaque, Error **errp)
1723 {
1724 PCMachineState *pcms = PC_MACHINE(obj);
1725 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1726
1727 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1728 }
1729
1730 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1731 void *opaque, Error **errp)
1732 {
1733 PCMachineState *pcms = PC_MACHINE(obj);
1734
1735 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1736 }
1737
1738 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1739 const char *name, void *opaque,
1740 Error **errp)
1741 {
1742 PCMachineState *pcms = PC_MACHINE(obj);
1743 uint64_t value = pcms->max_ram_below_4g;
1744
1745 visit_type_size(v, name, &value, errp);
1746 }
1747
1748 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1749 const char *name, void *opaque,
1750 Error **errp)
1751 {
1752 PCMachineState *pcms = PC_MACHINE(obj);
1753 uint64_t value;
1754
1755 if (!visit_type_size(v, name, &value, errp)) {
1756 return;
1757 }
1758 if (value > 4 * GiB) {
1759 error_setg(errp,
1760 "Machine option 'max-ram-below-4g=%"PRIu64
1761 "' expects size less than or equal to 4G", value);
1762 return;
1763 }
1764
1765 if (value < 1 * MiB) {
1766 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1767 "BIOS may not work with less than 1MiB", value);
1768 }
1769
1770 pcms->max_ram_below_4g = value;
1771 }
1772
1773 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1774 const char *name, void *opaque,
1775 Error **errp)
1776 {
1777 PCMachineState *pcms = PC_MACHINE(obj);
1778 uint64_t value = pcms->max_fw_size;
1779
1780 visit_type_size(v, name, &value, errp);
1781 }
1782
1783 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1784 const char *name, void *opaque,
1785 Error **errp)
1786 {
1787 PCMachineState *pcms = PC_MACHINE(obj);
1788 uint64_t value;
1789
1790 if (!visit_type_size(v, name, &value, errp)) {
1791 return;
1792 }
1793
1794 /*
1795 * We don't have a theoretically justifiable exact lower bound on the base
1796 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1797 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1798 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1799 * size.
1800 */
1801 if (value > 16 * MiB) {
1802 error_setg(errp,
1803 "User specified max allowed firmware size %" PRIu64 " is "
1804 "greater than 16MiB. If combined firwmare size exceeds "
1805 "16MiB the system may not boot, or experience intermittent"
1806 "stability issues.",
1807 value);
1808 return;
1809 }
1810
1811 pcms->max_fw_size = value;
1812 }
1813
1814
1815 static void pc_machine_initfn(Object *obj)
1816 {
1817 PCMachineState *pcms = PC_MACHINE(obj);
1818
1819 #ifdef CONFIG_VMPORT
1820 pcms->vmport = ON_OFF_AUTO_AUTO;
1821 #else
1822 pcms->vmport = ON_OFF_AUTO_OFF;
1823 #endif /* CONFIG_VMPORT */
1824 pcms->max_ram_below_4g = 0; /* use default */
1825 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1826
1827 /* acpi build is enabled by default if machine supports it */
1828 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1829 pcms->smbus_enabled = true;
1830 pcms->sata_enabled = true;
1831 pcms->i8042_enabled = true;
1832 pcms->max_fw_size = 8 * MiB;
1833 #ifdef CONFIG_HPET
1834 pcms->hpet_enabled = true;
1835 #endif
1836 pcms->default_bus_bypass_iommu = false;
1837
1838 pc_system_flash_create(pcms);
1839 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1840 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1841 OBJECT(pcms->pcspk), "audiodev");
1842 cxl_machine_init(obj, &pcms->cxl_devices_state);
1843 }
1844
1845 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1846 {
1847 CPUState *cs;
1848 X86CPU *cpu;
1849
1850 qemu_devices_reset(reason);
1851
1852 /* Reset APIC after devices have been reset to cancel
1853 * any changes that qemu_devices_reset() might have done.
1854 */
1855 CPU_FOREACH(cs) {
1856 cpu = X86_CPU(cs);
1857
1858 x86_cpu_after_reset(cpu);
1859 }
1860 }
1861
1862 static void pc_machine_wakeup(MachineState *machine)
1863 {
1864 cpu_synchronize_all_states();
1865 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1866 cpu_synchronize_all_post_reset();
1867 }
1868
1869 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1870 {
1871 X86IOMMUState *iommu = x86_iommu_get_default();
1872 IntelIOMMUState *intel_iommu;
1873
1874 if (iommu &&
1875 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1876 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1877 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1878 if (!intel_iommu->caching_mode) {
1879 error_setg(errp, "Device assignment is not allowed without "
1880 "enabling caching-mode=on for Intel IOMMU.");
1881 return false;
1882 }
1883 }
1884
1885 return true;
1886 }
1887
1888 static void pc_machine_class_init(ObjectClass *oc, void *data)
1889 {
1890 MachineClass *mc = MACHINE_CLASS(oc);
1891 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1892 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1893
1894 pcmc->pci_enabled = true;
1895 pcmc->has_acpi_build = true;
1896 pcmc->rsdp_in_ram = true;
1897 pcmc->smbios_defaults = true;
1898 pcmc->smbios_uuid_encoded = true;
1899 pcmc->gigabyte_align = true;
1900 pcmc->has_reserved_memory = true;
1901 pcmc->kvmclock_enabled = true;
1902 pcmc->enforce_aligned_dimm = true;
1903 pcmc->enforce_amd_1tb_hole = true;
1904 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1905 * to be used at the moment, 32K should be enough for a while. */
1906 pcmc->acpi_data_size = 0x20000 + 0x8000;
1907 pcmc->pvh_enabled = true;
1908 pcmc->kvmclock_create_always = true;
1909 assert(!mc->get_hotplug_handler);
1910 mc->get_hotplug_handler = pc_get_hotplug_handler;
1911 mc->hotplug_allowed = pc_hotplug_allowed;
1912 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1913 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1914 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1915 mc->auto_enable_numa_with_memhp = true;
1916 mc->auto_enable_numa_with_memdev = true;
1917 mc->has_hotpluggable_cpus = true;
1918 mc->default_boot_order = "cad";
1919 mc->block_default_type = IF_IDE;
1920 mc->max_cpus = 255;
1921 mc->reset = pc_machine_reset;
1922 mc->wakeup = pc_machine_wakeup;
1923 hc->pre_plug = pc_machine_device_pre_plug_cb;
1924 hc->plug = pc_machine_device_plug_cb;
1925 hc->unplug_request = pc_machine_device_unplug_request_cb;
1926 hc->unplug = pc_machine_device_unplug_cb;
1927 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1928 mc->nvdimm_supported = true;
1929 mc->smp_props.dies_supported = true;
1930 mc->default_ram_id = "pc.ram";
1931
1932 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1933 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1934 NULL, NULL);
1935 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1936 "Maximum ram below the 4G boundary (32bit boundary)");
1937
1938 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1939 pc_machine_get_device_memory_region_size, NULL,
1940 NULL, NULL);
1941
1942 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1943 pc_machine_get_vmport, pc_machine_set_vmport,
1944 NULL, NULL);
1945 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1946 "Enable vmport (pc & q35)");
1947
1948 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1949 pc_machine_get_smbus, pc_machine_set_smbus);
1950 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1951 "Enable/disable system management bus");
1952
1953 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1954 pc_machine_get_sata, pc_machine_set_sata);
1955 object_class_property_set_description(oc, PC_MACHINE_SATA,
1956 "Enable/disable Serial ATA bus");
1957
1958 object_class_property_add_bool(oc, "hpet",
1959 pc_machine_get_hpet, pc_machine_set_hpet);
1960 object_class_property_set_description(oc, "hpet",
1961 "Enable/disable high precision event timer emulation");
1962
1963 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1964 pc_machine_get_i8042, pc_machine_set_i8042);
1965
1966 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1967 pc_machine_get_default_bus_bypass_iommu,
1968 pc_machine_set_default_bus_bypass_iommu);
1969
1970 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1971 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1972 NULL, NULL);
1973 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1974 "Maximum combined firmware size");
1975
1976 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1977 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1978 NULL, NULL);
1979 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1980 "SMBIOS Entry Point type [32, 64]");
1981 }
1982
1983 static const TypeInfo pc_machine_info = {
1984 .name = TYPE_PC_MACHINE,
1985 .parent = TYPE_X86_MACHINE,
1986 .abstract = true,
1987 .instance_size = sizeof(PCMachineState),
1988 .instance_init = pc_machine_initfn,
1989 .class_size = sizeof(PCMachineClass),
1990 .class_init = pc_machine_class_init,
1991 .interfaces = (InterfaceInfo[]) {
1992 { TYPE_HOTPLUG_HANDLER },
1993 { }
1994 },
1995 };
1996
1997 static void pc_machine_register_types(void)
1998 {
1999 type_register_static(&pc_machine_info);
2000 }
2001
2002 type_init(pc_machine_register_types)
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