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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "qemu/bitmap.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
71 #include "qemu/option.h"
72 #include "qemu/cutils.h"
73 #include "hw/acpi/acpi.h"
74 #include "hw/acpi/cpu_hotplug.h"
75 #include "acpi-build.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "qapi/error.h"
79 #include "qapi/qapi-visit-common.h"
80 #include "qapi/qapi-visit-machine.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-iommu.h"
88 #include "hw/virtio/virtio-pmem-pci.h"
89 #include "hw/virtio/virtio-mem-pci.h"
90 #include "hw/mem/memory-device.h"
91 #include "sysemu/replay.h"
92 #include "qapi/qmp/qerror.h"
93 #include "e820_memory_layout.h"
94 #include "fw_cfg.h"
95 #include "trace.h"
96 #include CONFIG_DEVICES
97
98 GlobalProperty pc_compat_6_2[] = {
99 { "virtio-mem", "unplugged-inaccessible", "off" },
100 };
101 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
102
103 GlobalProperty pc_compat_6_1[] = {
104 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
105 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
106 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
107 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
108 };
109 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
110
111 GlobalProperty pc_compat_6_0[] = {
112 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
113 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
114 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
115 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
116 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
117 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
118 };
119 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
120
121 GlobalProperty pc_compat_5_2[] = {
122 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
123 };
124 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
125
126 GlobalProperty pc_compat_5_1[] = {
127 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
128 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
129 };
130 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
131
132 GlobalProperty pc_compat_5_0[] = {
133 };
134 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
135
136 GlobalProperty pc_compat_4_2[] = {
137 { "mch", "smbase-smram", "off" },
138 };
139 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
140
141 GlobalProperty pc_compat_4_1[] = {};
142 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
143
144 GlobalProperty pc_compat_4_0[] = {};
145 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
146
147 GlobalProperty pc_compat_3_1[] = {
148 { "intel-iommu", "dma-drain", "off" },
149 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
150 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
151 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
152 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
153 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
154 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
155 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
156 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
157 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
158 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
159 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
160 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
161 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
162 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
163 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
164 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
165 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
168 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
169 };
170 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
171
172 GlobalProperty pc_compat_3_0[] = {
173 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
174 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
175 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
176 };
177 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
178
179 GlobalProperty pc_compat_2_12[] = {
180 { TYPE_X86_CPU, "legacy-cache", "on" },
181 { TYPE_X86_CPU, "topoext", "off" },
182 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
183 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
184 };
185 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
186
187 GlobalProperty pc_compat_2_11[] = {
188 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
189 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
190 };
191 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
192
193 GlobalProperty pc_compat_2_10[] = {
194 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
195 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
196 { "q35-pcihost", "x-pci-hole64-fix", "off" },
197 };
198 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
199
200 GlobalProperty pc_compat_2_9[] = {
201 { "mch", "extended-tseg-mbytes", "0" },
202 };
203 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
204
205 GlobalProperty pc_compat_2_8[] = {
206 { TYPE_X86_CPU, "tcg-cpuid", "off" },
207 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
208 { "ICH9-LPC", "x-smi-broadcast", "off" },
209 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
210 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
211 };
212 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
213
214 GlobalProperty pc_compat_2_7[] = {
215 { TYPE_X86_CPU, "l3-cache", "off" },
216 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
217 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
218 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
219 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
220 { "isa-pcspk", "migrate", "off" },
221 };
222 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
223
224 GlobalProperty pc_compat_2_6[] = {
225 { TYPE_X86_CPU, "cpuid-0xb", "off" },
226 { "vmxnet3", "romfile", "" },
227 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
228 { "apic-common", "legacy-instance-id", "on", }
229 };
230 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
231
232 GlobalProperty pc_compat_2_5[] = {};
233 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
234
235 GlobalProperty pc_compat_2_4[] = {
236 PC_CPU_MODEL_IDS("2.4.0")
237 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
238 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
239 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
240 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
241 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
242 { TYPE_X86_CPU, "check", "off" },
243 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
244 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
245 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
246 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
247 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
248 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
249 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
250 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
251 };
252 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
253
254 GlobalProperty pc_compat_2_3[] = {
255 PC_CPU_MODEL_IDS("2.3.0")
256 { TYPE_X86_CPU, "arat", "off" },
257 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
258 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
259 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
260 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
261 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
262 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
263 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
264 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
265 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
266 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
267 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
268 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
276 };
277 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
278
279 GlobalProperty pc_compat_2_2[] = {
280 PC_CPU_MODEL_IDS("2.2.0")
281 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
282 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
283 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
284 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
285 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
286 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
287 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
288 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
296 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
297 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
298 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
299 };
300 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
301
302 GlobalProperty pc_compat_2_1[] = {
303 PC_CPU_MODEL_IDS("2.1.0")
304 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
305 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
306 };
307 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
308
309 GlobalProperty pc_compat_2_0[] = {
310 PC_CPU_MODEL_IDS("2.0.0")
311 { "virtio-scsi-pci", "any_layout", "off" },
312 { "PIIX4_PM", "memory-hotplug-support", "off" },
313 { "apic", "version", "0x11" },
314 { "nec-usb-xhci", "superspeed-ports-first", "off" },
315 { "nec-usb-xhci", "force-pcie-endcap", "on" },
316 { "pci-serial", "prog_if", "0" },
317 { "pci-serial-2x", "prog_if", "0" },
318 { "pci-serial-4x", "prog_if", "0" },
319 { "virtio-net-pci", "guest_announce", "off" },
320 { "ICH9-LPC", "memory-hotplug-support", "off" },
321 };
322 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
323
324 GlobalProperty pc_compat_1_7[] = {
325 PC_CPU_MODEL_IDS("1.7.0")
326 { TYPE_USB_DEVICE, "msos-desc", "no" },
327 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
328 { "hpet", HPET_INTCAP, "4" },
329 };
330 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
331
332 GlobalProperty pc_compat_1_6[] = {
333 PC_CPU_MODEL_IDS("1.6.0")
334 { "e1000", "mitigation", "off" },
335 { "qemu64-" TYPE_X86_CPU, "model", "2" },
336 { "qemu32-" TYPE_X86_CPU, "model", "3" },
337 { "i440FX-pcihost", "short_root_bus", "1" },
338 { "q35-pcihost", "short_root_bus", "1" },
339 };
340 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
341
342 GlobalProperty pc_compat_1_5[] = {
343 PC_CPU_MODEL_IDS("1.5.0")
344 { "Conroe-" TYPE_X86_CPU, "model", "2" },
345 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
346 { "Penryn-" TYPE_X86_CPU, "model", "2" },
347 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
348 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
349 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
350 { "virtio-net-pci", "any_layout", "off" },
351 { TYPE_X86_CPU, "pmu", "on" },
352 { "i440FX-pcihost", "short_root_bus", "0" },
353 { "q35-pcihost", "short_root_bus", "0" },
354 };
355 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
356
357 GlobalProperty pc_compat_1_4[] = {
358 PC_CPU_MODEL_IDS("1.4.0")
359 { "scsi-hd", "discard_granularity", "0" },
360 { "scsi-cd", "discard_granularity", "0" },
361 { "ide-hd", "discard_granularity", "0" },
362 { "ide-cd", "discard_granularity", "0" },
363 { "virtio-blk-pci", "discard_granularity", "0" },
364 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
365 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
366 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
367 { "e1000", "romfile", "pxe-e1000.rom" },
368 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
369 { "pcnet", "romfile", "pxe-pcnet.rom" },
370 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
371 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
372 { "486-" TYPE_X86_CPU, "model", "0" },
373 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
374 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
375 };
376 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
377
378 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
379 {
380 GSIState *s;
381
382 s = g_new0(GSIState, 1);
383 if (kvm_ioapic_in_kernel()) {
384 kvm_pc_setup_irq_routing(pci_enabled);
385 }
386 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
387
388 return s;
389 }
390
391 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
392 unsigned size)
393 {
394 }
395
396 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
397 {
398 return 0xffffffffffffffffULL;
399 }
400
401 /* MSDOS compatibility mode FPU exception support */
402 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
403 unsigned size)
404 {
405 if (tcg_enabled()) {
406 cpu_set_ignne();
407 }
408 }
409
410 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
411 {
412 return 0xffffffffffffffffULL;
413 }
414
415 /* PC cmos mappings */
416
417 #define REG_EQUIPMENT_BYTE 0x14
418
419 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
420 int16_t cylinders, int8_t heads, int8_t sectors)
421 {
422 rtc_set_memory(s, type_ofs, 47);
423 rtc_set_memory(s, info_ofs, cylinders);
424 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
425 rtc_set_memory(s, info_ofs + 2, heads);
426 rtc_set_memory(s, info_ofs + 3, 0xff);
427 rtc_set_memory(s, info_ofs + 4, 0xff);
428 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
429 rtc_set_memory(s, info_ofs + 6, cylinders);
430 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
431 rtc_set_memory(s, info_ofs + 8, sectors);
432 }
433
434 /* convert boot_device letter to something recognizable by the bios */
435 static int boot_device2nibble(char boot_device)
436 {
437 switch(boot_device) {
438 case 'a':
439 case 'b':
440 return 0x01; /* floppy boot */
441 case 'c':
442 return 0x02; /* hard drive boot */
443 case 'd':
444 return 0x03; /* CD-ROM boot */
445 case 'n':
446 return 0x04; /* Network boot */
447 }
448 return 0;
449 }
450
451 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
452 {
453 #define PC_MAX_BOOT_DEVICES 3
454 int nbds, bds[3] = { 0, };
455 int i;
456
457 nbds = strlen(boot_device);
458 if (nbds > PC_MAX_BOOT_DEVICES) {
459 error_setg(errp, "Too many boot devices for PC");
460 return;
461 }
462 for (i = 0; i < nbds; i++) {
463 bds[i] = boot_device2nibble(boot_device[i]);
464 if (bds[i] == 0) {
465 error_setg(errp, "Invalid boot device for PC: '%c'",
466 boot_device[i]);
467 return;
468 }
469 }
470 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
471 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
472 }
473
474 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
475 {
476 set_boot_dev(opaque, boot_device, errp);
477 }
478
479 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
480 {
481 int val, nb, i;
482 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
483 FLOPPY_DRIVE_TYPE_NONE };
484
485 /* floppy type */
486 if (floppy) {
487 for (i = 0; i < 2; i++) {
488 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
489 }
490 }
491 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
492 cmos_get_fd_drive_type(fd_type[1]);
493 rtc_set_memory(rtc_state, 0x10, val);
494
495 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
496 nb = 0;
497 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
498 nb++;
499 }
500 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
501 nb++;
502 }
503 switch (nb) {
504 case 0:
505 break;
506 case 1:
507 val |= 0x01; /* 1 drive, ready for boot */
508 break;
509 case 2:
510 val |= 0x41; /* 2 drives, ready for boot */
511 break;
512 }
513 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
514 }
515
516 typedef struct pc_cmos_init_late_arg {
517 ISADevice *rtc_state;
518 BusState *idebus[2];
519 } pc_cmos_init_late_arg;
520
521 typedef struct check_fdc_state {
522 ISADevice *floppy;
523 bool multiple;
524 } CheckFdcState;
525
526 static int check_fdc(Object *obj, void *opaque)
527 {
528 CheckFdcState *state = opaque;
529 Object *fdc;
530 uint32_t iobase;
531 Error *local_err = NULL;
532
533 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
534 if (!fdc) {
535 return 0;
536 }
537
538 iobase = object_property_get_uint(obj, "iobase", &local_err);
539 if (local_err || iobase != 0x3f0) {
540 error_free(local_err);
541 return 0;
542 }
543
544 if (state->floppy) {
545 state->multiple = true;
546 } else {
547 state->floppy = ISA_DEVICE(obj);
548 }
549 return 0;
550 }
551
552 static const char * const fdc_container_path[] = {
553 "/unattached", "/peripheral", "/peripheral-anon"
554 };
555
556 /*
557 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
558 * and ACPI objects.
559 */
560 ISADevice *pc_find_fdc0(void)
561 {
562 int i;
563 Object *container;
564 CheckFdcState state = { 0 };
565
566 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
567 container = container_get(qdev_get_machine(), fdc_container_path[i]);
568 object_child_foreach(container, check_fdc, &state);
569 }
570
571 if (state.multiple) {
572 warn_report("multiple floppy disk controllers with "
573 "iobase=0x3f0 have been found");
574 error_printf("the one being picked for CMOS setup might not reflect "
575 "your intent");
576 }
577
578 return state.floppy;
579 }
580
581 static void pc_cmos_init_late(void *opaque)
582 {
583 pc_cmos_init_late_arg *arg = opaque;
584 ISADevice *s = arg->rtc_state;
585 int16_t cylinders;
586 int8_t heads, sectors;
587 int val;
588 int i, trans;
589
590 val = 0;
591 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
592 &cylinders, &heads, &sectors) >= 0) {
593 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
594 val |= 0xf0;
595 }
596 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
597 &cylinders, &heads, &sectors) >= 0) {
598 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
599 val |= 0x0f;
600 }
601 rtc_set_memory(s, 0x12, val);
602
603 val = 0;
604 for (i = 0; i < 4; i++) {
605 /* NOTE: ide_get_geometry() returns the physical
606 geometry. It is always such that: 1 <= sects <= 63, 1
607 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
608 geometry can be different if a translation is done. */
609 if (arg->idebus[i / 2] &&
610 ide_get_geometry(arg->idebus[i / 2], i % 2,
611 &cylinders, &heads, &sectors) >= 0) {
612 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
613 assert((trans & ~3) == 0);
614 val |= trans << (i * 2);
615 }
616 }
617 rtc_set_memory(s, 0x39, val);
618
619 pc_cmos_init_floppy(s, pc_find_fdc0());
620
621 qemu_unregister_reset(pc_cmos_init_late, opaque);
622 }
623
624 void pc_cmos_init(PCMachineState *pcms,
625 BusState *idebus0, BusState *idebus1,
626 ISADevice *s)
627 {
628 int val;
629 static pc_cmos_init_late_arg arg;
630 X86MachineState *x86ms = X86_MACHINE(pcms);
631
632 /* various important CMOS locations needed by PC/Bochs bios */
633
634 /* memory size */
635 /* base memory (first MiB) */
636 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
637 rtc_set_memory(s, 0x15, val);
638 rtc_set_memory(s, 0x16, val >> 8);
639 /* extended memory (next 64MiB) */
640 if (x86ms->below_4g_mem_size > 1 * MiB) {
641 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
642 } else {
643 val = 0;
644 }
645 if (val > 65535)
646 val = 65535;
647 rtc_set_memory(s, 0x17, val);
648 rtc_set_memory(s, 0x18, val >> 8);
649 rtc_set_memory(s, 0x30, val);
650 rtc_set_memory(s, 0x31, val >> 8);
651 /* memory between 16MiB and 4GiB */
652 if (x86ms->below_4g_mem_size > 16 * MiB) {
653 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
654 } else {
655 val = 0;
656 }
657 if (val > 65535)
658 val = 65535;
659 rtc_set_memory(s, 0x34, val);
660 rtc_set_memory(s, 0x35, val >> 8);
661 /* memory above 4GiB */
662 val = x86ms->above_4g_mem_size / 65536;
663 rtc_set_memory(s, 0x5b, val);
664 rtc_set_memory(s, 0x5c, val >> 8);
665 rtc_set_memory(s, 0x5d, val >> 16);
666
667 object_property_add_link(OBJECT(pcms), "rtc_state",
668 TYPE_ISA_DEVICE,
669 (Object **)&x86ms->rtc,
670 object_property_allow_set_link,
671 OBJ_PROP_LINK_STRONG);
672 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
673 &error_abort);
674
675 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
676
677 val = 0;
678 val |= 0x02; /* FPU is there */
679 val |= 0x04; /* PS/2 mouse installed */
680 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
681
682 /* hard drives and FDC */
683 arg.rtc_state = s;
684 arg.idebus[0] = idebus0;
685 arg.idebus[1] = idebus1;
686 qemu_register_reset(pc_cmos_init_late, &arg);
687 }
688
689 static void handle_a20_line_change(void *opaque, int irq, int level)
690 {
691 X86CPU *cpu = opaque;
692
693 /* XXX: send to all CPUs ? */
694 /* XXX: add logic to handle multiple A20 line sources */
695 x86_cpu_set_a20(cpu, level);
696 }
697
698 #define NE2000_NB_MAX 6
699
700 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
701 0x280, 0x380 };
702 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
703
704 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
705 {
706 static int nb_ne2k = 0;
707
708 if (nb_ne2k == NE2000_NB_MAX)
709 return;
710 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
711 ne2000_irq[nb_ne2k], nd);
712 nb_ne2k++;
713 }
714
715 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
716 {
717 X86CPU *cpu = opaque;
718
719 if (level) {
720 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
721 }
722 }
723
724 static
725 void pc_machine_done(Notifier *notifier, void *data)
726 {
727 PCMachineState *pcms = container_of(notifier,
728 PCMachineState, machine_done);
729 X86MachineState *x86ms = X86_MACHINE(pcms);
730
731 /* set the number of CPUs */
732 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
733
734 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
735
736 acpi_setup();
737 if (x86ms->fw_cfg) {
738 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
739 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
740 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
741 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
742 }
743
744
745 if (x86ms->apic_id_limit > 255 && !xen_enabled() &&
746 !kvm_irqchip_in_kernel()) {
747 error_report("current -smp configuration requires kernel "
748 "irqchip support.");
749 exit(EXIT_FAILURE);
750 }
751 }
752
753 void pc_guest_info_init(PCMachineState *pcms)
754 {
755 X86MachineState *x86ms = X86_MACHINE(pcms);
756
757 x86ms->apic_xrupt_override = true;
758 pcms->machine_done.notify = pc_machine_done;
759 qemu_add_machine_init_done_notifier(&pcms->machine_done);
760 }
761
762 /* setup pci memory address space mapping into system address space */
763 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
764 MemoryRegion *pci_address_space)
765 {
766 /* Set to lower priority than RAM */
767 memory_region_add_subregion_overlap(system_memory, 0x0,
768 pci_address_space, -1);
769 }
770
771 void xen_load_linux(PCMachineState *pcms)
772 {
773 int i;
774 FWCfgState *fw_cfg;
775 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
776 X86MachineState *x86ms = X86_MACHINE(pcms);
777
778 assert(MACHINE(pcms)->kernel_filename != NULL);
779
780 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
781 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
782 rom_set_fw(fw_cfg);
783
784 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
785 pcmc->pvh_enabled);
786 for (i = 0; i < nb_option_roms; i++) {
787 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
788 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
789 !strcmp(option_rom[i].name, "pvh.bin") ||
790 !strcmp(option_rom[i].name, "multiboot.bin") ||
791 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
792 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
793 }
794 x86ms->fw_cfg = fw_cfg;
795 }
796
797 #define PC_ROM_MIN_VGA 0xc0000
798 #define PC_ROM_MIN_OPTION 0xc8000
799 #define PC_ROM_MAX 0xe0000
800 #define PC_ROM_ALIGN 0x800
801 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
802
803 void pc_memory_init(PCMachineState *pcms,
804 MemoryRegion *system_memory,
805 MemoryRegion *rom_memory,
806 MemoryRegion **ram_memory)
807 {
808 int linux_boot, i;
809 MemoryRegion *option_rom_mr;
810 MemoryRegion *ram_below_4g, *ram_above_4g;
811 FWCfgState *fw_cfg;
812 MachineState *machine = MACHINE(pcms);
813 MachineClass *mc = MACHINE_GET_CLASS(machine);
814 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
815 X86MachineState *x86ms = X86_MACHINE(pcms);
816
817 assert(machine->ram_size == x86ms->below_4g_mem_size +
818 x86ms->above_4g_mem_size);
819
820 linux_boot = (machine->kernel_filename != NULL);
821
822 /*
823 * Split single memory region and use aliases to address portions of it,
824 * done for backwards compatibility with older qemus.
825 */
826 *ram_memory = machine->ram;
827 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
828 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
829 0, x86ms->below_4g_mem_size);
830 memory_region_add_subregion(system_memory, 0, ram_below_4g);
831 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
832 if (x86ms->above_4g_mem_size > 0) {
833 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
834 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
835 machine->ram,
836 x86ms->below_4g_mem_size,
837 x86ms->above_4g_mem_size);
838 memory_region_add_subregion(system_memory, 0x100000000ULL,
839 ram_above_4g);
840 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
841 }
842
843 if (pcms->sgx_epc.size != 0) {
844 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
845 }
846
847 if (!pcmc->has_reserved_memory &&
848 (machine->ram_slots ||
849 (machine->maxram_size > machine->ram_size))) {
850
851 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
852 mc->name);
853 exit(EXIT_FAILURE);
854 }
855
856 /* always allocate the device memory information */
857 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
858
859 /* initialize device memory address space */
860 if (pcmc->has_reserved_memory &&
861 (machine->ram_size < machine->maxram_size)) {
862 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
863
864 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
865 error_report("unsupported amount of memory slots: %"PRIu64,
866 machine->ram_slots);
867 exit(EXIT_FAILURE);
868 }
869
870 if (QEMU_ALIGN_UP(machine->maxram_size,
871 TARGET_PAGE_SIZE) != machine->maxram_size) {
872 error_report("maximum memory size must by aligned to multiple of "
873 "%d bytes", TARGET_PAGE_SIZE);
874 exit(EXIT_FAILURE);
875 }
876
877 if (pcms->sgx_epc.size != 0) {
878 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc);
879 } else {
880 machine->device_memory->base =
881 0x100000000ULL + x86ms->above_4g_mem_size;
882 }
883
884 machine->device_memory->base =
885 ROUND_UP(machine->device_memory->base, 1 * GiB);
886
887 if (pcmc->enforce_aligned_dimm) {
888 /* size device region assuming 1G page max alignment per slot */
889 device_mem_size += (1 * GiB) * machine->ram_slots;
890 }
891
892 if ((machine->device_memory->base + device_mem_size) <
893 device_mem_size) {
894 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
895 machine->maxram_size);
896 exit(EXIT_FAILURE);
897 }
898
899 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
900 "device-memory", device_mem_size);
901 memory_region_add_subregion(system_memory, machine->device_memory->base,
902 &machine->device_memory->mr);
903 }
904
905 /* Initialize PC system firmware */
906 pc_system_firmware_init(pcms, rom_memory);
907
908 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
909 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
910 &error_fatal);
911 if (pcmc->pci_enabled) {
912 memory_region_set_readonly(option_rom_mr, true);
913 }
914 memory_region_add_subregion_overlap(rom_memory,
915 PC_ROM_MIN_VGA,
916 option_rom_mr,
917 1);
918
919 fw_cfg = fw_cfg_arch_create(machine,
920 x86ms->boot_cpus, x86ms->apic_id_limit);
921
922 rom_set_fw(fw_cfg);
923
924 if (pcmc->has_reserved_memory && machine->device_memory->base) {
925 uint64_t *val = g_malloc(sizeof(*val));
926 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
927 uint64_t res_mem_end = machine->device_memory->base;
928
929 if (!pcmc->broken_reserved_end) {
930 res_mem_end += memory_region_size(&machine->device_memory->mr);
931 }
932 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
933 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
934 }
935
936 if (linux_boot) {
937 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
938 pcmc->pvh_enabled);
939 }
940
941 for (i = 0; i < nb_option_roms; i++) {
942 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
943 }
944 x86ms->fw_cfg = fw_cfg;
945
946 /* Init default IOAPIC address space */
947 x86ms->ioapic_as = &address_space_memory;
948
949 /* Init ACPI memory hotplug IO base address */
950 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
951 }
952
953 /*
954 * The 64bit pci hole starts after "above 4G RAM" and
955 * potentially the space reserved for memory hotplug.
956 */
957 uint64_t pc_pci_hole64_start(void)
958 {
959 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
960 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
961 MachineState *ms = MACHINE(pcms);
962 X86MachineState *x86ms = X86_MACHINE(pcms);
963 uint64_t hole64_start = 0;
964
965 if (pcmc->has_reserved_memory && ms->device_memory->base) {
966 hole64_start = ms->device_memory->base;
967 if (!pcmc->broken_reserved_end) {
968 hole64_start += memory_region_size(&ms->device_memory->mr);
969 }
970 } else if (pcms->sgx_epc.size != 0) {
971 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc);
972 } else {
973 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
974 }
975
976 return ROUND_UP(hole64_start, 1 * GiB);
977 }
978
979 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
980 {
981 DeviceState *dev = NULL;
982
983 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
984 if (pci_bus) {
985 PCIDevice *pcidev = pci_vga_init(pci_bus);
986 dev = pcidev ? &pcidev->qdev : NULL;
987 } else if (isa_bus) {
988 ISADevice *isadev = isa_vga_init(isa_bus);
989 dev = isadev ? DEVICE(isadev) : NULL;
990 }
991 rom_reset_order_override();
992 return dev;
993 }
994
995 static const MemoryRegionOps ioport80_io_ops = {
996 .write = ioport80_write,
997 .read = ioport80_read,
998 .endianness = DEVICE_NATIVE_ENDIAN,
999 .impl = {
1000 .min_access_size = 1,
1001 .max_access_size = 1,
1002 },
1003 };
1004
1005 static const MemoryRegionOps ioportF0_io_ops = {
1006 .write = ioportF0_write,
1007 .read = ioportF0_read,
1008 .endianness = DEVICE_NATIVE_ENDIAN,
1009 .impl = {
1010 .min_access_size = 1,
1011 .max_access_size = 1,
1012 },
1013 };
1014
1015 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1016 bool create_i8042, bool no_vmport)
1017 {
1018 int i;
1019 DriveInfo *fd[MAX_FD];
1020 qemu_irq *a20_line;
1021 ISADevice *fdc, *i8042, *port92, *vmmouse;
1022
1023 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1024 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1025
1026 for (i = 0; i < MAX_FD; i++) {
1027 fd[i] = drive_get(IF_FLOPPY, 0, i);
1028 create_fdctrl |= !!fd[i];
1029 }
1030 if (create_fdctrl) {
1031 fdc = isa_new(TYPE_ISA_FDC);
1032 if (fdc) {
1033 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1034 isa_fdc_init_drives(fdc, fd);
1035 }
1036 }
1037
1038 if (!create_i8042) {
1039 return;
1040 }
1041
1042 i8042 = isa_create_simple(isa_bus, "i8042");
1043 if (!no_vmport) {
1044 isa_create_simple(isa_bus, TYPE_VMPORT);
1045 vmmouse = isa_try_new("vmmouse");
1046 } else {
1047 vmmouse = NULL;
1048 }
1049 if (vmmouse) {
1050 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1051 &error_abort);
1052 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1053 }
1054 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1055
1056 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1057 i8042_setup_a20_line(i8042, a20_line[0]);
1058 qdev_connect_gpio_out_named(DEVICE(port92),
1059 PORT92_A20_LINE, 0, a20_line[1]);
1060 g_free(a20_line);
1061 }
1062
1063 void pc_basic_device_init(struct PCMachineState *pcms,
1064 ISABus *isa_bus, qemu_irq *gsi,
1065 ISADevice **rtc_state,
1066 bool create_fdctrl,
1067 uint32_t hpet_irqs)
1068 {
1069 int i;
1070 DeviceState *hpet = NULL;
1071 int pit_isa_irq = 0;
1072 qemu_irq pit_alt_irq = NULL;
1073 qemu_irq rtc_irq = NULL;
1074 ISADevice *pit = NULL;
1075 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1076 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1077
1078 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1079 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1080
1081 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1082 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1083
1084 /*
1085 * Check if an HPET shall be created.
1086 *
1087 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1088 * when the HPET wants to take over. Thus we have to disable the latter.
1089 */
1090 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1091 kvm_has_pit_state2())) {
1092 hpet = qdev_try_new(TYPE_HPET);
1093 if (!hpet) {
1094 error_report("couldn't create HPET device");
1095 exit(1);
1096 }
1097 /*
1098 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1099 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1100 * IRQ2.
1101 */
1102 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1103 HPET_INTCAP, NULL);
1104 if (!compat) {
1105 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1106 }
1107 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1108 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1109
1110 for (i = 0; i < GSI_NUM_PINS; i++) {
1111 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1112 }
1113 pit_isa_irq = -1;
1114 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1115 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1116 }
1117 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1118
1119 qemu_register_boot_set(pc_boot_set, *rtc_state);
1120
1121 if (!xen_enabled() && pcms->pit_enabled) {
1122 if (kvm_pit_in_kernel()) {
1123 pit = kvm_pit_init(isa_bus, 0x40);
1124 } else {
1125 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1126 }
1127 if (hpet) {
1128 /* connect PIT to output control line of the HPET */
1129 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1130 }
1131 pcspk_init(pcms->pcspk, isa_bus, pit);
1132 }
1133
1134 i8257_dma_init(isa_bus, 0);
1135
1136 /* Super I/O */
1137 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1138 pcms->vmport != ON_OFF_AUTO_ON);
1139 }
1140
1141 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1142 {
1143 int i;
1144
1145 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1146 for (i = 0; i < nb_nics; i++) {
1147 NICInfo *nd = &nd_table[i];
1148 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1149
1150 if (g_str_equal(model, "ne2k_isa")) {
1151 pc_init_ne2k_isa(isa_bus, nd);
1152 } else {
1153 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1154 }
1155 }
1156 rom_reset_order_override();
1157 }
1158
1159 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1160 {
1161 qemu_irq *i8259;
1162
1163 if (kvm_pic_in_kernel()) {
1164 i8259 = kvm_i8259_init(isa_bus);
1165 } else if (xen_enabled()) {
1166 i8259 = xen_interrupt_controller_init();
1167 } else {
1168 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1169 }
1170
1171 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1172 i8259_irqs[i] = i8259[i];
1173 }
1174
1175 g_free(i8259);
1176 }
1177
1178 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1179 Error **errp)
1180 {
1181 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1182 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1183 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1184 const MachineState *ms = MACHINE(hotplug_dev);
1185 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1186 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1187 Error *local_err = NULL;
1188
1189 /*
1190 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1191 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1192 * addition to cover this case.
1193 */
1194 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1195 error_setg(errp,
1196 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1197 return;
1198 }
1199
1200 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1201 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1202 return;
1203 }
1204
1205 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1206 if (local_err) {
1207 error_propagate(errp, local_err);
1208 return;
1209 }
1210
1211 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1212 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1213 }
1214
1215 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1216 DeviceState *dev, Error **errp)
1217 {
1218 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1219 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1220 MachineState *ms = MACHINE(hotplug_dev);
1221 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1222
1223 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1224
1225 if (is_nvdimm) {
1226 nvdimm_plug(ms->nvdimms_state);
1227 }
1228
1229 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1230 }
1231
1232 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1233 DeviceState *dev, Error **errp)
1234 {
1235 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1236
1237 /*
1238 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1239 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1240 * addition to cover this case.
1241 */
1242 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1243 error_setg(errp,
1244 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1245 return;
1246 }
1247
1248 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1249 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1250 return;
1251 }
1252
1253 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1254 errp);
1255 }
1256
1257 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1258 DeviceState *dev, Error **errp)
1259 {
1260 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1261 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1262 Error *local_err = NULL;
1263
1264 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1265 if (local_err) {
1266 goto out;
1267 }
1268
1269 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1270 qdev_unrealize(dev);
1271 out:
1272 error_propagate(errp, local_err);
1273 }
1274
1275 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1276 DeviceState *dev, Error **errp)
1277 {
1278 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1279 Error *local_err = NULL;
1280
1281 if (!hotplug_dev2 && dev->hotplugged) {
1282 /*
1283 * Without a bus hotplug handler, we cannot control the plug/unplug
1284 * order. We should never reach this point when hotplugging on x86,
1285 * however, better add a safety net.
1286 */
1287 error_setg(errp, "hotplug of virtio based memory devices not supported"
1288 " on this bus.");
1289 return;
1290 }
1291 /*
1292 * First, see if we can plug this memory device at all. If that
1293 * succeeds, branch of to the actual hotplug handler.
1294 */
1295 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1296 &local_err);
1297 if (!local_err && hotplug_dev2) {
1298 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1299 }
1300 error_propagate(errp, local_err);
1301 }
1302
1303 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1304 DeviceState *dev, Error **errp)
1305 {
1306 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1307 Error *local_err = NULL;
1308
1309 /*
1310 * Plug the memory device first and then branch off to the actual
1311 * hotplug handler. If that one fails, we can easily undo the memory
1312 * device bits.
1313 */
1314 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1315 if (hotplug_dev2) {
1316 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1317 if (local_err) {
1318 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1319 }
1320 }
1321 error_propagate(errp, local_err);
1322 }
1323
1324 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1325 DeviceState *dev, Error **errp)
1326 {
1327 /* We don't support hot unplug of virtio based memory devices */
1328 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1329 }
1330
1331 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1332 DeviceState *dev, Error **errp)
1333 {
1334 /* We don't support hot unplug of virtio based memory devices */
1335 }
1336
1337 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1338 DeviceState *dev, Error **errp)
1339 {
1340 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1341 pc_memory_pre_plug(hotplug_dev, dev, errp);
1342 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1343 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1344 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1345 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1346 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1347 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1348 /* Declare the APIC range as the reserved MSI region */
1349 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1350 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1351
1352 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1353 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1354 resv_prop_str, errp);
1355 g_free(resv_prop_str);
1356 }
1357
1358 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1359 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1360 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1361
1362 if (pcms->iommu) {
1363 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1364 "for x86 yet.");
1365 return;
1366 }
1367 pcms->iommu = dev;
1368 }
1369 }
1370
1371 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1372 DeviceState *dev, Error **errp)
1373 {
1374 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1375 pc_memory_plug(hotplug_dev, dev, errp);
1376 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1377 x86_cpu_plug(hotplug_dev, dev, errp);
1378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1379 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1380 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1381 }
1382 }
1383
1384 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1385 DeviceState *dev, Error **errp)
1386 {
1387 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1388 pc_memory_unplug_request(hotplug_dev, dev, errp);
1389 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1390 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1391 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1392 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1393 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1394 } else {
1395 error_setg(errp, "acpi: device unplug request for not supported device"
1396 " type: %s", object_get_typename(OBJECT(dev)));
1397 }
1398 }
1399
1400 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1401 DeviceState *dev, Error **errp)
1402 {
1403 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1404 pc_memory_unplug(hotplug_dev, dev, errp);
1405 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1406 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1408 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1409 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1410 } else {
1411 error_setg(errp, "acpi: device unplug for not supported device"
1412 " type: %s", object_get_typename(OBJECT(dev)));
1413 }
1414 }
1415
1416 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1417 DeviceState *dev)
1418 {
1419 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1420 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1421 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1422 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1423 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1424 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1425 return HOTPLUG_HANDLER(machine);
1426 }
1427
1428 return NULL;
1429 }
1430
1431 static void
1432 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1433 const char *name, void *opaque,
1434 Error **errp)
1435 {
1436 MachineState *ms = MACHINE(obj);
1437 int64_t value = 0;
1438
1439 if (ms->device_memory) {
1440 value = memory_region_size(&ms->device_memory->mr);
1441 }
1442
1443 visit_type_int(v, name, &value, errp);
1444 }
1445
1446 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1447 void *opaque, Error **errp)
1448 {
1449 PCMachineState *pcms = PC_MACHINE(obj);
1450 OnOffAuto vmport = pcms->vmport;
1451
1452 visit_type_OnOffAuto(v, name, &vmport, errp);
1453 }
1454
1455 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1456 void *opaque, Error **errp)
1457 {
1458 PCMachineState *pcms = PC_MACHINE(obj);
1459
1460 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1461 }
1462
1463 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1464 {
1465 PCMachineState *pcms = PC_MACHINE(obj);
1466
1467 return pcms->smbus_enabled;
1468 }
1469
1470 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1471 {
1472 PCMachineState *pcms = PC_MACHINE(obj);
1473
1474 pcms->smbus_enabled = value;
1475 }
1476
1477 static bool pc_machine_get_sata(Object *obj, Error **errp)
1478 {
1479 PCMachineState *pcms = PC_MACHINE(obj);
1480
1481 return pcms->sata_enabled;
1482 }
1483
1484 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1485 {
1486 PCMachineState *pcms = PC_MACHINE(obj);
1487
1488 pcms->sata_enabled = value;
1489 }
1490
1491 static bool pc_machine_get_pit(Object *obj, Error **errp)
1492 {
1493 PCMachineState *pcms = PC_MACHINE(obj);
1494
1495 return pcms->pit_enabled;
1496 }
1497
1498 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1499 {
1500 PCMachineState *pcms = PC_MACHINE(obj);
1501
1502 pcms->pit_enabled = value;
1503 }
1504
1505 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1506 {
1507 PCMachineState *pcms = PC_MACHINE(obj);
1508
1509 return pcms->hpet_enabled;
1510 }
1511
1512 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1513 {
1514 PCMachineState *pcms = PC_MACHINE(obj);
1515
1516 pcms->hpet_enabled = value;
1517 }
1518
1519 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1520 {
1521 PCMachineState *pcms = PC_MACHINE(obj);
1522
1523 return pcms->i8042_enabled;
1524 }
1525
1526 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1527 {
1528 PCMachineState *pcms = PC_MACHINE(obj);
1529
1530 pcms->i8042_enabled = value;
1531 }
1532
1533 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1534 {
1535 PCMachineState *pcms = PC_MACHINE(obj);
1536
1537 return pcms->default_bus_bypass_iommu;
1538 }
1539
1540 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1541 Error **errp)
1542 {
1543 PCMachineState *pcms = PC_MACHINE(obj);
1544
1545 pcms->default_bus_bypass_iommu = value;
1546 }
1547
1548 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1549 void *opaque, Error **errp)
1550 {
1551 PCMachineState *pcms = PC_MACHINE(obj);
1552 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1553
1554 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1555 }
1556
1557 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1558 void *opaque, Error **errp)
1559 {
1560 PCMachineState *pcms = PC_MACHINE(obj);
1561
1562 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1563 }
1564
1565 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1566 const char *name, void *opaque,
1567 Error **errp)
1568 {
1569 PCMachineState *pcms = PC_MACHINE(obj);
1570 uint64_t value = pcms->max_ram_below_4g;
1571
1572 visit_type_size(v, name, &value, errp);
1573 }
1574
1575 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1576 const char *name, void *opaque,
1577 Error **errp)
1578 {
1579 PCMachineState *pcms = PC_MACHINE(obj);
1580 uint64_t value;
1581
1582 if (!visit_type_size(v, name, &value, errp)) {
1583 return;
1584 }
1585 if (value > 4 * GiB) {
1586 error_setg(errp,
1587 "Machine option 'max-ram-below-4g=%"PRIu64
1588 "' expects size less than or equal to 4G", value);
1589 return;
1590 }
1591
1592 if (value < 1 * MiB) {
1593 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1594 "BIOS may not work with less than 1MiB", value);
1595 }
1596
1597 pcms->max_ram_below_4g = value;
1598 }
1599
1600 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1601 const char *name, void *opaque,
1602 Error **errp)
1603 {
1604 PCMachineState *pcms = PC_MACHINE(obj);
1605 uint64_t value = pcms->max_fw_size;
1606
1607 visit_type_size(v, name, &value, errp);
1608 }
1609
1610 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1611 const char *name, void *opaque,
1612 Error **errp)
1613 {
1614 PCMachineState *pcms = PC_MACHINE(obj);
1615 Error *error = NULL;
1616 uint64_t value;
1617
1618 visit_type_size(v, name, &value, &error);
1619 if (error) {
1620 error_propagate(errp, error);
1621 return;
1622 }
1623
1624 /*
1625 * We don't have a theoretically justifiable exact lower bound on the base
1626 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1627 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1628 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1629 * size.
1630 */
1631 if (value > 16 * MiB) {
1632 error_setg(errp,
1633 "User specified max allowed firmware size %" PRIu64 " is "
1634 "greater than 16MiB. If combined firwmare size exceeds "
1635 "16MiB the system may not boot, or experience intermittent"
1636 "stability issues.",
1637 value);
1638 return;
1639 }
1640
1641 pcms->max_fw_size = value;
1642 }
1643
1644
1645 static void pc_machine_initfn(Object *obj)
1646 {
1647 PCMachineState *pcms = PC_MACHINE(obj);
1648
1649 #ifdef CONFIG_VMPORT
1650 pcms->vmport = ON_OFF_AUTO_AUTO;
1651 #else
1652 pcms->vmport = ON_OFF_AUTO_OFF;
1653 #endif /* CONFIG_VMPORT */
1654 pcms->max_ram_below_4g = 0; /* use default */
1655 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1656
1657 /* acpi build is enabled by default if machine supports it */
1658 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1659 pcms->smbus_enabled = true;
1660 pcms->sata_enabled = true;
1661 pcms->pit_enabled = true;
1662 pcms->i8042_enabled = true;
1663 pcms->max_fw_size = 8 * MiB;
1664 #ifdef CONFIG_HPET
1665 pcms->hpet_enabled = true;
1666 #endif
1667 pcms->default_bus_bypass_iommu = false;
1668
1669 pc_system_flash_create(pcms);
1670 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1671 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1672 OBJECT(pcms->pcspk), "audiodev");
1673 }
1674
1675 static void pc_machine_reset(MachineState *machine)
1676 {
1677 CPUState *cs;
1678 X86CPU *cpu;
1679
1680 qemu_devices_reset();
1681
1682 /* Reset APIC after devices have been reset to cancel
1683 * any changes that qemu_devices_reset() might have done.
1684 */
1685 CPU_FOREACH(cs) {
1686 cpu = X86_CPU(cs);
1687
1688 if (cpu->apic_state) {
1689 device_legacy_reset(cpu->apic_state);
1690 }
1691 }
1692 }
1693
1694 static void pc_machine_wakeup(MachineState *machine)
1695 {
1696 cpu_synchronize_all_states();
1697 pc_machine_reset(machine);
1698 cpu_synchronize_all_post_reset();
1699 }
1700
1701 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1702 {
1703 X86IOMMUState *iommu = x86_iommu_get_default();
1704 IntelIOMMUState *intel_iommu;
1705
1706 if (iommu &&
1707 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1708 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1709 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1710 if (!intel_iommu->caching_mode) {
1711 error_setg(errp, "Device assignment is not allowed without "
1712 "enabling caching-mode=on for Intel IOMMU.");
1713 return false;
1714 }
1715 }
1716
1717 return true;
1718 }
1719
1720 static void pc_machine_class_init(ObjectClass *oc, void *data)
1721 {
1722 MachineClass *mc = MACHINE_CLASS(oc);
1723 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1724 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1725
1726 pcmc->pci_enabled = true;
1727 pcmc->has_acpi_build = true;
1728 pcmc->rsdp_in_ram = true;
1729 pcmc->smbios_defaults = true;
1730 pcmc->smbios_uuid_encoded = true;
1731 pcmc->gigabyte_align = true;
1732 pcmc->has_reserved_memory = true;
1733 pcmc->kvmclock_enabled = true;
1734 pcmc->enforce_aligned_dimm = true;
1735 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1736 * to be used at the moment, 32K should be enough for a while. */
1737 pcmc->acpi_data_size = 0x20000 + 0x8000;
1738 pcmc->pvh_enabled = true;
1739 pcmc->kvmclock_create_always = true;
1740 assert(!mc->get_hotplug_handler);
1741 mc->get_hotplug_handler = pc_get_hotplug_handler;
1742 mc->hotplug_allowed = pc_hotplug_allowed;
1743 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1744 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1745 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1746 mc->auto_enable_numa_with_memhp = true;
1747 mc->auto_enable_numa_with_memdev = true;
1748 mc->has_hotpluggable_cpus = true;
1749 mc->default_boot_order = "cad";
1750 mc->block_default_type = IF_IDE;
1751 mc->max_cpus = 255;
1752 mc->reset = pc_machine_reset;
1753 mc->wakeup = pc_machine_wakeup;
1754 hc->pre_plug = pc_machine_device_pre_plug_cb;
1755 hc->plug = pc_machine_device_plug_cb;
1756 hc->unplug_request = pc_machine_device_unplug_request_cb;
1757 hc->unplug = pc_machine_device_unplug_cb;
1758 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1759 mc->nvdimm_supported = true;
1760 mc->smp_props.dies_supported = true;
1761 mc->default_ram_id = "pc.ram";
1762
1763 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1764 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1765 NULL, NULL);
1766 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1767 "Maximum ram below the 4G boundary (32bit boundary)");
1768
1769 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1770 pc_machine_get_device_memory_region_size, NULL,
1771 NULL, NULL);
1772
1773 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1774 pc_machine_get_vmport, pc_machine_set_vmport,
1775 NULL, NULL);
1776 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1777 "Enable vmport (pc & q35)");
1778
1779 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1780 pc_machine_get_smbus, pc_machine_set_smbus);
1781 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1782 "Enable/disable system management bus");
1783
1784 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1785 pc_machine_get_sata, pc_machine_set_sata);
1786 object_class_property_set_description(oc, PC_MACHINE_SATA,
1787 "Enable/disable Serial ATA bus");
1788
1789 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1790 pc_machine_get_pit, pc_machine_set_pit);
1791 object_class_property_set_description(oc, PC_MACHINE_PIT,
1792 "Enable/disable Intel 8254 programmable interval timer emulation");
1793
1794 object_class_property_add_bool(oc, "hpet",
1795 pc_machine_get_hpet, pc_machine_set_hpet);
1796 object_class_property_set_description(oc, "hpet",
1797 "Enable/disable high precision event timer emulation");
1798
1799 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1800 pc_machine_get_i8042, pc_machine_set_i8042);
1801
1802 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1803 pc_machine_get_default_bus_bypass_iommu,
1804 pc_machine_set_default_bus_bypass_iommu);
1805
1806 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1807 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1808 NULL, NULL);
1809 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1810 "Maximum combined firmware size");
1811
1812 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1813 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1814 NULL, NULL);
1815 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1816 "SMBIOS Entry Point type [32, 64]");
1817 }
1818
1819 static const TypeInfo pc_machine_info = {
1820 .name = TYPE_PC_MACHINE,
1821 .parent = TYPE_X86_MACHINE,
1822 .abstract = true,
1823 .instance_size = sizeof(PCMachineState),
1824 .instance_init = pc_machine_initfn,
1825 .class_size = sizeof(PCMachineClass),
1826 .class_init = pc_machine_class_init,
1827 .interfaces = (InterfaceInfo[]) {
1828 { TYPE_HOTPLUG_HANDLER },
1829 { }
1830 },
1831 };
1832
1833 static void pc_machine_register_types(void)
1834 {
1835 type_register_static(&pc_machine_info);
1836 }
1837
1838 type_init(pc_machine_register_types)
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