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hw/i386/pc: Inline port92_init()
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "qapi/error.h"
80 #include "qapi/qapi-visit-common.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/mem/memory-device.h"
89 #include "sysemu/replay.h"
90 #include "qapi/qmp/qerror.h"
91 #include "config-devices.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95
96 GlobalProperty pc_compat_4_2[] = {};
97 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
98
99 GlobalProperty pc_compat_4_1[] = {};
100 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
101
102 GlobalProperty pc_compat_4_0[] = {};
103 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
104
105 GlobalProperty pc_compat_3_1[] = {
106 { "intel-iommu", "dma-drain", "off" },
107 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
108 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
109 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
110 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
111 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
112 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
113 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
114 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
115 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
116 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
117 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
119 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
120 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
121 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
122 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
123 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
124 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
125 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
126 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
127 };
128 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
129
130 GlobalProperty pc_compat_3_0[] = {
131 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
132 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
133 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
134 };
135 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
136
137 GlobalProperty pc_compat_2_12[] = {
138 { TYPE_X86_CPU, "legacy-cache", "on" },
139 { TYPE_X86_CPU, "topoext", "off" },
140 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
141 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
142 };
143 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
144
145 GlobalProperty pc_compat_2_11[] = {
146 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
147 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
148 };
149 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
150
151 GlobalProperty pc_compat_2_10[] = {
152 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
153 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
154 { "q35-pcihost", "x-pci-hole64-fix", "off" },
155 };
156 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
157
158 GlobalProperty pc_compat_2_9[] = {
159 { "mch", "extended-tseg-mbytes", "0" },
160 };
161 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
162
163 GlobalProperty pc_compat_2_8[] = {
164 { TYPE_X86_CPU, "tcg-cpuid", "off" },
165 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
166 { "ICH9-LPC", "x-smi-broadcast", "off" },
167 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
168 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
169 };
170 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
171
172 GlobalProperty pc_compat_2_7[] = {
173 { TYPE_X86_CPU, "l3-cache", "off" },
174 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
175 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
176 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
177 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
178 { "isa-pcspk", "migrate", "off" },
179 };
180 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
181
182 GlobalProperty pc_compat_2_6[] = {
183 { TYPE_X86_CPU, "cpuid-0xb", "off" },
184 { "vmxnet3", "romfile", "" },
185 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
186 { "apic-common", "legacy-instance-id", "on", }
187 };
188 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
189
190 GlobalProperty pc_compat_2_5[] = {};
191 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
192
193 GlobalProperty pc_compat_2_4[] = {
194 PC_CPU_MODEL_IDS("2.4.0")
195 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
196 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
197 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
198 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
199 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
200 { TYPE_X86_CPU, "check", "off" },
201 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
202 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
203 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
204 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
205 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
206 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
207 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
208 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
209 };
210 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
211
212 GlobalProperty pc_compat_2_3[] = {
213 PC_CPU_MODEL_IDS("2.3.0")
214 { TYPE_X86_CPU, "arat", "off" },
215 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
216 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
217 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
218 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
219 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
220 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
221 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
222 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
223 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
224 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
225 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
226 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
227 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
228 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
229 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
234 };
235 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
236
237 GlobalProperty pc_compat_2_2[] = {
238 PC_CPU_MODEL_IDS("2.2.0")
239 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
240 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
241 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
242 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
243 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
244 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
245 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
246 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
247 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
256 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
257 };
258 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
259
260 GlobalProperty pc_compat_2_1[] = {
261 PC_CPU_MODEL_IDS("2.1.0")
262 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
263 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
264 };
265 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
266
267 GlobalProperty pc_compat_2_0[] = {
268 PC_CPU_MODEL_IDS("2.0.0")
269 { "virtio-scsi-pci", "any_layout", "off" },
270 { "PIIX4_PM", "memory-hotplug-support", "off" },
271 { "apic", "version", "0x11" },
272 { "nec-usb-xhci", "superspeed-ports-first", "off" },
273 { "nec-usb-xhci", "force-pcie-endcap", "on" },
274 { "pci-serial", "prog_if", "0" },
275 { "pci-serial-2x", "prog_if", "0" },
276 { "pci-serial-4x", "prog_if", "0" },
277 { "virtio-net-pci", "guest_announce", "off" },
278 { "ICH9-LPC", "memory-hotplug-support", "off" },
279 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
280 { "ioh3420", COMPAT_PROP_PCP, "off" },
281 };
282 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
283
284 GlobalProperty pc_compat_1_7[] = {
285 PC_CPU_MODEL_IDS("1.7.0")
286 { TYPE_USB_DEVICE, "msos-desc", "no" },
287 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
288 { "hpet", HPET_INTCAP, "4" },
289 };
290 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
291
292 GlobalProperty pc_compat_1_6[] = {
293 PC_CPU_MODEL_IDS("1.6.0")
294 { "e1000", "mitigation", "off" },
295 { "qemu64-" TYPE_X86_CPU, "model", "2" },
296 { "qemu32-" TYPE_X86_CPU, "model", "3" },
297 { "i440FX-pcihost", "short_root_bus", "1" },
298 { "q35-pcihost", "short_root_bus", "1" },
299 };
300 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
301
302 GlobalProperty pc_compat_1_5[] = {
303 PC_CPU_MODEL_IDS("1.5.0")
304 { "Conroe-" TYPE_X86_CPU, "model", "2" },
305 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
306 { "Penryn-" TYPE_X86_CPU, "model", "2" },
307 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
308 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
309 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
310 { "virtio-net-pci", "any_layout", "off" },
311 { TYPE_X86_CPU, "pmu", "on" },
312 { "i440FX-pcihost", "short_root_bus", "0" },
313 { "q35-pcihost", "short_root_bus", "0" },
314 };
315 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
316
317 GlobalProperty pc_compat_1_4[] = {
318 PC_CPU_MODEL_IDS("1.4.0")
319 { "scsi-hd", "discard_granularity", "0" },
320 { "scsi-cd", "discard_granularity", "0" },
321 { "scsi-disk", "discard_granularity", "0" },
322 { "ide-hd", "discard_granularity", "0" },
323 { "ide-cd", "discard_granularity", "0" },
324 { "ide-drive", "discard_granularity", "0" },
325 { "virtio-blk-pci", "discard_granularity", "0" },
326 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
327 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
328 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
329 { "e1000", "romfile", "pxe-e1000.rom" },
330 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
331 { "pcnet", "romfile", "pxe-pcnet.rom" },
332 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
333 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
334 { "486-" TYPE_X86_CPU, "model", "0" },
335 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
336 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
337 };
338 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
339
340 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
341 {
342 GSIState *s;
343
344 s = g_new0(GSIState, 1);
345 if (kvm_ioapic_in_kernel()) {
346 kvm_pc_setup_irq_routing(pci_enabled);
347 }
348 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
349
350 return s;
351 }
352
353 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
354 unsigned size)
355 {
356 }
357
358 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
359 {
360 return 0xffffffffffffffffULL;
361 }
362
363 /* MSDOS compatibility mode FPU exception support */
364 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
365 unsigned size)
366 {
367 if (tcg_enabled()) {
368 cpu_set_ignne();
369 }
370 }
371
372 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
373 {
374 return 0xffffffffffffffffULL;
375 }
376
377 /* PC cmos mappings */
378
379 #define REG_EQUIPMENT_BYTE 0x14
380
381 int cmos_get_fd_drive_type(FloppyDriveType fd0)
382 {
383 int val;
384
385 switch (fd0) {
386 case FLOPPY_DRIVE_TYPE_144:
387 /* 1.44 Mb 3"5 drive */
388 val = 4;
389 break;
390 case FLOPPY_DRIVE_TYPE_288:
391 /* 2.88 Mb 3"5 drive */
392 val = 5;
393 break;
394 case FLOPPY_DRIVE_TYPE_120:
395 /* 1.2 Mb 5"5 drive */
396 val = 2;
397 break;
398 case FLOPPY_DRIVE_TYPE_NONE:
399 default:
400 val = 0;
401 break;
402 }
403 return val;
404 }
405
406 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
407 int16_t cylinders, int8_t heads, int8_t sectors)
408 {
409 rtc_set_memory(s, type_ofs, 47);
410 rtc_set_memory(s, info_ofs, cylinders);
411 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
412 rtc_set_memory(s, info_ofs + 2, heads);
413 rtc_set_memory(s, info_ofs + 3, 0xff);
414 rtc_set_memory(s, info_ofs + 4, 0xff);
415 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
416 rtc_set_memory(s, info_ofs + 6, cylinders);
417 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
418 rtc_set_memory(s, info_ofs + 8, sectors);
419 }
420
421 /* convert boot_device letter to something recognizable by the bios */
422 static int boot_device2nibble(char boot_device)
423 {
424 switch(boot_device) {
425 case 'a':
426 case 'b':
427 return 0x01; /* floppy boot */
428 case 'c':
429 return 0x02; /* hard drive boot */
430 case 'd':
431 return 0x03; /* CD-ROM boot */
432 case 'n':
433 return 0x04; /* Network boot */
434 }
435 return 0;
436 }
437
438 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
439 {
440 #define PC_MAX_BOOT_DEVICES 3
441 int nbds, bds[3] = { 0, };
442 int i;
443
444 nbds = strlen(boot_device);
445 if (nbds > PC_MAX_BOOT_DEVICES) {
446 error_setg(errp, "Too many boot devices for PC");
447 return;
448 }
449 for (i = 0; i < nbds; i++) {
450 bds[i] = boot_device2nibble(boot_device[i]);
451 if (bds[i] == 0) {
452 error_setg(errp, "Invalid boot device for PC: '%c'",
453 boot_device[i]);
454 return;
455 }
456 }
457 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
458 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
459 }
460
461 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
462 {
463 set_boot_dev(opaque, boot_device, errp);
464 }
465
466 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
467 {
468 int val, nb, i;
469 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
470 FLOPPY_DRIVE_TYPE_NONE };
471
472 /* floppy type */
473 if (floppy) {
474 for (i = 0; i < 2; i++) {
475 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
476 }
477 }
478 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
479 cmos_get_fd_drive_type(fd_type[1]);
480 rtc_set_memory(rtc_state, 0x10, val);
481
482 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
483 nb = 0;
484 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
485 nb++;
486 }
487 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
488 nb++;
489 }
490 switch (nb) {
491 case 0:
492 break;
493 case 1:
494 val |= 0x01; /* 1 drive, ready for boot */
495 break;
496 case 2:
497 val |= 0x41; /* 2 drives, ready for boot */
498 break;
499 }
500 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
501 }
502
503 typedef struct pc_cmos_init_late_arg {
504 ISADevice *rtc_state;
505 BusState *idebus[2];
506 } pc_cmos_init_late_arg;
507
508 typedef struct check_fdc_state {
509 ISADevice *floppy;
510 bool multiple;
511 } CheckFdcState;
512
513 static int check_fdc(Object *obj, void *opaque)
514 {
515 CheckFdcState *state = opaque;
516 Object *fdc;
517 uint32_t iobase;
518 Error *local_err = NULL;
519
520 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
521 if (!fdc) {
522 return 0;
523 }
524
525 iobase = object_property_get_uint(obj, "iobase", &local_err);
526 if (local_err || iobase != 0x3f0) {
527 error_free(local_err);
528 return 0;
529 }
530
531 if (state->floppy) {
532 state->multiple = true;
533 } else {
534 state->floppy = ISA_DEVICE(obj);
535 }
536 return 0;
537 }
538
539 static const char * const fdc_container_path[] = {
540 "/unattached", "/peripheral", "/peripheral-anon"
541 };
542
543 /*
544 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
545 * and ACPI objects.
546 */
547 ISADevice *pc_find_fdc0(void)
548 {
549 int i;
550 Object *container;
551 CheckFdcState state = { 0 };
552
553 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
554 container = container_get(qdev_get_machine(), fdc_container_path[i]);
555 object_child_foreach(container, check_fdc, &state);
556 }
557
558 if (state.multiple) {
559 warn_report("multiple floppy disk controllers with "
560 "iobase=0x3f0 have been found");
561 error_printf("the one being picked for CMOS setup might not reflect "
562 "your intent");
563 }
564
565 return state.floppy;
566 }
567
568 static void pc_cmos_init_late(void *opaque)
569 {
570 pc_cmos_init_late_arg *arg = opaque;
571 ISADevice *s = arg->rtc_state;
572 int16_t cylinders;
573 int8_t heads, sectors;
574 int val;
575 int i, trans;
576
577 val = 0;
578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
579 &cylinders, &heads, &sectors) >= 0) {
580 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
581 val |= 0xf0;
582 }
583 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
584 &cylinders, &heads, &sectors) >= 0) {
585 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
586 val |= 0x0f;
587 }
588 rtc_set_memory(s, 0x12, val);
589
590 val = 0;
591 for (i = 0; i < 4; i++) {
592 /* NOTE: ide_get_geometry() returns the physical
593 geometry. It is always such that: 1 <= sects <= 63, 1
594 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
595 geometry can be different if a translation is done. */
596 if (arg->idebus[i / 2] &&
597 ide_get_geometry(arg->idebus[i / 2], i % 2,
598 &cylinders, &heads, &sectors) >= 0) {
599 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
600 assert((trans & ~3) == 0);
601 val |= trans << (i * 2);
602 }
603 }
604 rtc_set_memory(s, 0x39, val);
605
606 pc_cmos_init_floppy(s, pc_find_fdc0());
607
608 qemu_unregister_reset(pc_cmos_init_late, opaque);
609 }
610
611 void pc_cmos_init(PCMachineState *pcms,
612 BusState *idebus0, BusState *idebus1,
613 ISADevice *s)
614 {
615 int val;
616 static pc_cmos_init_late_arg arg;
617 X86MachineState *x86ms = X86_MACHINE(pcms);
618
619 /* various important CMOS locations needed by PC/Bochs bios */
620
621 /* memory size */
622 /* base memory (first MiB) */
623 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
624 rtc_set_memory(s, 0x15, val);
625 rtc_set_memory(s, 0x16, val >> 8);
626 /* extended memory (next 64MiB) */
627 if (x86ms->below_4g_mem_size > 1 * MiB) {
628 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
629 } else {
630 val = 0;
631 }
632 if (val > 65535)
633 val = 65535;
634 rtc_set_memory(s, 0x17, val);
635 rtc_set_memory(s, 0x18, val >> 8);
636 rtc_set_memory(s, 0x30, val);
637 rtc_set_memory(s, 0x31, val >> 8);
638 /* memory between 16MiB and 4GiB */
639 if (x86ms->below_4g_mem_size > 16 * MiB) {
640 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
641 } else {
642 val = 0;
643 }
644 if (val > 65535)
645 val = 65535;
646 rtc_set_memory(s, 0x34, val);
647 rtc_set_memory(s, 0x35, val >> 8);
648 /* memory above 4GiB */
649 val = x86ms->above_4g_mem_size / 65536;
650 rtc_set_memory(s, 0x5b, val);
651 rtc_set_memory(s, 0x5c, val >> 8);
652 rtc_set_memory(s, 0x5d, val >> 16);
653
654 object_property_add_link(OBJECT(pcms), "rtc_state",
655 TYPE_ISA_DEVICE,
656 (Object **)&x86ms->rtc,
657 object_property_allow_set_link,
658 OBJ_PROP_LINK_STRONG, &error_abort);
659 object_property_set_link(OBJECT(pcms), OBJECT(s),
660 "rtc_state", &error_abort);
661
662 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
663
664 val = 0;
665 val |= 0x02; /* FPU is there */
666 val |= 0x04; /* PS/2 mouse installed */
667 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
668
669 /* hard drives and FDC */
670 arg.rtc_state = s;
671 arg.idebus[0] = idebus0;
672 arg.idebus[1] = idebus1;
673 qemu_register_reset(pc_cmos_init_late, &arg);
674 }
675
676 #define TYPE_PORT92 "port92"
677 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
678
679 /* port 92 stuff: could be split off */
680 typedef struct Port92State {
681 ISADevice parent_obj;
682
683 MemoryRegion io;
684 uint8_t outport;
685 qemu_irq a20_out;
686 } Port92State;
687
688 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
689 unsigned size)
690 {
691 Port92State *s = opaque;
692 int oldval = s->outport;
693
694 trace_port92_write(val);
695 s->outport = val;
696 qemu_set_irq(s->a20_out, (val >> 1) & 1);
697 if ((val & 1) && !(oldval & 1)) {
698 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
699 }
700 }
701
702 static uint64_t port92_read(void *opaque, hwaddr addr,
703 unsigned size)
704 {
705 Port92State *s = opaque;
706 uint32_t ret;
707
708 ret = s->outport;
709 trace_port92_read(ret);
710 return ret;
711 }
712
713 static const VMStateDescription vmstate_port92_isa = {
714 .name = "port92",
715 .version_id = 1,
716 .minimum_version_id = 1,
717 .fields = (VMStateField[]) {
718 VMSTATE_UINT8(outport, Port92State),
719 VMSTATE_END_OF_LIST()
720 }
721 };
722
723 static void port92_reset(DeviceState *d)
724 {
725 Port92State *s = PORT92(d);
726
727 s->outport &= ~1;
728 }
729
730 static const MemoryRegionOps port92_ops = {
731 .read = port92_read,
732 .write = port92_write,
733 .impl = {
734 .min_access_size = 1,
735 .max_access_size = 1,
736 },
737 .endianness = DEVICE_LITTLE_ENDIAN,
738 };
739
740 static void port92_initfn(Object *obj)
741 {
742 Port92State *s = PORT92(obj);
743
744 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
745
746 s->outport = 0;
747
748 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
749 }
750
751 static void port92_realizefn(DeviceState *dev, Error **errp)
752 {
753 ISADevice *isadev = ISA_DEVICE(dev);
754 Port92State *s = PORT92(dev);
755
756 isa_register_ioport(isadev, &s->io, 0x92);
757 }
758
759 static void port92_class_initfn(ObjectClass *klass, void *data)
760 {
761 DeviceClass *dc = DEVICE_CLASS(klass);
762
763 dc->realize = port92_realizefn;
764 dc->reset = port92_reset;
765 dc->vmsd = &vmstate_port92_isa;
766 /*
767 * Reason: unlike ordinary ISA devices, this one needs additional
768 * wiring: its A20 output line needs to be wired up with
769 * qdev_connect_gpio_out_named().
770 */
771 dc->user_creatable = false;
772 }
773
774 static const TypeInfo port92_info = {
775 .name = TYPE_PORT92,
776 .parent = TYPE_ISA_DEVICE,
777 .instance_size = sizeof(Port92State),
778 .instance_init = port92_initfn,
779 .class_init = port92_class_initfn,
780 };
781
782 static void port92_register_types(void)
783 {
784 type_register_static(&port92_info);
785 }
786
787 type_init(port92_register_types)
788
789 static void handle_a20_line_change(void *opaque, int irq, int level)
790 {
791 X86CPU *cpu = opaque;
792
793 /* XXX: send to all CPUs ? */
794 /* XXX: add logic to handle multiple A20 line sources */
795 x86_cpu_set_a20(cpu, level);
796 }
797
798 #define NE2000_NB_MAX 6
799
800 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
801 0x280, 0x380 };
802 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
803
804 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
805 {
806 static int nb_ne2k = 0;
807
808 if (nb_ne2k == NE2000_NB_MAX)
809 return;
810 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
811 ne2000_irq[nb_ne2k], nd);
812 nb_ne2k++;
813 }
814
815 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
816 {
817 X86CPU *cpu = opaque;
818
819 if (level) {
820 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
821 }
822 }
823
824 /*
825 * This function is very similar to smp_parse()
826 * in hw/core/machine.c but includes CPU die support.
827 */
828 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
829 {
830 X86MachineState *x86ms = X86_MACHINE(ms);
831
832 if (opts) {
833 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
834 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
835 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
836 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
837 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
838
839 /* compute missing values, prefer sockets over cores over threads */
840 if (cpus == 0 || sockets == 0) {
841 cores = cores > 0 ? cores : 1;
842 threads = threads > 0 ? threads : 1;
843 if (cpus == 0) {
844 sockets = sockets > 0 ? sockets : 1;
845 cpus = cores * threads * dies * sockets;
846 } else {
847 ms->smp.max_cpus =
848 qemu_opt_get_number(opts, "maxcpus", cpus);
849 sockets = ms->smp.max_cpus / (cores * threads * dies);
850 }
851 } else if (cores == 0) {
852 threads = threads > 0 ? threads : 1;
853 cores = cpus / (sockets * dies * threads);
854 cores = cores > 0 ? cores : 1;
855 } else if (threads == 0) {
856 threads = cpus / (cores * dies * sockets);
857 threads = threads > 0 ? threads : 1;
858 } else if (sockets * dies * cores * threads < cpus) {
859 error_report("cpu topology: "
860 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
861 "smp_cpus (%u)",
862 sockets, dies, cores, threads, cpus);
863 exit(1);
864 }
865
866 ms->smp.max_cpus =
867 qemu_opt_get_number(opts, "maxcpus", cpus);
868
869 if (ms->smp.max_cpus < cpus) {
870 error_report("maxcpus must be equal to or greater than smp");
871 exit(1);
872 }
873
874 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
875 error_report("cpu topology: "
876 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
877 "maxcpus (%u)",
878 sockets, dies, cores, threads,
879 ms->smp.max_cpus);
880 exit(1);
881 }
882
883 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
884 warn_report("Invalid CPU topology deprecated: "
885 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
886 "!= maxcpus (%u)",
887 sockets, dies, cores, threads,
888 ms->smp.max_cpus);
889 }
890
891 ms->smp.cpus = cpus;
892 ms->smp.cores = cores;
893 ms->smp.threads = threads;
894 x86ms->smp_dies = dies;
895 }
896
897 if (ms->smp.cpus > 1) {
898 Error *blocker = NULL;
899 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
900 replay_add_blocker(blocker);
901 }
902 }
903
904 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
905 {
906 X86MachineState *x86ms = X86_MACHINE(ms);
907 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
908 Error *local_err = NULL;
909
910 if (id < 0) {
911 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
912 return;
913 }
914
915 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
916 error_setg(errp, "Unable to add CPU: %" PRIi64
917 ", resulting APIC ID (%" PRIi64 ") is too large",
918 id, apic_id);
919 return;
920 }
921
922
923 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
924 if (local_err) {
925 error_propagate(errp, local_err);
926 return;
927 }
928 }
929
930 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
931 {
932 if (cpus_count > 0xff) {
933 /* If the number of CPUs can't be represented in 8 bits, the
934 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
935 * to make old BIOSes fail more predictably.
936 */
937 rtc_set_memory(rtc, 0x5f, 0);
938 } else {
939 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
940 }
941 }
942
943 static
944 void pc_machine_done(Notifier *notifier, void *data)
945 {
946 PCMachineState *pcms = container_of(notifier,
947 PCMachineState, machine_done);
948 X86MachineState *x86ms = X86_MACHINE(pcms);
949 PCIBus *bus = pcms->bus;
950
951 /* set the number of CPUs */
952 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
953
954 if (bus) {
955 int extra_hosts = 0;
956
957 QLIST_FOREACH(bus, &bus->child, sibling) {
958 /* look for expander root buses */
959 if (pci_bus_is_root(bus)) {
960 extra_hosts++;
961 }
962 }
963 if (extra_hosts && x86ms->fw_cfg) {
964 uint64_t *val = g_malloc(sizeof(*val));
965 *val = cpu_to_le64(extra_hosts);
966 fw_cfg_add_file(x86ms->fw_cfg,
967 "etc/extra-pci-roots", val, sizeof(*val));
968 }
969 }
970
971 acpi_setup();
972 if (x86ms->fw_cfg) {
973 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
974 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
975 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
976 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
977 }
978
979 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
980 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
981
982 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
983 iommu->intr_eim != ON_OFF_AUTO_ON) {
984 error_report("current -smp configuration requires "
985 "Extended Interrupt Mode enabled. "
986 "You can add an IOMMU using: "
987 "-device intel-iommu,intremap=on,eim=on");
988 exit(EXIT_FAILURE);
989 }
990 }
991 }
992
993 void pc_guest_info_init(PCMachineState *pcms)
994 {
995 int i;
996 MachineState *ms = MACHINE(pcms);
997 X86MachineState *x86ms = X86_MACHINE(pcms);
998
999 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
1000 pcms->numa_nodes = ms->numa_state->num_nodes;
1001 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1002 sizeof *pcms->node_mem);
1003 for (i = 0; i < ms->numa_state->num_nodes; i++) {
1004 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
1005 }
1006
1007 pcms->machine_done.notify = pc_machine_done;
1008 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1009 }
1010
1011 /* setup pci memory address space mapping into system address space */
1012 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1013 MemoryRegion *pci_address_space)
1014 {
1015 /* Set to lower priority than RAM */
1016 memory_region_add_subregion_overlap(system_memory, 0x0,
1017 pci_address_space, -1);
1018 }
1019
1020 void xen_load_linux(PCMachineState *pcms)
1021 {
1022 int i;
1023 FWCfgState *fw_cfg;
1024 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1025 X86MachineState *x86ms = X86_MACHINE(pcms);
1026
1027 assert(MACHINE(pcms)->kernel_filename != NULL);
1028
1029 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1030 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1031 rom_set_fw(fw_cfg);
1032
1033 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1034 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1035 for (i = 0; i < nb_option_roms; i++) {
1036 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1037 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1038 !strcmp(option_rom[i].name, "pvh.bin") ||
1039 !strcmp(option_rom[i].name, "multiboot.bin"));
1040 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1041 }
1042 x86ms->fw_cfg = fw_cfg;
1043 }
1044
1045 void pc_memory_init(PCMachineState *pcms,
1046 MemoryRegion *system_memory,
1047 MemoryRegion *rom_memory,
1048 MemoryRegion **ram_memory)
1049 {
1050 int linux_boot, i;
1051 MemoryRegion *ram, *option_rom_mr;
1052 MemoryRegion *ram_below_4g, *ram_above_4g;
1053 FWCfgState *fw_cfg;
1054 MachineState *machine = MACHINE(pcms);
1055 MachineClass *mc = MACHINE_GET_CLASS(machine);
1056 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1057 X86MachineState *x86ms = X86_MACHINE(pcms);
1058
1059 assert(machine->ram_size == x86ms->below_4g_mem_size +
1060 x86ms->above_4g_mem_size);
1061
1062 linux_boot = (machine->kernel_filename != NULL);
1063
1064 /* Allocate RAM. We allocate it as a single memory region and use
1065 * aliases to address portions of it, mostly for backwards compatibility
1066 * with older qemus that used qemu_ram_alloc().
1067 */
1068 ram = g_malloc(sizeof(*ram));
1069 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1070 machine->ram_size);
1071 *ram_memory = ram;
1072 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1073 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1074 0, x86ms->below_4g_mem_size);
1075 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1076 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1077 if (x86ms->above_4g_mem_size > 0) {
1078 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1079 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1080 x86ms->below_4g_mem_size,
1081 x86ms->above_4g_mem_size);
1082 memory_region_add_subregion(system_memory, 0x100000000ULL,
1083 ram_above_4g);
1084 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
1085 }
1086
1087 if (!pcmc->has_reserved_memory &&
1088 (machine->ram_slots ||
1089 (machine->maxram_size > machine->ram_size))) {
1090
1091 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1092 mc->name);
1093 exit(EXIT_FAILURE);
1094 }
1095
1096 /* always allocate the device memory information */
1097 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1098
1099 /* initialize device memory address space */
1100 if (pcmc->has_reserved_memory &&
1101 (machine->ram_size < machine->maxram_size)) {
1102 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1103
1104 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1105 error_report("unsupported amount of memory slots: %"PRIu64,
1106 machine->ram_slots);
1107 exit(EXIT_FAILURE);
1108 }
1109
1110 if (QEMU_ALIGN_UP(machine->maxram_size,
1111 TARGET_PAGE_SIZE) != machine->maxram_size) {
1112 error_report("maximum memory size must by aligned to multiple of "
1113 "%d bytes", TARGET_PAGE_SIZE);
1114 exit(EXIT_FAILURE);
1115 }
1116
1117 machine->device_memory->base =
1118 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1119
1120 if (pcmc->enforce_aligned_dimm) {
1121 /* size device region assuming 1G page max alignment per slot */
1122 device_mem_size += (1 * GiB) * machine->ram_slots;
1123 }
1124
1125 if ((machine->device_memory->base + device_mem_size) <
1126 device_mem_size) {
1127 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1128 machine->maxram_size);
1129 exit(EXIT_FAILURE);
1130 }
1131
1132 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1133 "device-memory", device_mem_size);
1134 memory_region_add_subregion(system_memory, machine->device_memory->base,
1135 &machine->device_memory->mr);
1136 }
1137
1138 /* Initialize PC system firmware */
1139 pc_system_firmware_init(pcms, rom_memory);
1140
1141 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1142 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1143 &error_fatal);
1144 if (pcmc->pci_enabled) {
1145 memory_region_set_readonly(option_rom_mr, true);
1146 }
1147 memory_region_add_subregion_overlap(rom_memory,
1148 PC_ROM_MIN_VGA,
1149 option_rom_mr,
1150 1);
1151
1152 fw_cfg = fw_cfg_arch_create(machine,
1153 x86ms->boot_cpus, x86ms->apic_id_limit);
1154
1155 rom_set_fw(fw_cfg);
1156
1157 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1158 uint64_t *val = g_malloc(sizeof(*val));
1159 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1160 uint64_t res_mem_end = machine->device_memory->base;
1161
1162 if (!pcmc->broken_reserved_end) {
1163 res_mem_end += memory_region_size(&machine->device_memory->mr);
1164 }
1165 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1166 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1167 }
1168
1169 if (linux_boot) {
1170 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1171 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1172 }
1173
1174 for (i = 0; i < nb_option_roms; i++) {
1175 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1176 }
1177 x86ms->fw_cfg = fw_cfg;
1178
1179 /* Init default IOAPIC address space */
1180 x86ms->ioapic_as = &address_space_memory;
1181
1182 /* Init ACPI memory hotplug IO base address */
1183 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1184 }
1185
1186 /*
1187 * The 64bit pci hole starts after "above 4G RAM" and
1188 * potentially the space reserved for memory hotplug.
1189 */
1190 uint64_t pc_pci_hole64_start(void)
1191 {
1192 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1193 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1194 MachineState *ms = MACHINE(pcms);
1195 X86MachineState *x86ms = X86_MACHINE(pcms);
1196 uint64_t hole64_start = 0;
1197
1198 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1199 hole64_start = ms->device_memory->base;
1200 if (!pcmc->broken_reserved_end) {
1201 hole64_start += memory_region_size(&ms->device_memory->mr);
1202 }
1203 } else {
1204 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1205 }
1206
1207 return ROUND_UP(hole64_start, 1 * GiB);
1208 }
1209
1210 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1211 {
1212 DeviceState *dev = NULL;
1213
1214 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1215 if (pci_bus) {
1216 PCIDevice *pcidev = pci_vga_init(pci_bus);
1217 dev = pcidev ? &pcidev->qdev : NULL;
1218 } else if (isa_bus) {
1219 ISADevice *isadev = isa_vga_init(isa_bus);
1220 dev = isadev ? DEVICE(isadev) : NULL;
1221 }
1222 rom_reset_order_override();
1223 return dev;
1224 }
1225
1226 static const MemoryRegionOps ioport80_io_ops = {
1227 .write = ioport80_write,
1228 .read = ioport80_read,
1229 .endianness = DEVICE_NATIVE_ENDIAN,
1230 .impl = {
1231 .min_access_size = 1,
1232 .max_access_size = 1,
1233 },
1234 };
1235
1236 static const MemoryRegionOps ioportF0_io_ops = {
1237 .write = ioportF0_write,
1238 .read = ioportF0_read,
1239 .endianness = DEVICE_NATIVE_ENDIAN,
1240 .impl = {
1241 .min_access_size = 1,
1242 .max_access_size = 1,
1243 },
1244 };
1245
1246 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1247 {
1248 int i;
1249 DriveInfo *fd[MAX_FD];
1250 qemu_irq *a20_line;
1251 ISADevice *i8042, *port92, *vmmouse;
1252
1253 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1254 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1255
1256 for (i = 0; i < MAX_FD; i++) {
1257 fd[i] = drive_get(IF_FLOPPY, 0, i);
1258 create_fdctrl |= !!fd[i];
1259 }
1260 if (create_fdctrl) {
1261 fdctrl_init_isa(isa_bus, fd);
1262 }
1263
1264 i8042 = isa_create_simple(isa_bus, "i8042");
1265 if (!no_vmport) {
1266 vmport_init(isa_bus);
1267 vmmouse = isa_try_create(isa_bus, "vmmouse");
1268 } else {
1269 vmmouse = NULL;
1270 }
1271 if (vmmouse) {
1272 DeviceState *dev = DEVICE(vmmouse);
1273 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1274 qdev_init_nofail(dev);
1275 }
1276 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1277
1278 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1279 i8042_setup_a20_line(i8042, a20_line[0]);
1280 qdev_connect_gpio_out_named(DEVICE(port92),
1281 PORT92_A20_LINE, 0, a20_line[1]);
1282 g_free(a20_line);
1283 }
1284
1285 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1286 ISADevice **rtc_state,
1287 bool create_fdctrl,
1288 bool no_vmport,
1289 bool has_pit,
1290 uint32_t hpet_irqs)
1291 {
1292 int i;
1293 DeviceState *hpet = NULL;
1294 int pit_isa_irq = 0;
1295 qemu_irq pit_alt_irq = NULL;
1296 qemu_irq rtc_irq = NULL;
1297 ISADevice *pit = NULL;
1298 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1299 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1300
1301 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1302 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1303
1304 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1305 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1306
1307 /*
1308 * Check if an HPET shall be created.
1309 *
1310 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1311 * when the HPET wants to take over. Thus we have to disable the latter.
1312 */
1313 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1314 /* In order to set property, here not using sysbus_try_create_simple */
1315 hpet = qdev_try_create(NULL, TYPE_HPET);
1316 if (hpet) {
1317 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1318 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1319 * IRQ8 and IRQ2.
1320 */
1321 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1322 HPET_INTCAP, NULL);
1323 if (!compat) {
1324 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1325 }
1326 qdev_init_nofail(hpet);
1327 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1328
1329 for (i = 0; i < GSI_NUM_PINS; i++) {
1330 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1331 }
1332 pit_isa_irq = -1;
1333 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1334 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1335 }
1336 }
1337 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1338
1339 qemu_register_boot_set(pc_boot_set, *rtc_state);
1340
1341 if (!xen_enabled() && has_pit) {
1342 if (kvm_pit_in_kernel()) {
1343 pit = kvm_pit_init(isa_bus, 0x40);
1344 } else {
1345 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1346 }
1347 if (hpet) {
1348 /* connect PIT to output control line of the HPET */
1349 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1350 }
1351 pcspk_init(isa_bus, pit);
1352 }
1353
1354 i8257_dma_init(isa_bus, 0);
1355
1356 /* Super I/O */
1357 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1358 }
1359
1360 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1361 {
1362 int i;
1363
1364 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1365 for (i = 0; i < nb_nics; i++) {
1366 NICInfo *nd = &nd_table[i];
1367 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1368
1369 if (g_str_equal(model, "ne2k_isa")) {
1370 pc_init_ne2k_isa(isa_bus, nd);
1371 } else {
1372 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1373 }
1374 }
1375 rom_reset_order_override();
1376 }
1377
1378 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1379 {
1380 qemu_irq *i8259;
1381
1382 if (kvm_pic_in_kernel()) {
1383 i8259 = kvm_i8259_init(isa_bus);
1384 } else if (xen_enabled()) {
1385 i8259 = xen_interrupt_controller_init();
1386 } else {
1387 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1388 }
1389
1390 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1391 i8259_irqs[i] = i8259[i];
1392 }
1393
1394 g_free(i8259);
1395 }
1396
1397 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1398 Error **errp)
1399 {
1400 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1401 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1402 const MachineState *ms = MACHINE(hotplug_dev);
1403 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1404 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1405 Error *local_err = NULL;
1406
1407 /*
1408 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1409 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1410 * addition to cover this case.
1411 */
1412 if (!pcms->acpi_dev || !acpi_enabled) {
1413 error_setg(errp,
1414 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1415 return;
1416 }
1417
1418 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1419 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1420 return;
1421 }
1422
1423 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1424 if (local_err) {
1425 error_propagate(errp, local_err);
1426 return;
1427 }
1428
1429 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1430 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1431 }
1432
1433 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1434 DeviceState *dev, Error **errp)
1435 {
1436 Error *local_err = NULL;
1437 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1438 MachineState *ms = MACHINE(hotplug_dev);
1439 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1440
1441 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1442 if (local_err) {
1443 goto out;
1444 }
1445
1446 if (is_nvdimm) {
1447 nvdimm_plug(ms->nvdimms_state);
1448 }
1449
1450 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1451 out:
1452 error_propagate(errp, local_err);
1453 }
1454
1455 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1456 DeviceState *dev, Error **errp)
1457 {
1458 Error *local_err = NULL;
1459 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1460
1461 /*
1462 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1463 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1464 * addition to cover this case.
1465 */
1466 if (!pcms->acpi_dev || !acpi_enabled) {
1467 error_setg(&local_err,
1468 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1469 goto out;
1470 }
1471
1472 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1473 error_setg(&local_err,
1474 "nvdimm device hot unplug is not supported yet.");
1475 goto out;
1476 }
1477
1478 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1479 &local_err);
1480 out:
1481 error_propagate(errp, local_err);
1482 }
1483
1484 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1485 DeviceState *dev, Error **errp)
1486 {
1487 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1488 Error *local_err = NULL;
1489
1490 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1491 if (local_err) {
1492 goto out;
1493 }
1494
1495 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1496 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1497 out:
1498 error_propagate(errp, local_err);
1499 }
1500
1501 static int pc_apic_cmp(const void *a, const void *b)
1502 {
1503 CPUArchId *apic_a = (CPUArchId *)a;
1504 CPUArchId *apic_b = (CPUArchId *)b;
1505
1506 return apic_a->arch_id - apic_b->arch_id;
1507 }
1508
1509 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1510 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1511 * entry corresponding to CPU's apic_id returns NULL.
1512 */
1513 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1514 {
1515 CPUArchId apic_id, *found_cpu;
1516
1517 apic_id.arch_id = id;
1518 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1519 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1520 pc_apic_cmp);
1521 if (found_cpu && idx) {
1522 *idx = found_cpu - ms->possible_cpus->cpus;
1523 }
1524 return found_cpu;
1525 }
1526
1527 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1528 DeviceState *dev, Error **errp)
1529 {
1530 CPUArchId *found_cpu;
1531 Error *local_err = NULL;
1532 X86CPU *cpu = X86_CPU(dev);
1533 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1534 X86MachineState *x86ms = X86_MACHINE(pcms);
1535
1536 if (pcms->acpi_dev) {
1537 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1538 if (local_err) {
1539 goto out;
1540 }
1541 }
1542
1543 /* increment the number of CPUs */
1544 x86ms->boot_cpus++;
1545 if (x86ms->rtc) {
1546 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1547 }
1548 if (x86ms->fw_cfg) {
1549 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1550 }
1551
1552 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1553 found_cpu->cpu = OBJECT(dev);
1554 out:
1555 error_propagate(errp, local_err);
1556 }
1557 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1558 DeviceState *dev, Error **errp)
1559 {
1560 int idx = -1;
1561 Error *local_err = NULL;
1562 X86CPU *cpu = X86_CPU(dev);
1563 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1564
1565 if (!pcms->acpi_dev) {
1566 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1567 goto out;
1568 }
1569
1570 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1571 assert(idx != -1);
1572 if (idx == 0) {
1573 error_setg(&local_err, "Boot CPU is unpluggable");
1574 goto out;
1575 }
1576
1577 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1578 &local_err);
1579 if (local_err) {
1580 goto out;
1581 }
1582
1583 out:
1584 error_propagate(errp, local_err);
1585
1586 }
1587
1588 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1589 DeviceState *dev, Error **errp)
1590 {
1591 CPUArchId *found_cpu;
1592 Error *local_err = NULL;
1593 X86CPU *cpu = X86_CPU(dev);
1594 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1595 X86MachineState *x86ms = X86_MACHINE(pcms);
1596
1597 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1598 if (local_err) {
1599 goto out;
1600 }
1601
1602 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1603 found_cpu->cpu = NULL;
1604 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1605
1606 /* decrement the number of CPUs */
1607 x86ms->boot_cpus--;
1608 /* Update the number of CPUs in CMOS */
1609 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1610 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1611 out:
1612 error_propagate(errp, local_err);
1613 }
1614
1615 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1616 DeviceState *dev, Error **errp)
1617 {
1618 int idx;
1619 CPUState *cs;
1620 CPUArchId *cpu_slot;
1621 X86CPUTopoInfo topo;
1622 X86CPU *cpu = X86_CPU(dev);
1623 CPUX86State *env = &cpu->env;
1624 MachineState *ms = MACHINE(hotplug_dev);
1625 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1626 X86MachineState *x86ms = X86_MACHINE(pcms);
1627 unsigned int smp_cores = ms->smp.cores;
1628 unsigned int smp_threads = ms->smp.threads;
1629
1630 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1631 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1632 ms->cpu_type);
1633 return;
1634 }
1635
1636 env->nr_dies = x86ms->smp_dies;
1637
1638 /*
1639 * If APIC ID is not set,
1640 * set it based on socket/die/core/thread properties.
1641 */
1642 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1643 int max_socket = (ms->smp.max_cpus - 1) /
1644 smp_threads / smp_cores / x86ms->smp_dies;
1645
1646 /*
1647 * die-id was optional in QEMU 4.0 and older, so keep it optional
1648 * if there's only one die per socket.
1649 */
1650 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1651 cpu->die_id = 0;
1652 }
1653
1654 if (cpu->socket_id < 0) {
1655 error_setg(errp, "CPU socket-id is not set");
1656 return;
1657 } else if (cpu->socket_id > max_socket) {
1658 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1659 cpu->socket_id, max_socket);
1660 return;
1661 }
1662 if (cpu->die_id < 0) {
1663 error_setg(errp, "CPU die-id is not set");
1664 return;
1665 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1666 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1667 cpu->die_id, x86ms->smp_dies - 1);
1668 return;
1669 }
1670 if (cpu->core_id < 0) {
1671 error_setg(errp, "CPU core-id is not set");
1672 return;
1673 } else if (cpu->core_id > (smp_cores - 1)) {
1674 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1675 cpu->core_id, smp_cores - 1);
1676 return;
1677 }
1678 if (cpu->thread_id < 0) {
1679 error_setg(errp, "CPU thread-id is not set");
1680 return;
1681 } else if (cpu->thread_id > (smp_threads - 1)) {
1682 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1683 cpu->thread_id, smp_threads - 1);
1684 return;
1685 }
1686
1687 topo.pkg_id = cpu->socket_id;
1688 topo.die_id = cpu->die_id;
1689 topo.core_id = cpu->core_id;
1690 topo.smt_id = cpu->thread_id;
1691 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1692 smp_threads, &topo);
1693 }
1694
1695 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1696 if (!cpu_slot) {
1697 MachineState *ms = MACHINE(pcms);
1698
1699 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1700 smp_cores, smp_threads, &topo);
1701 error_setg(errp,
1702 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1703 " APIC ID %" PRIu32 ", valid index range 0:%d",
1704 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1705 cpu->apic_id, ms->possible_cpus->len - 1);
1706 return;
1707 }
1708
1709 if (cpu_slot->cpu) {
1710 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1711 idx, cpu->apic_id);
1712 return;
1713 }
1714
1715 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1716 * so that machine_query_hotpluggable_cpus would show correct values
1717 */
1718 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1719 * once -smp refactoring is complete and there will be CPU private
1720 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1721 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1722 smp_cores, smp_threads, &topo);
1723 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1724 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1725 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1726 return;
1727 }
1728 cpu->socket_id = topo.pkg_id;
1729
1730 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1731 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1732 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1733 return;
1734 }
1735 cpu->die_id = topo.die_id;
1736
1737 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1738 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1739 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1740 return;
1741 }
1742 cpu->core_id = topo.core_id;
1743
1744 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1745 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1746 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1747 return;
1748 }
1749 cpu->thread_id = topo.smt_id;
1750
1751 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1752 !kvm_hv_vpindex_settable()) {
1753 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1754 return;
1755 }
1756
1757 cs = CPU(cpu);
1758 cs->cpu_index = idx;
1759
1760 numa_cpu_pre_plug(cpu_slot, dev, errp);
1761 }
1762
1763 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1764 DeviceState *dev, Error **errp)
1765 {
1766 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1767 Error *local_err = NULL;
1768
1769 if (!hotplug_dev2) {
1770 /*
1771 * Without a bus hotplug handler, we cannot control the plug/unplug
1772 * order. This should never be the case on x86, however better add
1773 * a safety net.
1774 */
1775 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1776 return;
1777 }
1778 /*
1779 * First, see if we can plug this memory device at all. If that
1780 * succeeds, branch of to the actual hotplug handler.
1781 */
1782 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1783 &local_err);
1784 if (!local_err) {
1785 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1786 }
1787 error_propagate(errp, local_err);
1788 }
1789
1790 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1791 DeviceState *dev, Error **errp)
1792 {
1793 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1794 Error *local_err = NULL;
1795
1796 /*
1797 * Plug the memory device first and then branch off to the actual
1798 * hotplug handler. If that one fails, we can easily undo the memory
1799 * device bits.
1800 */
1801 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1802 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1803 if (local_err) {
1804 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1805 }
1806 error_propagate(errp, local_err);
1807 }
1808
1809 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1810 DeviceState *dev, Error **errp)
1811 {
1812 /* We don't support virtio pmem hot unplug */
1813 error_setg(errp, "virtio pmem device unplug not supported.");
1814 }
1815
1816 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1817 DeviceState *dev, Error **errp)
1818 {
1819 /* We don't support virtio pmem hot unplug */
1820 }
1821
1822 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1823 DeviceState *dev, Error **errp)
1824 {
1825 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1826 pc_memory_pre_plug(hotplug_dev, dev, errp);
1827 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1828 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1829 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1830 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1831 }
1832 }
1833
1834 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1835 DeviceState *dev, Error **errp)
1836 {
1837 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1838 pc_memory_plug(hotplug_dev, dev, errp);
1839 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1840 pc_cpu_plug(hotplug_dev, dev, errp);
1841 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1842 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1843 }
1844 }
1845
1846 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1847 DeviceState *dev, Error **errp)
1848 {
1849 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1850 pc_memory_unplug_request(hotplug_dev, dev, errp);
1851 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1852 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1853 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1854 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1855 } else {
1856 error_setg(errp, "acpi: device unplug request for not supported device"
1857 " type: %s", object_get_typename(OBJECT(dev)));
1858 }
1859 }
1860
1861 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1862 DeviceState *dev, Error **errp)
1863 {
1864 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1865 pc_memory_unplug(hotplug_dev, dev, errp);
1866 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1867 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1868 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1869 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1870 } else {
1871 error_setg(errp, "acpi: device unplug for not supported device"
1872 " type: %s", object_get_typename(OBJECT(dev)));
1873 }
1874 }
1875
1876 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1877 DeviceState *dev)
1878 {
1879 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1880 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1881 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1882 return HOTPLUG_HANDLER(machine);
1883 }
1884
1885 return NULL;
1886 }
1887
1888 static void
1889 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1890 const char *name, void *opaque,
1891 Error **errp)
1892 {
1893 MachineState *ms = MACHINE(obj);
1894 int64_t value = 0;
1895
1896 if (ms->device_memory) {
1897 value = memory_region_size(&ms->device_memory->mr);
1898 }
1899
1900 visit_type_int(v, name, &value, errp);
1901 }
1902
1903 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1904 void *opaque, Error **errp)
1905 {
1906 PCMachineState *pcms = PC_MACHINE(obj);
1907 OnOffAuto vmport = pcms->vmport;
1908
1909 visit_type_OnOffAuto(v, name, &vmport, errp);
1910 }
1911
1912 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1913 void *opaque, Error **errp)
1914 {
1915 PCMachineState *pcms = PC_MACHINE(obj);
1916
1917 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1918 }
1919
1920 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1921 {
1922 PCMachineState *pcms = PC_MACHINE(obj);
1923
1924 return pcms->smbus_enabled;
1925 }
1926
1927 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1928 {
1929 PCMachineState *pcms = PC_MACHINE(obj);
1930
1931 pcms->smbus_enabled = value;
1932 }
1933
1934 static bool pc_machine_get_sata(Object *obj, Error **errp)
1935 {
1936 PCMachineState *pcms = PC_MACHINE(obj);
1937
1938 return pcms->sata_enabled;
1939 }
1940
1941 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1942 {
1943 PCMachineState *pcms = PC_MACHINE(obj);
1944
1945 pcms->sata_enabled = value;
1946 }
1947
1948 static bool pc_machine_get_pit(Object *obj, Error **errp)
1949 {
1950 PCMachineState *pcms = PC_MACHINE(obj);
1951
1952 return pcms->pit_enabled;
1953 }
1954
1955 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1956 {
1957 PCMachineState *pcms = PC_MACHINE(obj);
1958
1959 pcms->pit_enabled = value;
1960 }
1961
1962 static void pc_machine_initfn(Object *obj)
1963 {
1964 PCMachineState *pcms = PC_MACHINE(obj);
1965
1966 #ifdef CONFIG_VMPORT
1967 pcms->vmport = ON_OFF_AUTO_AUTO;
1968 #else
1969 pcms->vmport = ON_OFF_AUTO_OFF;
1970 #endif /* CONFIG_VMPORT */
1971 /* acpi build is enabled by default if machine supports it */
1972 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1973 pcms->smbus_enabled = true;
1974 pcms->sata_enabled = true;
1975 pcms->pit_enabled = true;
1976
1977 pc_system_flash_create(pcms);
1978 }
1979
1980 static void pc_machine_reset(MachineState *machine)
1981 {
1982 CPUState *cs;
1983 X86CPU *cpu;
1984
1985 qemu_devices_reset();
1986
1987 /* Reset APIC after devices have been reset to cancel
1988 * any changes that qemu_devices_reset() might have done.
1989 */
1990 CPU_FOREACH(cs) {
1991 cpu = X86_CPU(cs);
1992
1993 if (cpu->apic_state) {
1994 device_reset(cpu->apic_state);
1995 }
1996 }
1997 }
1998
1999 static void pc_machine_wakeup(MachineState *machine)
2000 {
2001 cpu_synchronize_all_states();
2002 pc_machine_reset(machine);
2003 cpu_synchronize_all_post_reset();
2004 }
2005
2006 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
2007 {
2008 X86IOMMUState *iommu = x86_iommu_get_default();
2009 IntelIOMMUState *intel_iommu;
2010
2011 if (iommu &&
2012 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
2013 object_dynamic_cast((Object *)dev, "vfio-pci")) {
2014 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2015 if (!intel_iommu->caching_mode) {
2016 error_setg(errp, "Device assignment is not allowed without "
2017 "enabling caching-mode=on for Intel IOMMU.");
2018 return false;
2019 }
2020 }
2021
2022 return true;
2023 }
2024
2025 static void pc_machine_class_init(ObjectClass *oc, void *data)
2026 {
2027 MachineClass *mc = MACHINE_CLASS(oc);
2028 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2029 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2030
2031 pcmc->pci_enabled = true;
2032 pcmc->has_acpi_build = true;
2033 pcmc->rsdp_in_ram = true;
2034 pcmc->smbios_defaults = true;
2035 pcmc->smbios_uuid_encoded = true;
2036 pcmc->gigabyte_align = true;
2037 pcmc->has_reserved_memory = true;
2038 pcmc->kvmclock_enabled = true;
2039 pcmc->enforce_aligned_dimm = true;
2040 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2041 * to be used at the moment, 32K should be enough for a while. */
2042 pcmc->acpi_data_size = 0x20000 + 0x8000;
2043 pcmc->linuxboot_dma_enabled = true;
2044 pcmc->pvh_enabled = true;
2045 assert(!mc->get_hotplug_handler);
2046 mc->get_hotplug_handler = pc_get_hotplug_handler;
2047 mc->hotplug_allowed = pc_hotplug_allowed;
2048 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
2049 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
2050 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
2051 mc->auto_enable_numa_with_memhp = true;
2052 mc->has_hotpluggable_cpus = true;
2053 mc->default_boot_order = "cad";
2054 mc->hot_add_cpu = pc_hot_add_cpu;
2055 mc->smp_parse = pc_smp_parse;
2056 mc->block_default_type = IF_IDE;
2057 mc->max_cpus = 255;
2058 mc->reset = pc_machine_reset;
2059 mc->wakeup = pc_machine_wakeup;
2060 hc->pre_plug = pc_machine_device_pre_plug_cb;
2061 hc->plug = pc_machine_device_plug_cb;
2062 hc->unplug_request = pc_machine_device_unplug_request_cb;
2063 hc->unplug = pc_machine_device_unplug_cb;
2064 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2065 mc->nvdimm_supported = true;
2066 mc->numa_mem_supported = true;
2067
2068 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2069 pc_machine_get_device_memory_region_size, NULL,
2070 NULL, NULL, &error_abort);
2071
2072 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2073 pc_machine_get_vmport, pc_machine_set_vmport,
2074 NULL, NULL, &error_abort);
2075 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2076 "Enable vmport (pc & q35)", &error_abort);
2077
2078 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2079 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2080
2081 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2082 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2083
2084 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2085 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2086 }
2087
2088 static const TypeInfo pc_machine_info = {
2089 .name = TYPE_PC_MACHINE,
2090 .parent = TYPE_X86_MACHINE,
2091 .abstract = true,
2092 .instance_size = sizeof(PCMachineState),
2093 .instance_init = pc_machine_initfn,
2094 .class_size = sizeof(PCMachineClass),
2095 .class_init = pc_machine_class_init,
2096 .interfaces = (InterfaceInfo[]) {
2097 { TYPE_HOTPLUG_HANDLER },
2098 { }
2099 },
2100 };
2101
2102 static void pc_machine_register_types(void)
2103 {
2104 type_register_static(&pc_machine_info);
2105 }
2106
2107 type_init(pc_machine_register_types)
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