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Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "qemu/bitmap.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
71 #include "qemu/option.h"
72 #include "qemu/cutils.h"
73 #include "hw/acpi/acpi.h"
74 #include "hw/acpi/cpu_hotplug.h"
75 #include "acpi-build.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/cxl/cxl.h"
79 #include "hw/cxl/cxl_host.h"
80 #include "qapi/error.h"
81 #include "qapi/qapi-visit-common.h"
82 #include "qapi/qapi-visit-machine.h"
83 #include "qapi/visitor.h"
84 #include "hw/core/cpu.h"
85 #include "hw/usb.h"
86 #include "hw/i386/intel_iommu.h"
87 #include "hw/net/ne2000-isa.h"
88 #include "standard-headers/asm-x86/bootparam.h"
89 #include "hw/virtio/virtio-iommu.h"
90 #include "hw/virtio/virtio-pmem-pci.h"
91 #include "hw/virtio/virtio-mem-pci.h"
92 #include "hw/mem/memory-device.h"
93 #include "sysemu/replay.h"
94 #include "target/i386/cpu.h"
95 #include "qapi/qmp/qerror.h"
96 #include "e820_memory_layout.h"
97 #include "fw_cfg.h"
98 #include "trace.h"
99 #include CONFIG_DEVICES
100
101 /*
102 * Helper for setting model-id for CPU models that changed model-id
103 * depending on QEMU versions up to QEMU 2.4.
104 */
105 #define PC_CPU_MODEL_IDS(v) \
106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
109
110 GlobalProperty pc_compat_7_2[] = {
111 { "ICH9-LPC", "noreboot", "true" },
112 };
113 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
114
115 GlobalProperty pc_compat_7_1[] = {};
116 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
117
118 GlobalProperty pc_compat_7_0[] = {};
119 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
120
121 GlobalProperty pc_compat_6_2[] = {
122 { "virtio-mem", "unplugged-inaccessible", "off" },
123 };
124 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
125
126 GlobalProperty pc_compat_6_1[] = {
127 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
128 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
129 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
130 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
131 };
132 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
133
134 GlobalProperty pc_compat_6_0[] = {
135 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
136 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
137 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
138 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
139 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
140 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
141 };
142 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
143
144 GlobalProperty pc_compat_5_2[] = {
145 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
146 };
147 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
148
149 GlobalProperty pc_compat_5_1[] = {
150 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
151 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
152 };
153 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
154
155 GlobalProperty pc_compat_5_0[] = {
156 };
157 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
158
159 GlobalProperty pc_compat_4_2[] = {
160 { "mch", "smbase-smram", "off" },
161 };
162 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
163
164 GlobalProperty pc_compat_4_1[] = {};
165 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
166
167 GlobalProperty pc_compat_4_0[] = {};
168 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
169
170 GlobalProperty pc_compat_3_1[] = {
171 { "intel-iommu", "dma-drain", "off" },
172 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
173 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
174 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
175 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
176 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
177 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
178 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
179 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
180 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
182 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
183 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
184 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
185 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
186 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
187 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
188 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
189 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
190 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
191 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
192 };
193 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
194
195 GlobalProperty pc_compat_3_0[] = {
196 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
197 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
198 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
199 };
200 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
201
202 GlobalProperty pc_compat_2_12[] = {
203 { TYPE_X86_CPU, "legacy-cache", "on" },
204 { TYPE_X86_CPU, "topoext", "off" },
205 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
206 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
207 };
208 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
209
210 GlobalProperty pc_compat_2_11[] = {
211 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
212 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
213 };
214 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
215
216 GlobalProperty pc_compat_2_10[] = {
217 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
218 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
219 { "q35-pcihost", "x-pci-hole64-fix", "off" },
220 };
221 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
222
223 GlobalProperty pc_compat_2_9[] = {
224 { "mch", "extended-tseg-mbytes", "0" },
225 };
226 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
227
228 GlobalProperty pc_compat_2_8[] = {
229 { TYPE_X86_CPU, "tcg-cpuid", "off" },
230 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
231 { "ICH9-LPC", "x-smi-broadcast", "off" },
232 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
233 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
234 };
235 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
236
237 GlobalProperty pc_compat_2_7[] = {
238 { TYPE_X86_CPU, "l3-cache", "off" },
239 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
240 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
241 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
242 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
243 { "isa-pcspk", "migrate", "off" },
244 };
245 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
246
247 GlobalProperty pc_compat_2_6[] = {
248 { TYPE_X86_CPU, "cpuid-0xb", "off" },
249 { "vmxnet3", "romfile", "" },
250 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
251 { "apic-common", "legacy-instance-id", "on", }
252 };
253 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
254
255 GlobalProperty pc_compat_2_5[] = {};
256 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
257
258 GlobalProperty pc_compat_2_4[] = {
259 PC_CPU_MODEL_IDS("2.4.0")
260 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
261 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
262 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
263 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
264 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
265 { TYPE_X86_CPU, "check", "off" },
266 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
267 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
268 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
269 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
270 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
271 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
272 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
273 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
274 };
275 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
276
277 GlobalProperty pc_compat_2_3[] = {
278 PC_CPU_MODEL_IDS("2.3.0")
279 { TYPE_X86_CPU, "arat", "off" },
280 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
281 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
282 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
283 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
284 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
285 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
286 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
287 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
291 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
292 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
293 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
294 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
295 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
296 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
297 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
298 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
299 };
300 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
301
302 GlobalProperty pc_compat_2_2[] = {
303 PC_CPU_MODEL_IDS("2.2.0")
304 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
305 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
306 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
307 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
308 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
309 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
310 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
311 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
312 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
313 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
314 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
315 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
316 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
317 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
318 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
319 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
320 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
321 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
322 };
323 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
324
325 GlobalProperty pc_compat_2_1[] = {
326 PC_CPU_MODEL_IDS("2.1.0")
327 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
328 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
329 };
330 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
331
332 GlobalProperty pc_compat_2_0[] = {
333 PC_CPU_MODEL_IDS("2.0.0")
334 { "virtio-scsi-pci", "any_layout", "off" },
335 { "PIIX4_PM", "memory-hotplug-support", "off" },
336 { "apic", "version", "0x11" },
337 { "nec-usb-xhci", "superspeed-ports-first", "off" },
338 { "nec-usb-xhci", "force-pcie-endcap", "on" },
339 { "pci-serial", "prog_if", "0" },
340 { "pci-serial-2x", "prog_if", "0" },
341 { "pci-serial-4x", "prog_if", "0" },
342 { "virtio-net-pci", "guest_announce", "off" },
343 { "ICH9-LPC", "memory-hotplug-support", "off" },
344 };
345 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
346
347 GlobalProperty pc_compat_1_7[] = {
348 PC_CPU_MODEL_IDS("1.7.0")
349 { TYPE_USB_DEVICE, "msos-desc", "no" },
350 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
351 { "hpet", HPET_INTCAP, "4" },
352 };
353 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
354
355 GlobalProperty pc_compat_1_6[] = {
356 PC_CPU_MODEL_IDS("1.6.0")
357 { "e1000", "mitigation", "off" },
358 { "qemu64-" TYPE_X86_CPU, "model", "2" },
359 { "qemu32-" TYPE_X86_CPU, "model", "3" },
360 { "i440FX-pcihost", "short_root_bus", "1" },
361 { "q35-pcihost", "short_root_bus", "1" },
362 };
363 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
364
365 GlobalProperty pc_compat_1_5[] = {
366 PC_CPU_MODEL_IDS("1.5.0")
367 { "Conroe-" TYPE_X86_CPU, "model", "2" },
368 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
369 { "Penryn-" TYPE_X86_CPU, "model", "2" },
370 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
371 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
372 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
373 { "virtio-net-pci", "any_layout", "off" },
374 { TYPE_X86_CPU, "pmu", "on" },
375 { "i440FX-pcihost", "short_root_bus", "0" },
376 { "q35-pcihost", "short_root_bus", "0" },
377 };
378 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
379
380 GlobalProperty pc_compat_1_4[] = {
381 PC_CPU_MODEL_IDS("1.4.0")
382 { "scsi-hd", "discard_granularity", "0" },
383 { "scsi-cd", "discard_granularity", "0" },
384 { "ide-hd", "discard_granularity", "0" },
385 { "ide-cd", "discard_granularity", "0" },
386 { "virtio-blk-pci", "discard_granularity", "0" },
387 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
388 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
389 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
390 { "e1000", "romfile", "pxe-e1000.rom" },
391 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
392 { "pcnet", "romfile", "pxe-pcnet.rom" },
393 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
394 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
395 { "486-" TYPE_X86_CPU, "model", "0" },
396 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
397 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
398 };
399 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
400
401 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
402 {
403 GSIState *s;
404
405 s = g_new0(GSIState, 1);
406 if (kvm_ioapic_in_kernel()) {
407 kvm_pc_setup_irq_routing(pci_enabled);
408 }
409 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
410
411 return s;
412 }
413
414 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
415 unsigned size)
416 {
417 }
418
419 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
420 {
421 return 0xffffffffffffffffULL;
422 }
423
424 /* MSDOS compatibility mode FPU exception support */
425 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
426 unsigned size)
427 {
428 if (tcg_enabled()) {
429 cpu_set_ignne();
430 }
431 }
432
433 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
434 {
435 return 0xffffffffffffffffULL;
436 }
437
438 /* PC cmos mappings */
439
440 #define REG_EQUIPMENT_BYTE 0x14
441
442 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
443 int16_t cylinders, int8_t heads, int8_t sectors)
444 {
445 rtc_set_memory(s, type_ofs, 47);
446 rtc_set_memory(s, info_ofs, cylinders);
447 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
448 rtc_set_memory(s, info_ofs + 2, heads);
449 rtc_set_memory(s, info_ofs + 3, 0xff);
450 rtc_set_memory(s, info_ofs + 4, 0xff);
451 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
452 rtc_set_memory(s, info_ofs + 6, cylinders);
453 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
454 rtc_set_memory(s, info_ofs + 8, sectors);
455 }
456
457 /* convert boot_device letter to something recognizable by the bios */
458 static int boot_device2nibble(char boot_device)
459 {
460 switch(boot_device) {
461 case 'a':
462 case 'b':
463 return 0x01; /* floppy boot */
464 case 'c':
465 return 0x02; /* hard drive boot */
466 case 'd':
467 return 0x03; /* CD-ROM boot */
468 case 'n':
469 return 0x04; /* Network boot */
470 }
471 return 0;
472 }
473
474 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
475 {
476 #define PC_MAX_BOOT_DEVICES 3
477 int nbds, bds[3] = { 0, };
478 int i;
479
480 nbds = strlen(boot_device);
481 if (nbds > PC_MAX_BOOT_DEVICES) {
482 error_setg(errp, "Too many boot devices for PC");
483 return;
484 }
485 for (i = 0; i < nbds; i++) {
486 bds[i] = boot_device2nibble(boot_device[i]);
487 if (bds[i] == 0) {
488 error_setg(errp, "Invalid boot device for PC: '%c'",
489 boot_device[i]);
490 return;
491 }
492 }
493 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
494 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
495 }
496
497 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
498 {
499 set_boot_dev(opaque, boot_device, errp);
500 }
501
502 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
503 {
504 int val, nb, i;
505 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
506 FLOPPY_DRIVE_TYPE_NONE };
507
508 /* floppy type */
509 if (floppy) {
510 for (i = 0; i < 2; i++) {
511 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
512 }
513 }
514 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
515 cmos_get_fd_drive_type(fd_type[1]);
516 rtc_set_memory(rtc_state, 0x10, val);
517
518 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
519 nb = 0;
520 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
521 nb++;
522 }
523 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
524 nb++;
525 }
526 switch (nb) {
527 case 0:
528 break;
529 case 1:
530 val |= 0x01; /* 1 drive, ready for boot */
531 break;
532 case 2:
533 val |= 0x41; /* 2 drives, ready for boot */
534 break;
535 }
536 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
537 }
538
539 typedef struct pc_cmos_init_late_arg {
540 ISADevice *rtc_state;
541 BusState *idebus[2];
542 } pc_cmos_init_late_arg;
543
544 typedef struct check_fdc_state {
545 ISADevice *floppy;
546 bool multiple;
547 } CheckFdcState;
548
549 static int check_fdc(Object *obj, void *opaque)
550 {
551 CheckFdcState *state = opaque;
552 Object *fdc;
553 uint32_t iobase;
554 Error *local_err = NULL;
555
556 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
557 if (!fdc) {
558 return 0;
559 }
560
561 iobase = object_property_get_uint(obj, "iobase", &local_err);
562 if (local_err || iobase != 0x3f0) {
563 error_free(local_err);
564 return 0;
565 }
566
567 if (state->floppy) {
568 state->multiple = true;
569 } else {
570 state->floppy = ISA_DEVICE(obj);
571 }
572 return 0;
573 }
574
575 static const char * const fdc_container_path[] = {
576 "/unattached", "/peripheral", "/peripheral-anon"
577 };
578
579 /*
580 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
581 * and ACPI objects.
582 */
583 static ISADevice *pc_find_fdc0(void)
584 {
585 int i;
586 Object *container;
587 CheckFdcState state = { 0 };
588
589 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
590 container = container_get(qdev_get_machine(), fdc_container_path[i]);
591 object_child_foreach(container, check_fdc, &state);
592 }
593
594 if (state.multiple) {
595 warn_report("multiple floppy disk controllers with "
596 "iobase=0x3f0 have been found");
597 error_printf("the one being picked for CMOS setup might not reflect "
598 "your intent");
599 }
600
601 return state.floppy;
602 }
603
604 static void pc_cmos_init_late(void *opaque)
605 {
606 pc_cmos_init_late_arg *arg = opaque;
607 ISADevice *s = arg->rtc_state;
608 int16_t cylinders;
609 int8_t heads, sectors;
610 int val;
611 int i, trans;
612
613 val = 0;
614 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
615 &cylinders, &heads, &sectors) >= 0) {
616 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
617 val |= 0xf0;
618 }
619 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
620 &cylinders, &heads, &sectors) >= 0) {
621 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
622 val |= 0x0f;
623 }
624 rtc_set_memory(s, 0x12, val);
625
626 val = 0;
627 for (i = 0; i < 4; i++) {
628 /* NOTE: ide_get_geometry() returns the physical
629 geometry. It is always such that: 1 <= sects <= 63, 1
630 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
631 geometry can be different if a translation is done. */
632 if (arg->idebus[i / 2] &&
633 ide_get_geometry(arg->idebus[i / 2], i % 2,
634 &cylinders, &heads, &sectors) >= 0) {
635 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
636 assert((trans & ~3) == 0);
637 val |= trans << (i * 2);
638 }
639 }
640 rtc_set_memory(s, 0x39, val);
641
642 pc_cmos_init_floppy(s, pc_find_fdc0());
643
644 qemu_unregister_reset(pc_cmos_init_late, opaque);
645 }
646
647 void pc_cmos_init(PCMachineState *pcms,
648 BusState *idebus0, BusState *idebus1,
649 ISADevice *s)
650 {
651 int val;
652 static pc_cmos_init_late_arg arg;
653 X86MachineState *x86ms = X86_MACHINE(pcms);
654
655 /* various important CMOS locations needed by PC/Bochs bios */
656
657 /* memory size */
658 /* base memory (first MiB) */
659 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
660 rtc_set_memory(s, 0x15, val);
661 rtc_set_memory(s, 0x16, val >> 8);
662 /* extended memory (next 64MiB) */
663 if (x86ms->below_4g_mem_size > 1 * MiB) {
664 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
665 } else {
666 val = 0;
667 }
668 if (val > 65535)
669 val = 65535;
670 rtc_set_memory(s, 0x17, val);
671 rtc_set_memory(s, 0x18, val >> 8);
672 rtc_set_memory(s, 0x30, val);
673 rtc_set_memory(s, 0x31, val >> 8);
674 /* memory between 16MiB and 4GiB */
675 if (x86ms->below_4g_mem_size > 16 * MiB) {
676 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
677 } else {
678 val = 0;
679 }
680 if (val > 65535)
681 val = 65535;
682 rtc_set_memory(s, 0x34, val);
683 rtc_set_memory(s, 0x35, val >> 8);
684 /* memory above 4GiB */
685 val = x86ms->above_4g_mem_size / 65536;
686 rtc_set_memory(s, 0x5b, val);
687 rtc_set_memory(s, 0x5c, val >> 8);
688 rtc_set_memory(s, 0x5d, val >> 16);
689
690 object_property_add_link(OBJECT(pcms), "rtc_state",
691 TYPE_ISA_DEVICE,
692 (Object **)&x86ms->rtc,
693 object_property_allow_set_link,
694 OBJ_PROP_LINK_STRONG);
695 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
696 &error_abort);
697
698 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
699
700 val = 0;
701 val |= 0x02; /* FPU is there */
702 val |= 0x04; /* PS/2 mouse installed */
703 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
704
705 /* hard drives and FDC */
706 arg.rtc_state = s;
707 arg.idebus[0] = idebus0;
708 arg.idebus[1] = idebus1;
709 qemu_register_reset(pc_cmos_init_late, &arg);
710 }
711
712 static void handle_a20_line_change(void *opaque, int irq, int level)
713 {
714 X86CPU *cpu = opaque;
715
716 /* XXX: send to all CPUs ? */
717 /* XXX: add logic to handle multiple A20 line sources */
718 x86_cpu_set_a20(cpu, level);
719 }
720
721 #define NE2000_NB_MAX 6
722
723 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
724 0x280, 0x380 };
725 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
726
727 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
728 {
729 static int nb_ne2k = 0;
730
731 if (nb_ne2k == NE2000_NB_MAX)
732 return;
733 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
734 ne2000_irq[nb_ne2k], nd);
735 nb_ne2k++;
736 }
737
738 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
739 {
740 X86CPU *cpu = opaque;
741
742 if (level) {
743 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
744 }
745 }
746
747 static
748 void pc_machine_done(Notifier *notifier, void *data)
749 {
750 PCMachineState *pcms = container_of(notifier,
751 PCMachineState, machine_done);
752 X86MachineState *x86ms = X86_MACHINE(pcms);
753
754 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
755 &error_fatal);
756
757 if (pcms->cxl_devices_state.is_enabled) {
758 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
759 }
760
761 /* set the number of CPUs */
762 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
763
764 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
765
766 acpi_setup();
767 if (x86ms->fw_cfg) {
768 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
769 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
770 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
771 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
772 }
773 }
774
775 void pc_guest_info_init(PCMachineState *pcms)
776 {
777 X86MachineState *x86ms = X86_MACHINE(pcms);
778
779 x86ms->apic_xrupt_override = true;
780 pcms->machine_done.notify = pc_machine_done;
781 qemu_add_machine_init_done_notifier(&pcms->machine_done);
782 }
783
784 /* setup pci memory address space mapping into system address space */
785 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
786 MemoryRegion *pci_address_space)
787 {
788 /* Set to lower priority than RAM */
789 memory_region_add_subregion_overlap(system_memory, 0x0,
790 pci_address_space, -1);
791 }
792
793 void xen_load_linux(PCMachineState *pcms)
794 {
795 int i;
796 FWCfgState *fw_cfg;
797 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
798 X86MachineState *x86ms = X86_MACHINE(pcms);
799
800 assert(MACHINE(pcms)->kernel_filename != NULL);
801
802 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
803 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
804 rom_set_fw(fw_cfg);
805
806 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
807 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
808 for (i = 0; i < nb_option_roms; i++) {
809 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
810 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
811 !strcmp(option_rom[i].name, "pvh.bin") ||
812 !strcmp(option_rom[i].name, "multiboot.bin") ||
813 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
814 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
815 }
816 x86ms->fw_cfg = fw_cfg;
817 }
818
819 #define PC_ROM_MIN_VGA 0xc0000
820 #define PC_ROM_MIN_OPTION 0xc8000
821 #define PC_ROM_MAX 0xe0000
822 #define PC_ROM_ALIGN 0x800
823 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
824
825 static hwaddr pc_above_4g_end(PCMachineState *pcms)
826 {
827 X86MachineState *x86ms = X86_MACHINE(pcms);
828
829 if (pcms->sgx_epc.size != 0) {
830 return sgx_epc_above_4g_end(&pcms->sgx_epc);
831 }
832
833 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
834 }
835
836 static void pc_get_device_memory_range(PCMachineState *pcms,
837 hwaddr *base,
838 ram_addr_t *device_mem_size)
839 {
840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
841 MachineState *machine = MACHINE(pcms);
842 ram_addr_t size;
843 hwaddr addr;
844
845 size = machine->maxram_size - machine->ram_size;
846 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
847
848 if (pcmc->enforce_aligned_dimm) {
849 /* size device region assuming 1G page max alignment per slot */
850 size += (1 * GiB) * machine->ram_slots;
851 }
852
853 *base = addr;
854 *device_mem_size = size;
855 }
856
857 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
858 {
859 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
860 hwaddr cxl_base;
861 ram_addr_t size;
862
863 if (pcmc->has_reserved_memory) {
864 pc_get_device_memory_range(pcms, &cxl_base, &size);
865 cxl_base += size;
866 } else {
867 cxl_base = pc_above_4g_end(pcms);
868 }
869
870 return cxl_base;
871 }
872
873 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
874 {
875 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
876
877 if (pcms->cxl_devices_state.fixed_windows) {
878 GList *it;
879
880 start = ROUND_UP(start, 256 * MiB);
881 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
882 CXLFixedWindow *fw = it->data;
883 start += fw->size;
884 }
885 }
886
887 return start;
888 }
889
890 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
891 {
892 X86CPU *cpu = X86_CPU(first_cpu);
893
894 /* 32-bit systems don't have hole64 thus return max CPU address */
895 if (cpu->phys_bits <= 32) {
896 return ((hwaddr)1 << cpu->phys_bits) - 1;
897 }
898
899 return pc_pci_hole64_start() + pci_hole64_size - 1;
900 }
901
902 /*
903 * AMD systems with an IOMMU have an additional hole close to the
904 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
905 * on kernel version, VFIO may or may not let you DMA map those ranges.
906 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
907 * with certain memory sizes. It's also wrong to use those IOVA ranges
908 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
909 * The ranges reserved for Hyper-Transport are:
910 *
911 * FD_0000_0000h - FF_FFFF_FFFFh
912 *
913 * The ranges represent the following:
914 *
915 * Base Address Top Address Use
916 *
917 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
918 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
919 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
920 * FD_F910_0000h FD_F91F_FFFFh System Management
921 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
922 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
923 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
924 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
925 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
926 * FE_2000_0000h FF_FFFF_FFFFh Reserved
927 *
928 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
929 * Table 3: Special Address Controls (GPA) for more information.
930 */
931 #define AMD_HT_START 0xfd00000000UL
932 #define AMD_HT_END 0xffffffffffUL
933 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
934 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
935
936 void pc_memory_init(PCMachineState *pcms,
937 MemoryRegion *system_memory,
938 MemoryRegion *rom_memory,
939 MemoryRegion **ram_memory,
940 uint64_t pci_hole64_size)
941 {
942 int linux_boot, i;
943 MemoryRegion *option_rom_mr;
944 MemoryRegion *ram_below_4g, *ram_above_4g;
945 FWCfgState *fw_cfg;
946 MachineState *machine = MACHINE(pcms);
947 MachineClass *mc = MACHINE_GET_CLASS(machine);
948 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
949 X86MachineState *x86ms = X86_MACHINE(pcms);
950 hwaddr maxphysaddr, maxusedaddr;
951 hwaddr cxl_base, cxl_resv_end = 0;
952 X86CPU *cpu = X86_CPU(first_cpu);
953
954 assert(machine->ram_size == x86ms->below_4g_mem_size +
955 x86ms->above_4g_mem_size);
956
957 linux_boot = (machine->kernel_filename != NULL);
958
959 /*
960 * The HyperTransport range close to the 1T boundary is unique to AMD
961 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
962 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
963 * older machine types (<= 7.0) for compatibility purposes.
964 */
965 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
966 /* Bail out if max possible address does not cross HT range */
967 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
968 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
969 }
970
971 /*
972 * Advertise the HT region if address space covers the reserved
973 * region or if we relocate.
974 */
975 if (cpu->phys_bits >= 40) {
976 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
977 }
978 }
979
980 /*
981 * phys-bits is required to be appropriately configured
982 * to make sure max used GPA is reachable.
983 */
984 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
985 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
986 if (maxphysaddr < maxusedaddr) {
987 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
988 " phys-bits too low (%u)",
989 maxphysaddr, maxusedaddr, cpu->phys_bits);
990 exit(EXIT_FAILURE);
991 }
992
993 /*
994 * Split single memory region and use aliases to address portions of it,
995 * done for backwards compatibility with older qemus.
996 */
997 *ram_memory = machine->ram;
998 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
999 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
1000 0, x86ms->below_4g_mem_size);
1001 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1002 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1003 if (x86ms->above_4g_mem_size > 0) {
1004 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1005 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1006 machine->ram,
1007 x86ms->below_4g_mem_size,
1008 x86ms->above_4g_mem_size);
1009 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1010 ram_above_4g);
1011 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1012 E820_RAM);
1013 }
1014
1015 if (pcms->sgx_epc.size != 0) {
1016 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1017 }
1018
1019 if (!pcmc->has_reserved_memory &&
1020 (machine->ram_slots ||
1021 (machine->maxram_size > machine->ram_size))) {
1022
1023 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1024 mc->name);
1025 exit(EXIT_FAILURE);
1026 }
1027
1028 /* always allocate the device memory information */
1029 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1030
1031 /* initialize device memory address space */
1032 if (pcmc->has_reserved_memory &&
1033 (machine->ram_size < machine->maxram_size)) {
1034 ram_addr_t device_mem_size;
1035
1036 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1037 error_report("unsupported amount of memory slots: %"PRIu64,
1038 machine->ram_slots);
1039 exit(EXIT_FAILURE);
1040 }
1041
1042 if (QEMU_ALIGN_UP(machine->maxram_size,
1043 TARGET_PAGE_SIZE) != machine->maxram_size) {
1044 error_report("maximum memory size must by aligned to multiple of "
1045 "%d bytes", TARGET_PAGE_SIZE);
1046 exit(EXIT_FAILURE);
1047 }
1048
1049 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1050
1051 if ((machine->device_memory->base + device_mem_size) <
1052 device_mem_size) {
1053 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1054 machine->maxram_size);
1055 exit(EXIT_FAILURE);
1056 }
1057
1058 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1059 "device-memory", device_mem_size);
1060 memory_region_add_subregion(system_memory, machine->device_memory->base,
1061 &machine->device_memory->mr);
1062 }
1063
1064 if (pcms->cxl_devices_state.is_enabled) {
1065 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1066 hwaddr cxl_size = MiB;
1067
1068 cxl_base = pc_get_cxl_range_start(pcms);
1069 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1070 memory_region_add_subregion(system_memory, cxl_base, mr);
1071 cxl_resv_end = cxl_base + cxl_size;
1072 if (pcms->cxl_devices_state.fixed_windows) {
1073 hwaddr cxl_fmw_base;
1074 GList *it;
1075
1076 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1077 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1078 CXLFixedWindow *fw = it->data;
1079
1080 fw->base = cxl_fmw_base;
1081 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1082 "cxl-fixed-memory-region", fw->size);
1083 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1084 cxl_fmw_base += fw->size;
1085 cxl_resv_end = cxl_fmw_base;
1086 }
1087 }
1088 }
1089
1090 /* Initialize PC system firmware */
1091 pc_system_firmware_init(pcms, rom_memory);
1092
1093 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1094 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1095 &error_fatal);
1096 if (pcmc->pci_enabled) {
1097 memory_region_set_readonly(option_rom_mr, true);
1098 }
1099 memory_region_add_subregion_overlap(rom_memory,
1100 PC_ROM_MIN_VGA,
1101 option_rom_mr,
1102 1);
1103
1104 fw_cfg = fw_cfg_arch_create(machine,
1105 x86ms->boot_cpus, x86ms->apic_id_limit);
1106
1107 rom_set_fw(fw_cfg);
1108
1109 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1110 uint64_t *val = g_malloc(sizeof(*val));
1111 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1112 uint64_t res_mem_end = machine->device_memory->base;
1113
1114 if (!pcmc->broken_reserved_end) {
1115 res_mem_end += memory_region_size(&machine->device_memory->mr);
1116 }
1117
1118 if (pcms->cxl_devices_state.is_enabled) {
1119 res_mem_end = cxl_resv_end;
1120 }
1121 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1122 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1123 }
1124
1125 if (linux_boot) {
1126 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1127 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
1128 }
1129
1130 for (i = 0; i < nb_option_roms; i++) {
1131 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1132 }
1133 x86ms->fw_cfg = fw_cfg;
1134
1135 /* Init default IOAPIC address space */
1136 x86ms->ioapic_as = &address_space_memory;
1137
1138 /* Init ACPI memory hotplug IO base address */
1139 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1140 }
1141
1142 /*
1143 * The 64bit pci hole starts after "above 4G RAM" and
1144 * potentially the space reserved for memory hotplug.
1145 */
1146 uint64_t pc_pci_hole64_start(void)
1147 {
1148 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1149 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1150 MachineState *ms = MACHINE(pcms);
1151 uint64_t hole64_start = 0;
1152 ram_addr_t size = 0;
1153
1154 if (pcms->cxl_devices_state.is_enabled) {
1155 hole64_start = pc_get_cxl_range_end(pcms);
1156 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1157 pc_get_device_memory_range(pcms, &hole64_start, &size);
1158 if (!pcmc->broken_reserved_end) {
1159 hole64_start += size;
1160 }
1161 } else {
1162 hole64_start = pc_above_4g_end(pcms);
1163 }
1164
1165 return ROUND_UP(hole64_start, 1 * GiB);
1166 }
1167
1168 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1169 {
1170 DeviceState *dev = NULL;
1171
1172 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1173 if (pci_bus) {
1174 PCIDevice *pcidev = pci_vga_init(pci_bus);
1175 dev = pcidev ? &pcidev->qdev : NULL;
1176 } else if (isa_bus) {
1177 ISADevice *isadev = isa_vga_init(isa_bus);
1178 dev = isadev ? DEVICE(isadev) : NULL;
1179 }
1180 rom_reset_order_override();
1181 return dev;
1182 }
1183
1184 static const MemoryRegionOps ioport80_io_ops = {
1185 .write = ioport80_write,
1186 .read = ioport80_read,
1187 .endianness = DEVICE_NATIVE_ENDIAN,
1188 .impl = {
1189 .min_access_size = 1,
1190 .max_access_size = 1,
1191 },
1192 };
1193
1194 static const MemoryRegionOps ioportF0_io_ops = {
1195 .write = ioportF0_write,
1196 .read = ioportF0_read,
1197 .endianness = DEVICE_NATIVE_ENDIAN,
1198 .impl = {
1199 .min_access_size = 1,
1200 .max_access_size = 1,
1201 },
1202 };
1203
1204 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1205 bool create_i8042, bool no_vmport)
1206 {
1207 int i;
1208 DriveInfo *fd[MAX_FD];
1209 qemu_irq *a20_line;
1210 ISADevice *fdc, *i8042, *port92, *vmmouse;
1211
1212 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1213 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1214
1215 for (i = 0; i < MAX_FD; i++) {
1216 fd[i] = drive_get(IF_FLOPPY, 0, i);
1217 create_fdctrl |= !!fd[i];
1218 }
1219 if (create_fdctrl) {
1220 fdc = isa_new(TYPE_ISA_FDC);
1221 if (fdc) {
1222 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1223 isa_fdc_init_drives(fdc, fd);
1224 }
1225 }
1226
1227 if (!create_i8042) {
1228 return;
1229 }
1230
1231 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1232 if (!no_vmport) {
1233 isa_create_simple(isa_bus, TYPE_VMPORT);
1234 vmmouse = isa_try_new("vmmouse");
1235 } else {
1236 vmmouse = NULL;
1237 }
1238 if (vmmouse) {
1239 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1240 &error_abort);
1241 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1242 }
1243 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1244
1245 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1246 i8042_setup_a20_line(i8042, a20_line[0]);
1247 qdev_connect_gpio_out_named(DEVICE(port92),
1248 PORT92_A20_LINE, 0, a20_line[1]);
1249 g_free(a20_line);
1250 }
1251
1252 void pc_basic_device_init(struct PCMachineState *pcms,
1253 ISABus *isa_bus, qemu_irq *gsi,
1254 ISADevice **rtc_state,
1255 bool create_fdctrl,
1256 uint32_t hpet_irqs)
1257 {
1258 int i;
1259 DeviceState *hpet = NULL;
1260 int pit_isa_irq = 0;
1261 qemu_irq pit_alt_irq = NULL;
1262 qemu_irq rtc_irq = NULL;
1263 ISADevice *pit = NULL;
1264 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1265 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1266 X86MachineState *x86ms = X86_MACHINE(pcms);
1267
1268 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1269 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1270
1271 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1272 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1273
1274 /*
1275 * Check if an HPET shall be created.
1276 *
1277 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1278 * when the HPET wants to take over. Thus we have to disable the latter.
1279 */
1280 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1281 kvm_has_pit_state2())) {
1282 hpet = qdev_try_new(TYPE_HPET);
1283 if (!hpet) {
1284 error_report("couldn't create HPET device");
1285 exit(1);
1286 }
1287 /*
1288 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1289 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1290 * IRQ2.
1291 */
1292 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1293 HPET_INTCAP, NULL);
1294 if (!compat) {
1295 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1296 }
1297 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1298 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1299
1300 for (i = 0; i < GSI_NUM_PINS; i++) {
1301 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1302 }
1303 pit_isa_irq = -1;
1304 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1305 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1306 }
1307 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1308
1309 qemu_register_boot_set(pc_boot_set, *rtc_state);
1310
1311 if (!xen_enabled() &&
1312 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1313 if (kvm_pit_in_kernel()) {
1314 pit = kvm_pit_init(isa_bus, 0x40);
1315 } else {
1316 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1317 }
1318 if (hpet) {
1319 /* connect PIT to output control line of the HPET */
1320 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1321 }
1322 pcspk_init(pcms->pcspk, isa_bus, pit);
1323 }
1324
1325 /* Super I/O */
1326 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1327 pcms->vmport != ON_OFF_AUTO_ON);
1328 }
1329
1330 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1331 {
1332 int i;
1333
1334 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1335 for (i = 0; i < nb_nics; i++) {
1336 NICInfo *nd = &nd_table[i];
1337 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1338
1339 if (g_str_equal(model, "ne2k_isa")) {
1340 pc_init_ne2k_isa(isa_bus, nd);
1341 } else {
1342 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1343 }
1344 }
1345 rom_reset_order_override();
1346 }
1347
1348 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1349 {
1350 qemu_irq *i8259;
1351
1352 if (kvm_pic_in_kernel()) {
1353 i8259 = kvm_i8259_init(isa_bus);
1354 } else if (xen_enabled()) {
1355 i8259 = xen_interrupt_controller_init();
1356 } else {
1357 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1358 }
1359
1360 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1361 i8259_irqs[i] = i8259[i];
1362 }
1363
1364 g_free(i8259);
1365 }
1366
1367 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1368 Error **errp)
1369 {
1370 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1371 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1372 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1373 const MachineState *ms = MACHINE(hotplug_dev);
1374 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1375 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1376 Error *local_err = NULL;
1377
1378 /*
1379 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1380 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1381 * addition to cover this case.
1382 */
1383 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1384 error_setg(errp,
1385 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1386 return;
1387 }
1388
1389 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1390 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1391 return;
1392 }
1393
1394 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1395 if (local_err) {
1396 error_propagate(errp, local_err);
1397 return;
1398 }
1399
1400 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1401 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1402 }
1403
1404 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1405 DeviceState *dev, Error **errp)
1406 {
1407 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1408 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1409 MachineState *ms = MACHINE(hotplug_dev);
1410 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1411
1412 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1413
1414 if (is_nvdimm) {
1415 nvdimm_plug(ms->nvdimms_state);
1416 }
1417
1418 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1419 }
1420
1421 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1422 DeviceState *dev, Error **errp)
1423 {
1424 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1425
1426 /*
1427 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1428 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1429 * addition to cover this case.
1430 */
1431 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1432 error_setg(errp,
1433 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1434 return;
1435 }
1436
1437 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1438 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1439 return;
1440 }
1441
1442 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1443 errp);
1444 }
1445
1446 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1447 DeviceState *dev, Error **errp)
1448 {
1449 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1450 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1451 Error *local_err = NULL;
1452
1453 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1454 if (local_err) {
1455 goto out;
1456 }
1457
1458 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1459 qdev_unrealize(dev);
1460 out:
1461 error_propagate(errp, local_err);
1462 }
1463
1464 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1465 DeviceState *dev, Error **errp)
1466 {
1467 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1468 Error *local_err = NULL;
1469
1470 if (!hotplug_dev2 && dev->hotplugged) {
1471 /*
1472 * Without a bus hotplug handler, we cannot control the plug/unplug
1473 * order. We should never reach this point when hotplugging on x86,
1474 * however, better add a safety net.
1475 */
1476 error_setg(errp, "hotplug of virtio based memory devices not supported"
1477 " on this bus.");
1478 return;
1479 }
1480 /*
1481 * First, see if we can plug this memory device at all. If that
1482 * succeeds, branch of to the actual hotplug handler.
1483 */
1484 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1485 &local_err);
1486 if (!local_err && hotplug_dev2) {
1487 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1488 }
1489 error_propagate(errp, local_err);
1490 }
1491
1492 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1493 DeviceState *dev, Error **errp)
1494 {
1495 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1496 Error *local_err = NULL;
1497
1498 /*
1499 * Plug the memory device first and then branch off to the actual
1500 * hotplug handler. If that one fails, we can easily undo the memory
1501 * device bits.
1502 */
1503 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1504 if (hotplug_dev2) {
1505 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1506 if (local_err) {
1507 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1508 }
1509 }
1510 error_propagate(errp, local_err);
1511 }
1512
1513 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1514 DeviceState *dev, Error **errp)
1515 {
1516 /* We don't support hot unplug of virtio based memory devices */
1517 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1518 }
1519
1520 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1521 DeviceState *dev, Error **errp)
1522 {
1523 /* We don't support hot unplug of virtio based memory devices */
1524 }
1525
1526 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1527 DeviceState *dev, Error **errp)
1528 {
1529 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1530 pc_memory_pre_plug(hotplug_dev, dev, errp);
1531 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1532 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1533 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1534 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1535 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1536 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1537 /* Declare the APIC range as the reserved MSI region */
1538 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1539 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1540
1541 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1542 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1543 resv_prop_str, errp);
1544 g_free(resv_prop_str);
1545 }
1546
1547 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1548 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1549 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1550
1551 if (pcms->iommu) {
1552 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1553 "for x86 yet.");
1554 return;
1555 }
1556 pcms->iommu = dev;
1557 }
1558 }
1559
1560 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1561 DeviceState *dev, Error **errp)
1562 {
1563 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1564 pc_memory_plug(hotplug_dev, dev, errp);
1565 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1566 x86_cpu_plug(hotplug_dev, dev, errp);
1567 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1568 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1569 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1570 }
1571 }
1572
1573 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1574 DeviceState *dev, Error **errp)
1575 {
1576 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1577 pc_memory_unplug_request(hotplug_dev, dev, errp);
1578 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1579 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1580 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1581 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1582 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1583 } else {
1584 error_setg(errp, "acpi: device unplug request for not supported device"
1585 " type: %s", object_get_typename(OBJECT(dev)));
1586 }
1587 }
1588
1589 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1590 DeviceState *dev, Error **errp)
1591 {
1592 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1593 pc_memory_unplug(hotplug_dev, dev, errp);
1594 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1595 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1596 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1597 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1598 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1599 } else {
1600 error_setg(errp, "acpi: device unplug for not supported device"
1601 " type: %s", object_get_typename(OBJECT(dev)));
1602 }
1603 }
1604
1605 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1606 DeviceState *dev)
1607 {
1608 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1609 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1610 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1611 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1612 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1613 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1614 return HOTPLUG_HANDLER(machine);
1615 }
1616
1617 return NULL;
1618 }
1619
1620 static void
1621 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1622 const char *name, void *opaque,
1623 Error **errp)
1624 {
1625 MachineState *ms = MACHINE(obj);
1626 int64_t value = 0;
1627
1628 if (ms->device_memory) {
1629 value = memory_region_size(&ms->device_memory->mr);
1630 }
1631
1632 visit_type_int(v, name, &value, errp);
1633 }
1634
1635 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1636 void *opaque, Error **errp)
1637 {
1638 PCMachineState *pcms = PC_MACHINE(obj);
1639 OnOffAuto vmport = pcms->vmport;
1640
1641 visit_type_OnOffAuto(v, name, &vmport, errp);
1642 }
1643
1644 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1645 void *opaque, Error **errp)
1646 {
1647 PCMachineState *pcms = PC_MACHINE(obj);
1648
1649 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1650 }
1651
1652 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1653 {
1654 PCMachineState *pcms = PC_MACHINE(obj);
1655
1656 return pcms->smbus_enabled;
1657 }
1658
1659 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1660 {
1661 PCMachineState *pcms = PC_MACHINE(obj);
1662
1663 pcms->smbus_enabled = value;
1664 }
1665
1666 static bool pc_machine_get_sata(Object *obj, Error **errp)
1667 {
1668 PCMachineState *pcms = PC_MACHINE(obj);
1669
1670 return pcms->sata_enabled;
1671 }
1672
1673 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1674 {
1675 PCMachineState *pcms = PC_MACHINE(obj);
1676
1677 pcms->sata_enabled = value;
1678 }
1679
1680 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1681 {
1682 PCMachineState *pcms = PC_MACHINE(obj);
1683
1684 return pcms->hpet_enabled;
1685 }
1686
1687 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1688 {
1689 PCMachineState *pcms = PC_MACHINE(obj);
1690
1691 pcms->hpet_enabled = value;
1692 }
1693
1694 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1695 {
1696 PCMachineState *pcms = PC_MACHINE(obj);
1697
1698 return pcms->i8042_enabled;
1699 }
1700
1701 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1702 {
1703 PCMachineState *pcms = PC_MACHINE(obj);
1704
1705 pcms->i8042_enabled = value;
1706 }
1707
1708 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1709 {
1710 PCMachineState *pcms = PC_MACHINE(obj);
1711
1712 return pcms->default_bus_bypass_iommu;
1713 }
1714
1715 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1716 Error **errp)
1717 {
1718 PCMachineState *pcms = PC_MACHINE(obj);
1719
1720 pcms->default_bus_bypass_iommu = value;
1721 }
1722
1723 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1724 void *opaque, Error **errp)
1725 {
1726 PCMachineState *pcms = PC_MACHINE(obj);
1727 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1728
1729 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1730 }
1731
1732 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1733 void *opaque, Error **errp)
1734 {
1735 PCMachineState *pcms = PC_MACHINE(obj);
1736
1737 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1738 }
1739
1740 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1741 const char *name, void *opaque,
1742 Error **errp)
1743 {
1744 PCMachineState *pcms = PC_MACHINE(obj);
1745 uint64_t value = pcms->max_ram_below_4g;
1746
1747 visit_type_size(v, name, &value, errp);
1748 }
1749
1750 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1751 const char *name, void *opaque,
1752 Error **errp)
1753 {
1754 PCMachineState *pcms = PC_MACHINE(obj);
1755 uint64_t value;
1756
1757 if (!visit_type_size(v, name, &value, errp)) {
1758 return;
1759 }
1760 if (value > 4 * GiB) {
1761 error_setg(errp,
1762 "Machine option 'max-ram-below-4g=%"PRIu64
1763 "' expects size less than or equal to 4G", value);
1764 return;
1765 }
1766
1767 if (value < 1 * MiB) {
1768 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1769 "BIOS may not work with less than 1MiB", value);
1770 }
1771
1772 pcms->max_ram_below_4g = value;
1773 }
1774
1775 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1776 const char *name, void *opaque,
1777 Error **errp)
1778 {
1779 PCMachineState *pcms = PC_MACHINE(obj);
1780 uint64_t value = pcms->max_fw_size;
1781
1782 visit_type_size(v, name, &value, errp);
1783 }
1784
1785 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1786 const char *name, void *opaque,
1787 Error **errp)
1788 {
1789 PCMachineState *pcms = PC_MACHINE(obj);
1790 uint64_t value;
1791
1792 if (!visit_type_size(v, name, &value, errp)) {
1793 return;
1794 }
1795
1796 /*
1797 * We don't have a theoretically justifiable exact lower bound on the base
1798 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1799 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1800 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1801 * size.
1802 */
1803 if (value > 16 * MiB) {
1804 error_setg(errp,
1805 "User specified max allowed firmware size %" PRIu64 " is "
1806 "greater than 16MiB. If combined firwmare size exceeds "
1807 "16MiB the system may not boot, or experience intermittent"
1808 "stability issues.",
1809 value);
1810 return;
1811 }
1812
1813 pcms->max_fw_size = value;
1814 }
1815
1816
1817 static void pc_machine_initfn(Object *obj)
1818 {
1819 PCMachineState *pcms = PC_MACHINE(obj);
1820
1821 #ifdef CONFIG_VMPORT
1822 pcms->vmport = ON_OFF_AUTO_AUTO;
1823 #else
1824 pcms->vmport = ON_OFF_AUTO_OFF;
1825 #endif /* CONFIG_VMPORT */
1826 pcms->max_ram_below_4g = 0; /* use default */
1827 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1828
1829 /* acpi build is enabled by default if machine supports it */
1830 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1831 pcms->smbus_enabled = true;
1832 pcms->sata_enabled = true;
1833 pcms->i8042_enabled = true;
1834 pcms->max_fw_size = 8 * MiB;
1835 #ifdef CONFIG_HPET
1836 pcms->hpet_enabled = true;
1837 #endif
1838 pcms->default_bus_bypass_iommu = false;
1839
1840 pc_system_flash_create(pcms);
1841 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1842 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1843 OBJECT(pcms->pcspk), "audiodev");
1844 cxl_machine_init(obj, &pcms->cxl_devices_state);
1845 }
1846
1847 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1848 {
1849 CPUState *cs;
1850 X86CPU *cpu;
1851
1852 qemu_devices_reset(reason);
1853
1854 /* Reset APIC after devices have been reset to cancel
1855 * any changes that qemu_devices_reset() might have done.
1856 */
1857 CPU_FOREACH(cs) {
1858 cpu = X86_CPU(cs);
1859
1860 x86_cpu_after_reset(cpu);
1861 }
1862 }
1863
1864 static void pc_machine_wakeup(MachineState *machine)
1865 {
1866 cpu_synchronize_all_states();
1867 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1868 cpu_synchronize_all_post_reset();
1869 }
1870
1871 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1872 {
1873 X86IOMMUState *iommu = x86_iommu_get_default();
1874 IntelIOMMUState *intel_iommu;
1875
1876 if (iommu &&
1877 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1878 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1879 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1880 if (!intel_iommu->caching_mode) {
1881 error_setg(errp, "Device assignment is not allowed without "
1882 "enabling caching-mode=on for Intel IOMMU.");
1883 return false;
1884 }
1885 }
1886
1887 return true;
1888 }
1889
1890 static void pc_machine_class_init(ObjectClass *oc, void *data)
1891 {
1892 MachineClass *mc = MACHINE_CLASS(oc);
1893 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1894 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1895
1896 pcmc->pci_enabled = true;
1897 pcmc->has_acpi_build = true;
1898 pcmc->rsdp_in_ram = true;
1899 pcmc->smbios_defaults = true;
1900 pcmc->smbios_uuid_encoded = true;
1901 pcmc->gigabyte_align = true;
1902 pcmc->has_reserved_memory = true;
1903 pcmc->kvmclock_enabled = true;
1904 pcmc->enforce_aligned_dimm = true;
1905 pcmc->enforce_amd_1tb_hole = true;
1906 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1907 * to be used at the moment, 32K should be enough for a while. */
1908 pcmc->acpi_data_size = 0x20000 + 0x8000;
1909 pcmc->pvh_enabled = true;
1910 pcmc->kvmclock_create_always = true;
1911 assert(!mc->get_hotplug_handler);
1912 mc->get_hotplug_handler = pc_get_hotplug_handler;
1913 mc->hotplug_allowed = pc_hotplug_allowed;
1914 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1915 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1916 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1917 mc->auto_enable_numa_with_memhp = true;
1918 mc->auto_enable_numa_with_memdev = true;
1919 mc->has_hotpluggable_cpus = true;
1920 mc->default_boot_order = "cad";
1921 mc->block_default_type = IF_IDE;
1922 mc->max_cpus = 255;
1923 mc->reset = pc_machine_reset;
1924 mc->wakeup = pc_machine_wakeup;
1925 hc->pre_plug = pc_machine_device_pre_plug_cb;
1926 hc->plug = pc_machine_device_plug_cb;
1927 hc->unplug_request = pc_machine_device_unplug_request_cb;
1928 hc->unplug = pc_machine_device_unplug_cb;
1929 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1930 mc->nvdimm_supported = true;
1931 mc->smp_props.dies_supported = true;
1932 mc->default_ram_id = "pc.ram";
1933
1934 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1935 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1936 NULL, NULL);
1937 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1938 "Maximum ram below the 4G boundary (32bit boundary)");
1939
1940 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1941 pc_machine_get_device_memory_region_size, NULL,
1942 NULL, NULL);
1943
1944 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1945 pc_machine_get_vmport, pc_machine_set_vmport,
1946 NULL, NULL);
1947 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1948 "Enable vmport (pc & q35)");
1949
1950 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1951 pc_machine_get_smbus, pc_machine_set_smbus);
1952 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1953 "Enable/disable system management bus");
1954
1955 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1956 pc_machine_get_sata, pc_machine_set_sata);
1957 object_class_property_set_description(oc, PC_MACHINE_SATA,
1958 "Enable/disable Serial ATA bus");
1959
1960 object_class_property_add_bool(oc, "hpet",
1961 pc_machine_get_hpet, pc_machine_set_hpet);
1962 object_class_property_set_description(oc, "hpet",
1963 "Enable/disable high precision event timer emulation");
1964
1965 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1966 pc_machine_get_i8042, pc_machine_set_i8042);
1967
1968 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1969 pc_machine_get_default_bus_bypass_iommu,
1970 pc_machine_set_default_bus_bypass_iommu);
1971
1972 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1973 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1974 NULL, NULL);
1975 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1976 "Maximum combined firmware size");
1977
1978 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1979 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1980 NULL, NULL);
1981 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1982 "SMBIOS Entry Point type [32, 64]");
1983 }
1984
1985 static const TypeInfo pc_machine_info = {
1986 .name = TYPE_PC_MACHINE,
1987 .parent = TYPE_X86_MACHINE,
1988 .abstract = true,
1989 .instance_size = sizeof(PCMachineState),
1990 .instance_init = pc_machine_initfn,
1991 .class_size = sizeof(PCMachineClass),
1992 .class_init = pc_machine_class_init,
1993 .interfaces = (InterfaceInfo[]) {
1994 { TYPE_HOTPLUG_HANDLER },
1995 { }
1996 },
1997 };
1998
1999 static void pc_machine_register_types(void)
2000 {
2001 type_register_static(&pc_machine_info);
2002 }
2003
2004 type_init(pc_machine_register_types)
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