2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/net/ne2000-isa.h"
78 /* debug PC/ISA interrupts */
82 #define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85 #define DPRINTF(fmt, ...)
88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94 #define E820_NR_ENTRIES 16
100 } QEMU_PACKED
__attribute((__aligned__(4)));
104 struct e820_entry entry
[E820_NR_ENTRIES
];
105 } QEMU_PACKED
__attribute((__aligned__(4)));
107 static struct e820_table e820_reserve
;
108 static struct e820_entry
*e820_table
;
109 static unsigned e820_entries
;
110 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
112 GlobalProperty pc_compat_3_1
[] = {
114 .driver
= "intel-iommu",
115 .property
= "dma-drain",
119 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
121 GlobalProperty pc_compat_3_0
[] = {
123 .driver
= TYPE_X86_CPU
,
124 .property
= "x-hv-synic-kvm-only",
127 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
131 .driver
= "Skylake-Server-IBRS" "-" TYPE_X86_CPU
,
136 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
138 GlobalProperty pc_compat_2_12
[] = {
140 .driver
= TYPE_X86_CPU
,
141 .property
= "legacy-cache",
144 .driver
= TYPE_X86_CPU
,
145 .property
= "topoext",
148 .driver
= "EPYC-" TYPE_X86_CPU
,
149 .property
= "xlevel",
150 .value
= stringify(0x8000000a),
152 .driver
= "EPYC-IBPB-" TYPE_X86_CPU
,
153 .property
= "xlevel",
154 .value
= stringify(0x8000000a),
157 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
159 GlobalProperty pc_compat_2_11
[] = {
161 .driver
= TYPE_X86_CPU
,
162 .property
= "x-migrate-smi-count",
165 .driver
= "Skylake-Server" "-" TYPE_X86_CPU
,
166 .property
= "clflushopt",
170 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
172 GlobalProperty pc_compat_2_10
[] = {
174 .driver
= TYPE_X86_CPU
,
175 .property
= "x-hv-max-vps",
178 .driver
= "i440FX-pcihost",
179 .property
= "x-pci-hole64-fix",
182 .driver
= "q35-pcihost",
183 .property
= "x-pci-hole64-fix",
187 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
189 GlobalProperty pc_compat_2_9
[] = {
192 .property
= "extended-tseg-mbytes",
193 .value
= stringify(0),
196 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
198 GlobalProperty pc_compat_2_8
[] = {
200 .driver
= TYPE_X86_CPU
,
201 .property
= "tcg-cpuid",
205 .driver
= "kvmclock",
206 .property
= "x-mach-use-reliable-get-clock",
210 .driver
= "ICH9-LPC",
211 .property
= "x-smi-broadcast",
215 .driver
= TYPE_X86_CPU
,
216 .property
= "vmware-cpuid-freq",
220 .driver
= "Haswell-" TYPE_X86_CPU
,
221 .property
= "stepping",
225 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
227 GlobalProperty pc_compat_2_7
[] = {
229 .driver
= TYPE_X86_CPU
,
230 .property
= "l3-cache",
234 .driver
= TYPE_X86_CPU
,
235 .property
= "full-cpuid-auto-level",
239 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
240 .property
= "family",
244 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
249 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
250 .property
= "stepping",
254 .driver
= "isa-pcspk",
255 .property
= "migrate",
259 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
261 GlobalProperty pc_compat_2_6
[] = {
263 .driver
= TYPE_X86_CPU
,
264 .property
= "cpuid-0xb",
268 .property
= "romfile",
272 .driver
= TYPE_X86_CPU
,
273 .property
= "fill-mtrr-mask",
277 .driver
= "apic-common",
278 .property
= "legacy-instance-id",
282 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
284 GlobalProperty pc_compat_2_5
[] = {};
285 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
287 GlobalProperty pc_compat_2_4
[] = {
288 PC_CPU_MODEL_IDS("2.4.0")
290 .driver
= "Haswell-" TYPE_X86_CPU
,
295 .driver
= "Haswell-noTSX-" TYPE_X86_CPU
,
300 .driver
= "Broadwell-" TYPE_X86_CPU
,
305 .driver
= "Broadwell-noTSX-" TYPE_X86_CPU
,
310 .driver
= "host" "-" TYPE_X86_CPU
,
311 .property
= "host-cache-info",
315 .driver
= TYPE_X86_CPU
,
320 .driver
= "qemu64" "-" TYPE_X86_CPU
,
325 .driver
= "qemu64" "-" TYPE_X86_CPU
,
330 .driver
= "qemu64" "-" TYPE_X86_CPU
,
331 .property
= "popcnt",
335 .driver
= "qemu32" "-" TYPE_X86_CPU
,
336 .property
= "popcnt",
339 .driver
= "Opteron_G2" "-" TYPE_X86_CPU
,
340 .property
= "rdtscp",
343 .driver
= "Opteron_G3" "-" TYPE_X86_CPU
,
344 .property
= "rdtscp",
347 .driver
= "Opteron_G4" "-" TYPE_X86_CPU
,
348 .property
= "rdtscp",
351 .driver
= "Opteron_G5" "-" TYPE_X86_CPU
,
352 .property
= "rdtscp",
356 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
358 void gsi_handler(void *opaque
, int n
, int level
)
360 GSIState
*s
= opaque
;
362 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
363 if (n
< ISA_NUM_IRQS
) {
364 qemu_set_irq(s
->i8259_irq
[n
], level
);
366 qemu_set_irq(s
->ioapic_irq
[n
], level
);
369 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
374 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
376 return 0xffffffffffffffffULL
;
379 /* MSDOS compatibility mode FPU exception support */
380 static qemu_irq ferr_irq
;
382 void pc_register_ferr_irq(qemu_irq irq
)
387 /* XXX: add IGNNE support */
388 void cpu_set_ferr(CPUX86State
*s
)
390 qemu_irq_raise(ferr_irq
);
393 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
396 qemu_irq_lower(ferr_irq
);
399 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
401 return 0xffffffffffffffffULL
;
405 uint64_t cpu_get_tsc(CPUX86State
*env
)
407 return cpu_get_ticks();
411 int cpu_get_pic_interrupt(CPUX86State
*env
)
413 X86CPU
*cpu
= x86_env_get_cpu(env
);
416 if (!kvm_irqchip_in_kernel()) {
417 intno
= apic_get_interrupt(cpu
->apic_state
);
421 /* read the irq from the PIC */
422 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
427 intno
= pic_read_irq(isa_pic
);
431 static void pic_irq_request(void *opaque
, int irq
, int level
)
433 CPUState
*cs
= first_cpu
;
434 X86CPU
*cpu
= X86_CPU(cs
);
436 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
437 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
440 if (apic_accept_pic_intr(cpu
->apic_state
)) {
441 apic_deliver_pic_intr(cpu
->apic_state
, level
);
446 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
448 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
453 /* PC cmos mappings */
455 #define REG_EQUIPMENT_BYTE 0x14
457 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
462 case FLOPPY_DRIVE_TYPE_144
:
463 /* 1.44 Mb 3"5 drive */
466 case FLOPPY_DRIVE_TYPE_288
:
467 /* 2.88 Mb 3"5 drive */
470 case FLOPPY_DRIVE_TYPE_120
:
471 /* 1.2 Mb 5"5 drive */
474 case FLOPPY_DRIVE_TYPE_NONE
:
482 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
483 int16_t cylinders
, int8_t heads
, int8_t sectors
)
485 rtc_set_memory(s
, type_ofs
, 47);
486 rtc_set_memory(s
, info_ofs
, cylinders
);
487 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
488 rtc_set_memory(s
, info_ofs
+ 2, heads
);
489 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
490 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
491 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
492 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
493 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
494 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
497 /* convert boot_device letter to something recognizable by the bios */
498 static int boot_device2nibble(char boot_device
)
500 switch(boot_device
) {
503 return 0x01; /* floppy boot */
505 return 0x02; /* hard drive boot */
507 return 0x03; /* CD-ROM boot */
509 return 0x04; /* Network boot */
514 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
516 #define PC_MAX_BOOT_DEVICES 3
517 int nbds
, bds
[3] = { 0, };
520 nbds
= strlen(boot_device
);
521 if (nbds
> PC_MAX_BOOT_DEVICES
) {
522 error_setg(errp
, "Too many boot devices for PC");
525 for (i
= 0; i
< nbds
; i
++) {
526 bds
[i
] = boot_device2nibble(boot_device
[i
]);
528 error_setg(errp
, "Invalid boot device for PC: '%c'",
533 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
534 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
537 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
539 set_boot_dev(opaque
, boot_device
, errp
);
542 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
545 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
546 FLOPPY_DRIVE_TYPE_NONE
};
550 for (i
= 0; i
< 2; i
++) {
551 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
554 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
555 cmos_get_fd_drive_type(fd_type
[1]);
556 rtc_set_memory(rtc_state
, 0x10, val
);
558 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
560 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
563 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
570 val
|= 0x01; /* 1 drive, ready for boot */
573 val
|= 0x41; /* 2 drives, ready for boot */
576 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
579 typedef struct pc_cmos_init_late_arg
{
580 ISADevice
*rtc_state
;
582 } pc_cmos_init_late_arg
;
584 typedef struct check_fdc_state
{
589 static int check_fdc(Object
*obj
, void *opaque
)
591 CheckFdcState
*state
= opaque
;
594 Error
*local_err
= NULL
;
596 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
601 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
602 if (local_err
|| iobase
!= 0x3f0) {
603 error_free(local_err
);
608 state
->multiple
= true;
610 state
->floppy
= ISA_DEVICE(obj
);
615 static const char * const fdc_container_path
[] = {
616 "/unattached", "/peripheral", "/peripheral-anon"
620 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
623 ISADevice
*pc_find_fdc0(void)
627 CheckFdcState state
= { 0 };
629 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
630 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
631 object_child_foreach(container
, check_fdc
, &state
);
634 if (state
.multiple
) {
635 warn_report("multiple floppy disk controllers with "
636 "iobase=0x3f0 have been found");
637 error_printf("the one being picked for CMOS setup might not reflect "
644 static void pc_cmos_init_late(void *opaque
)
646 pc_cmos_init_late_arg
*arg
= opaque
;
647 ISADevice
*s
= arg
->rtc_state
;
649 int8_t heads
, sectors
;
654 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
655 &cylinders
, &heads
, §ors
) >= 0) {
656 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
659 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
660 &cylinders
, &heads
, §ors
) >= 0) {
661 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
664 rtc_set_memory(s
, 0x12, val
);
667 for (i
= 0; i
< 4; i
++) {
668 /* NOTE: ide_get_geometry() returns the physical
669 geometry. It is always such that: 1 <= sects <= 63, 1
670 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
671 geometry can be different if a translation is done. */
672 if (arg
->idebus
[i
/ 2] &&
673 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
674 &cylinders
, &heads
, §ors
) >= 0) {
675 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
676 assert((trans
& ~3) == 0);
677 val
|= trans
<< (i
* 2);
680 rtc_set_memory(s
, 0x39, val
);
682 pc_cmos_init_floppy(s
, pc_find_fdc0());
684 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
687 void pc_cmos_init(PCMachineState
*pcms
,
688 BusState
*idebus0
, BusState
*idebus1
,
692 static pc_cmos_init_late_arg arg
;
694 /* various important CMOS locations needed by PC/Bochs bios */
697 /* base memory (first MiB) */
698 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
699 rtc_set_memory(s
, 0x15, val
);
700 rtc_set_memory(s
, 0x16, val
>> 8);
701 /* extended memory (next 64MiB) */
702 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
703 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
709 rtc_set_memory(s
, 0x17, val
);
710 rtc_set_memory(s
, 0x18, val
>> 8);
711 rtc_set_memory(s
, 0x30, val
);
712 rtc_set_memory(s
, 0x31, val
>> 8);
713 /* memory between 16MiB and 4GiB */
714 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
715 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
721 rtc_set_memory(s
, 0x34, val
);
722 rtc_set_memory(s
, 0x35, val
>> 8);
723 /* memory above 4GiB */
724 val
= pcms
->above_4g_mem_size
/ 65536;
725 rtc_set_memory(s
, 0x5b, val
);
726 rtc_set_memory(s
, 0x5c, val
>> 8);
727 rtc_set_memory(s
, 0x5d, val
>> 16);
729 object_property_add_link(OBJECT(pcms
), "rtc_state",
731 (Object
**)&pcms
->rtc
,
732 object_property_allow_set_link
,
733 OBJ_PROP_LINK_STRONG
, &error_abort
);
734 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
735 "rtc_state", &error_abort
);
737 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
740 val
|= 0x02; /* FPU is there */
741 val
|= 0x04; /* PS/2 mouse installed */
742 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
744 /* hard drives and FDC */
746 arg
.idebus
[0] = idebus0
;
747 arg
.idebus
[1] = idebus1
;
748 qemu_register_reset(pc_cmos_init_late
, &arg
);
751 #define TYPE_PORT92 "port92"
752 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
754 /* port 92 stuff: could be split off */
755 typedef struct Port92State
{
756 ISADevice parent_obj
;
763 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
766 Port92State
*s
= opaque
;
767 int oldval
= s
->outport
;
769 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
771 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
772 if ((val
& 1) && !(oldval
& 1)) {
773 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
777 static uint64_t port92_read(void *opaque
, hwaddr addr
,
780 Port92State
*s
= opaque
;
784 DPRINTF("port92: read 0x%02x\n", ret
);
788 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
790 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
793 static const VMStateDescription vmstate_port92_isa
= {
796 .minimum_version_id
= 1,
797 .fields
= (VMStateField
[]) {
798 VMSTATE_UINT8(outport
, Port92State
),
799 VMSTATE_END_OF_LIST()
803 static void port92_reset(DeviceState
*d
)
805 Port92State
*s
= PORT92(d
);
810 static const MemoryRegionOps port92_ops
= {
812 .write
= port92_write
,
814 .min_access_size
= 1,
815 .max_access_size
= 1,
817 .endianness
= DEVICE_LITTLE_ENDIAN
,
820 static void port92_initfn(Object
*obj
)
822 Port92State
*s
= PORT92(obj
);
824 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
828 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
831 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
833 ISADevice
*isadev
= ISA_DEVICE(dev
);
834 Port92State
*s
= PORT92(dev
);
836 isa_register_ioport(isadev
, &s
->io
, 0x92);
839 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
841 DeviceClass
*dc
= DEVICE_CLASS(klass
);
843 dc
->realize
= port92_realizefn
;
844 dc
->reset
= port92_reset
;
845 dc
->vmsd
= &vmstate_port92_isa
;
847 * Reason: unlike ordinary ISA devices, this one needs additional
848 * wiring: its A20 output line needs to be wired up by
851 dc
->user_creatable
= false;
854 static const TypeInfo port92_info
= {
856 .parent
= TYPE_ISA_DEVICE
,
857 .instance_size
= sizeof(Port92State
),
858 .instance_init
= port92_initfn
,
859 .class_init
= port92_class_initfn
,
862 static void port92_register_types(void)
864 type_register_static(&port92_info
);
867 type_init(port92_register_types
)
869 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
871 X86CPU
*cpu
= opaque
;
873 /* XXX: send to all CPUs ? */
874 /* XXX: add logic to handle multiple A20 line sources */
875 x86_cpu_set_a20(cpu
, level
);
878 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
880 int index
= le32_to_cpu(e820_reserve
.count
);
881 struct e820_entry
*entry
;
883 if (type
!= E820_RAM
) {
884 /* old FW_CFG_E820_TABLE entry -- reservations only */
885 if (index
>= E820_NR_ENTRIES
) {
888 entry
= &e820_reserve
.entry
[index
++];
890 entry
->address
= cpu_to_le64(address
);
891 entry
->length
= cpu_to_le64(length
);
892 entry
->type
= cpu_to_le32(type
);
894 e820_reserve
.count
= cpu_to_le32(index
);
897 /* new "etc/e820" file -- include ram too */
898 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
899 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
900 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
901 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
907 int e820_get_num_entries(void)
912 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
914 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
915 *address
= le64_to_cpu(e820_table
[idx
].address
);
916 *length
= le64_to_cpu(e820_table
[idx
].length
);
922 /* Enables contiguous-apic-ID mode, for compatibility */
923 static bool compat_apic_id_mode
;
925 void enable_compat_apic_id_mode(void)
927 compat_apic_id_mode
= true;
930 /* Calculates initial APIC ID for a specific CPU index
932 * Currently we need to be able to calculate the APIC ID from the CPU index
933 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
934 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
935 * all CPUs up to max_cpus.
937 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
942 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
943 if (compat_apic_id_mode
) {
944 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
945 error_report("APIC IDs set in compatibility mode, "
946 "CPU topology won't match the configuration");
955 static void pc_build_smbios(PCMachineState
*pcms
)
957 uint8_t *smbios_tables
, *smbios_anchor
;
958 size_t smbios_tables_len
, smbios_anchor_len
;
959 struct smbios_phys_mem_area
*mem_array
;
960 unsigned i
, array_count
;
961 MachineState
*ms
= MACHINE(pcms
);
962 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
964 /* tell smbios about cpuid version and features */
965 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
967 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
969 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
970 smbios_tables
, smbios_tables_len
);
973 /* build the array of physical mem area from e820 table */
974 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
975 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
978 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
979 mem_array
[array_count
].address
= addr
;
980 mem_array
[array_count
].length
= len
;
984 smbios_get_tables(mem_array
, array_count
,
985 &smbios_tables
, &smbios_tables_len
,
986 &smbios_anchor
, &smbios_anchor_len
);
990 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
991 smbios_tables
, smbios_tables_len
);
992 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
993 smbios_anchor
, smbios_anchor_len
);
997 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
1000 uint64_t *numa_fw_cfg
;
1002 const CPUArchIdList
*cpus
;
1003 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1005 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
1006 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1008 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1010 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1011 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1012 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1013 * for CPU hotplug also uses APIC ID and not "CPU index".
1014 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1015 * but the "limit to the APIC ID values SeaBIOS may see".
1017 * So for compatibility reasons with old BIOSes we are stuck with
1018 * "etc/max-cpus" actually being apic_id_limit
1020 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
1021 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1022 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
1023 acpi_tables
, acpi_tables_len
);
1024 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
1026 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
1027 &e820_reserve
, sizeof(e820_reserve
));
1028 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
1029 sizeof(struct e820_entry
) * e820_entries
);
1031 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
1032 /* allocate memory for the NUMA channel: one (64bit) word for the number
1033 * of nodes, one word for each VCPU->node and one word for each node to
1034 * hold the amount of memory.
1036 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
1037 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
1038 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
1039 for (i
= 0; i
< cpus
->len
; i
++) {
1040 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
1041 assert(apic_id
< pcms
->apic_id_limit
);
1042 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
1044 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1045 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
1046 cpu_to_le64(numa_info
[i
].node_mem
);
1048 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
1049 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
1050 sizeof(*numa_fw_cfg
));
1055 static long get_file_size(FILE *f
)
1059 /* XXX: on Unix systems, using fstat() probably makes more sense */
1062 fseek(f
, 0, SEEK_END
);
1064 fseek(f
, where
, SEEK_SET
);
1069 /* setup_data types */
1070 #define SETUP_NONE 0
1071 #define SETUP_E820_EXT 1
1081 } __attribute__((packed
));
1083 static void load_linux(PCMachineState
*pcms
,
1087 int setup_size
, kernel_size
, cmdline_size
;
1088 int dtb_size
, setup_data_offset
;
1089 uint32_t initrd_max
;
1090 uint8_t header
[8192], *setup
, *kernel
;
1091 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
1094 MachineState
*machine
= MACHINE(pcms
);
1095 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1096 struct setup_data
*setup_data
;
1097 const char *kernel_filename
= machine
->kernel_filename
;
1098 const char *initrd_filename
= machine
->initrd_filename
;
1099 const char *dtb_filename
= machine
->dtb
;
1100 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1102 /* Align to 16 bytes as a paranoia measure */
1103 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
1105 /* load the kernel header */
1106 f
= fopen(kernel_filename
, "rb");
1107 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
1108 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
1109 MIN(ARRAY_SIZE(header
), kernel_size
)) {
1110 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
1111 kernel_filename
, strerror(errno
));
1115 /* kernel protocol version */
1117 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
1119 if (ldl_p(header
+0x202) == 0x53726448) {
1120 protocol
= lduw_p(header
+0x206);
1122 /* This looks like a multiboot kernel. If it is, let's stop
1123 treating it like a Linux kernel. */
1124 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
1125 kernel_cmdline
, kernel_size
, header
)) {
1131 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
1133 real_addr
= 0x90000;
1134 cmdline_addr
= 0x9a000 - cmdline_size
;
1135 prot_addr
= 0x10000;
1136 } else if (protocol
< 0x202) {
1137 /* High but ancient kernel */
1138 real_addr
= 0x90000;
1139 cmdline_addr
= 0x9a000 - cmdline_size
;
1140 prot_addr
= 0x100000;
1142 /* High and recent kernel */
1143 real_addr
= 0x10000;
1144 cmdline_addr
= 0x20000;
1145 prot_addr
= 0x100000;
1150 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
1151 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
1152 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
1158 /* highest address for loading the initrd */
1159 if (protocol
>= 0x203) {
1160 initrd_max
= ldl_p(header
+0x22c);
1162 initrd_max
= 0x37ffffff;
1165 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
1166 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1169 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
1170 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
1171 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1173 if (protocol
>= 0x202) {
1174 stl_p(header
+0x228, cmdline_addr
);
1176 stw_p(header
+0x20, 0xA33F);
1177 stw_p(header
+0x22, cmdline_addr
-real_addr
);
1180 /* handle vga= parameter */
1181 vmode
= strstr(kernel_cmdline
, "vga=");
1183 unsigned int video_mode
;
1186 if (!strncmp(vmode
, "normal", 6)) {
1187 video_mode
= 0xffff;
1188 } else if (!strncmp(vmode
, "ext", 3)) {
1189 video_mode
= 0xfffe;
1190 } else if (!strncmp(vmode
, "ask", 3)) {
1191 video_mode
= 0xfffd;
1193 video_mode
= strtol(vmode
, NULL
, 0);
1195 stw_p(header
+0x1fa, video_mode
);
1199 /* High nybble = B reserved for QEMU; low nybble is revision number.
1200 If this code is substantially changed, you may want to consider
1201 incrementing the revision. */
1202 if (protocol
>= 0x200) {
1203 header
[0x210] = 0xB0;
1206 if (protocol
>= 0x201) {
1207 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
1208 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
1212 if (initrd_filename
) {
1215 GError
*gerr
= NULL
;
1217 if (protocol
< 0x200) {
1218 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1222 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1223 &initrd_size
, &gerr
)) {
1224 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1225 initrd_filename
, gerr
->message
);
1228 if (initrd_size
>= initrd_max
) {
1229 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1230 "(max: %"PRIu32
", need %"PRId64
")\n",
1231 initrd_max
, (uint64_t)initrd_size
);
1235 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1237 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1238 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1239 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1241 stl_p(header
+0x218, initrd_addr
);
1242 stl_p(header
+0x21c, initrd_size
);
1245 /* load kernel and setup */
1246 setup_size
= header
[0x1f1];
1247 if (setup_size
== 0) {
1250 setup_size
= (setup_size
+1)*512;
1251 if (setup_size
> kernel_size
) {
1252 fprintf(stderr
, "qemu: invalid kernel header\n");
1255 kernel_size
-= setup_size
;
1257 setup
= g_malloc(setup_size
);
1258 kernel
= g_malloc(kernel_size
);
1259 fseek(f
, 0, SEEK_SET
);
1260 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1261 fprintf(stderr
, "fread() failed\n");
1264 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1265 fprintf(stderr
, "fread() failed\n");
1270 /* append dtb to kernel */
1272 if (protocol
< 0x209) {
1273 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1277 dtb_size
= get_image_size(dtb_filename
);
1278 if (dtb_size
<= 0) {
1279 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1280 dtb_filename
, strerror(errno
));
1284 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1285 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1286 kernel
= g_realloc(kernel
, kernel_size
);
1288 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1290 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1291 setup_data
->next
= 0;
1292 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1293 setup_data
->len
= cpu_to_le32(dtb_size
);
1295 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1298 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1300 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1301 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1302 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1304 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1305 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1306 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1308 option_rom
[nb_option_roms
].bootindex
= 0;
1309 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1310 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1311 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1316 #define NE2000_NB_MAX 6
1318 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1320 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1322 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1324 static int nb_ne2k
= 0;
1326 if (nb_ne2k
== NE2000_NB_MAX
)
1328 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1329 ne2000_irq
[nb_ne2k
], nd
);
1333 DeviceState
*cpu_get_current_apic(void)
1336 X86CPU
*cpu
= X86_CPU(current_cpu
);
1337 return cpu
->apic_state
;
1343 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1345 X86CPU
*cpu
= opaque
;
1348 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1352 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1355 Error
*local_err
= NULL
;
1357 cpu
= object_new(typename
);
1359 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1360 object_property_set_bool(cpu
, true, "realized", &local_err
);
1363 error_propagate(errp
, local_err
);
1366 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1368 MachineState
*ms
= MACHINE(qdev_get_machine());
1369 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1370 Error
*local_err
= NULL
;
1373 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1377 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1378 error_setg(errp
, "Unable to add CPU: %" PRIi64
1379 ", resulting APIC ID (%" PRIi64
") is too large",
1384 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1386 error_propagate(errp
, local_err
);
1391 void pc_cpus_init(PCMachineState
*pcms
)
1394 const CPUArchIdList
*possible_cpus
;
1395 MachineState
*ms
= MACHINE(pcms
);
1396 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1398 /* Calculates the limit to CPU APIC ID values
1400 * Limit for the APIC ID value, so that all
1401 * CPU APIC IDs are < pcms->apic_id_limit.
1403 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1405 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1406 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1407 for (i
= 0; i
< smp_cpus
; i
++) {
1408 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1413 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1415 MachineState
*ms
= MACHINE(pcms
);
1416 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1417 CPUX86State
*env
= &cpu
->env
;
1418 uint32_t unused
, ecx
, edx
;
1419 uint64_t feature_control_bits
= 0;
1422 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1423 if (ecx
& CPUID_EXT_VMX
) {
1424 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1427 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1428 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1429 (env
->mcg_cap
& MCG_LMCE_P
)) {
1430 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1433 if (!feature_control_bits
) {
1437 val
= g_malloc(sizeof(*val
));
1438 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1439 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1442 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1444 if (cpus_count
> 0xff) {
1445 /* If the number of CPUs can't be represented in 8 bits, the
1446 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1447 * to make old BIOSes fail more predictably.
1449 rtc_set_memory(rtc
, 0x5f, 0);
1451 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1456 void pc_machine_done(Notifier
*notifier
, void *data
)
1458 PCMachineState
*pcms
= container_of(notifier
,
1459 PCMachineState
, machine_done
);
1460 PCIBus
*bus
= pcms
->bus
;
1462 /* set the number of CPUs */
1463 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1466 int extra_hosts
= 0;
1468 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1469 /* look for expander root buses */
1470 if (pci_bus_is_root(bus
)) {
1474 if (extra_hosts
&& pcms
->fw_cfg
) {
1475 uint64_t *val
= g_malloc(sizeof(*val
));
1476 *val
= cpu_to_le64(extra_hosts
);
1477 fw_cfg_add_file(pcms
->fw_cfg
,
1478 "etc/extra-pci-roots", val
, sizeof(*val
));
1484 pc_build_smbios(pcms
);
1485 pc_build_feature_control_file(pcms
);
1486 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1487 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1490 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1491 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1493 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1494 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1495 error_report("current -smp configuration requires "
1496 "Extended Interrupt Mode enabled. "
1497 "You can add an IOMMU using: "
1498 "-device intel-iommu,intremap=on,eim=on");
1504 void pc_guest_info_init(PCMachineState
*pcms
)
1508 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1509 pcms
->numa_nodes
= nb_numa_nodes
;
1510 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1511 sizeof *pcms
->node_mem
);
1512 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1513 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1516 pcms
->machine_done
.notify
= pc_machine_done
;
1517 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1520 /* setup pci memory address space mapping into system address space */
1521 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1522 MemoryRegion
*pci_address_space
)
1524 /* Set to lower priority than RAM */
1525 memory_region_add_subregion_overlap(system_memory
, 0x0,
1526 pci_address_space
, -1);
1529 void pc_acpi_init(const char *default_dsdt
)
1533 if (acpi_tables
!= NULL
) {
1534 /* manually set via -acpitable, leave it alone */
1538 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1539 if (filename
== NULL
) {
1540 warn_report("failed to find %s", default_dsdt
);
1542 QemuOpts
*opts
= qemu_opts_create(qemu_find_opts("acpi"), NULL
, 0,
1546 qemu_opt_set(opts
, "file", filename
, &error_abort
);
1548 acpi_table_add_builtin(opts
, &err
);
1550 warn_reportf_err(err
, "failed to load %s: ", filename
);
1556 void xen_load_linux(PCMachineState
*pcms
)
1561 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1563 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1564 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1567 load_linux(pcms
, fw_cfg
);
1568 for (i
= 0; i
< nb_option_roms
; i
++) {
1569 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1570 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1571 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1572 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1574 pcms
->fw_cfg
= fw_cfg
;
1577 void pc_memory_init(PCMachineState
*pcms
,
1578 MemoryRegion
*system_memory
,
1579 MemoryRegion
*rom_memory
,
1580 MemoryRegion
**ram_memory
)
1583 MemoryRegion
*ram
, *option_rom_mr
;
1584 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1586 MachineState
*machine
= MACHINE(pcms
);
1587 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1589 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1590 pcms
->above_4g_mem_size
);
1592 linux_boot
= (machine
->kernel_filename
!= NULL
);
1594 /* Allocate RAM. We allocate it as a single memory region and use
1595 * aliases to address portions of it, mostly for backwards compatibility
1596 * with older qemus that used qemu_ram_alloc().
1598 ram
= g_malloc(sizeof(*ram
));
1599 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1602 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1603 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1604 0, pcms
->below_4g_mem_size
);
1605 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1606 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1607 if (pcms
->above_4g_mem_size
> 0) {
1608 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1609 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1610 pcms
->below_4g_mem_size
,
1611 pcms
->above_4g_mem_size
);
1612 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1614 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1617 if (!pcmc
->has_reserved_memory
&&
1618 (machine
->ram_slots
||
1619 (machine
->maxram_size
> machine
->ram_size
))) {
1620 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1622 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1627 /* always allocate the device memory information */
1628 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1630 /* initialize device memory address space */
1631 if (pcmc
->has_reserved_memory
&&
1632 (machine
->ram_size
< machine
->maxram_size
)) {
1633 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1635 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1636 error_report("unsupported amount of memory slots: %"PRIu64
,
1637 machine
->ram_slots
);
1641 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1642 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1643 error_report("maximum memory size must by aligned to multiple of "
1644 "%d bytes", TARGET_PAGE_SIZE
);
1648 machine
->device_memory
->base
=
1649 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1651 if (pcmc
->enforce_aligned_dimm
) {
1652 /* size device region assuming 1G page max alignment per slot */
1653 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1656 if ((machine
->device_memory
->base
+ device_mem_size
) <
1658 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1659 machine
->maxram_size
);
1663 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1664 "device-memory", device_mem_size
);
1665 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1666 &machine
->device_memory
->mr
);
1669 /* Initialize PC system firmware */
1670 pc_system_firmware_init(rom_memory
, !pcmc
->pci_enabled
);
1672 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1673 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1675 if (pcmc
->pci_enabled
) {
1676 memory_region_set_readonly(option_rom_mr
, true);
1678 memory_region_add_subregion_overlap(rom_memory
,
1683 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1687 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1688 uint64_t *val
= g_malloc(sizeof(*val
));
1689 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1690 uint64_t res_mem_end
= machine
->device_memory
->base
;
1692 if (!pcmc
->broken_reserved_end
) {
1693 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1695 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1696 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1700 load_linux(pcms
, fw_cfg
);
1703 for (i
= 0; i
< nb_option_roms
; i
++) {
1704 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1706 pcms
->fw_cfg
= fw_cfg
;
1708 /* Init default IOAPIC address space */
1709 pcms
->ioapic_as
= &address_space_memory
;
1713 * The 64bit pci hole starts after "above 4G RAM" and
1714 * potentially the space reserved for memory hotplug.
1716 uint64_t pc_pci_hole64_start(void)
1718 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1719 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1720 MachineState
*ms
= MACHINE(pcms
);
1721 uint64_t hole64_start
= 0;
1723 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1724 hole64_start
= ms
->device_memory
->base
;
1725 if (!pcmc
->broken_reserved_end
) {
1726 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1729 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1732 return ROUND_UP(hole64_start
, 1 * GiB
);
1735 qemu_irq
pc_allocate_cpu_irq(void)
1737 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1740 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1742 DeviceState
*dev
= NULL
;
1744 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1746 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1747 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1748 } else if (isa_bus
) {
1749 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1750 dev
= isadev
? DEVICE(isadev
) : NULL
;
1752 rom_reset_order_override();
1756 static const MemoryRegionOps ioport80_io_ops
= {
1757 .write
= ioport80_write
,
1758 .read
= ioport80_read
,
1759 .endianness
= DEVICE_NATIVE_ENDIAN
,
1761 .min_access_size
= 1,
1762 .max_access_size
= 1,
1766 static const MemoryRegionOps ioportF0_io_ops
= {
1767 .write
= ioportF0_write
,
1768 .read
= ioportF0_read
,
1769 .endianness
= DEVICE_NATIVE_ENDIAN
,
1771 .min_access_size
= 1,
1772 .max_access_size
= 1,
1776 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
1779 DriveInfo
*fd
[MAX_FD
];
1781 ISADevice
*i8042
, *port92
, *vmmouse
;
1783 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1784 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1786 for (i
= 0; i
< MAX_FD
; i
++) {
1787 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1788 create_fdctrl
|= !!fd
[i
];
1790 if (create_fdctrl
) {
1791 fdctrl_init_isa(isa_bus
, fd
);
1794 i8042
= isa_create_simple(isa_bus
, "i8042");
1796 vmport_init(isa_bus
);
1797 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1802 DeviceState
*dev
= DEVICE(vmmouse
);
1803 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1804 qdev_init_nofail(dev
);
1806 port92
= isa_create_simple(isa_bus
, "port92");
1808 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1809 i8042_setup_a20_line(i8042
, a20_line
[0]);
1810 port92_init(port92
, a20_line
[1]);
1814 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1815 ISADevice
**rtc_state
,
1822 DeviceState
*hpet
= NULL
;
1823 int pit_isa_irq
= 0;
1824 qemu_irq pit_alt_irq
= NULL
;
1825 qemu_irq rtc_irq
= NULL
;
1826 ISADevice
*pit
= NULL
;
1827 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1828 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1830 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1831 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1833 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1834 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1837 * Check if an HPET shall be created.
1839 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1840 * when the HPET wants to take over. Thus we have to disable the latter.
1842 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1843 /* In order to set property, here not using sysbus_try_create_simple */
1844 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1846 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1847 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1850 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1853 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1855 qdev_init_nofail(hpet
);
1856 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1858 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1859 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1862 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1863 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1866 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
1868 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1870 if (!xen_enabled() && has_pit
) {
1871 if (kvm_pit_in_kernel()) {
1872 pit
= kvm_pit_init(isa_bus
, 0x40);
1874 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1877 /* connect PIT to output control line of the HPET */
1878 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1880 pcspk_init(isa_bus
, pit
);
1883 i8257_dma_init(isa_bus
, 0);
1886 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
1889 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1893 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1894 for (i
= 0; i
< nb_nics
; i
++) {
1895 NICInfo
*nd
= &nd_table
[i
];
1896 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1898 if (g_str_equal(model
, "ne2k_isa")) {
1899 pc_init_ne2k_isa(isa_bus
, nd
);
1901 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1904 rom_reset_order_override();
1907 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1913 if (kvm_ioapic_in_kernel()) {
1914 dev
= qdev_create(NULL
, "kvm-ioapic");
1916 dev
= qdev_create(NULL
, "ioapic");
1919 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1920 "ioapic", OBJECT(dev
), NULL
);
1922 qdev_init_nofail(dev
);
1923 d
= SYS_BUS_DEVICE(dev
);
1924 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1926 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1927 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1931 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1934 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1935 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1936 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1937 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
1940 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1941 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1942 * addition to cover this case.
1944 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1946 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1950 if (is_nvdimm
&& !pcms
->acpi_nvdimm_state
.is_enabled
) {
1951 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1955 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
1956 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
1959 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1960 DeviceState
*dev
, Error
**errp
)
1962 HotplugHandlerClass
*hhc
;
1963 Error
*local_err
= NULL
;
1964 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1965 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1967 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
1973 nvdimm_plug(&pcms
->acpi_nvdimm_state
);
1976 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1977 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
1979 error_propagate(errp
, local_err
);
1982 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1983 DeviceState
*dev
, Error
**errp
)
1985 HotplugHandlerClass
*hhc
;
1986 Error
*local_err
= NULL
;
1987 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1990 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1991 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1992 * addition to cover this case.
1994 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
1995 error_setg(&local_err
,
1996 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2000 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2001 error_setg(&local_err
,
2002 "nvdimm device hot unplug is not supported yet.");
2006 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2007 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2010 error_propagate(errp
, local_err
);
2013 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
2014 DeviceState
*dev
, Error
**errp
)
2016 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2017 HotplugHandlerClass
*hhc
;
2018 Error
*local_err
= NULL
;
2020 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2021 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2027 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
2028 object_unparent(OBJECT(dev
));
2031 error_propagate(errp
, local_err
);
2034 static int pc_apic_cmp(const void *a
, const void *b
)
2036 CPUArchId
*apic_a
= (CPUArchId
*)a
;
2037 CPUArchId
*apic_b
= (CPUArchId
*)b
;
2039 return apic_a
->arch_id
- apic_b
->arch_id
;
2042 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2043 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2044 * entry corresponding to CPU's apic_id returns NULL.
2046 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2048 CPUArchId apic_id
, *found_cpu
;
2050 apic_id
.arch_id
= id
;
2051 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
2052 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
2054 if (found_cpu
&& idx
) {
2055 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
2060 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
2061 DeviceState
*dev
, Error
**errp
)
2063 CPUArchId
*found_cpu
;
2064 HotplugHandlerClass
*hhc
;
2065 Error
*local_err
= NULL
;
2066 X86CPU
*cpu
= X86_CPU(dev
);
2067 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2069 if (pcms
->acpi_dev
) {
2070 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2071 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2077 /* increment the number of CPUs */
2080 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2083 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2086 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2087 found_cpu
->cpu
= OBJECT(dev
);
2089 error_propagate(errp
, local_err
);
2091 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2092 DeviceState
*dev
, Error
**errp
)
2095 HotplugHandlerClass
*hhc
;
2096 Error
*local_err
= NULL
;
2097 X86CPU
*cpu
= X86_CPU(dev
);
2098 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2100 if (!pcms
->acpi_dev
) {
2101 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
2105 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2108 error_setg(&local_err
, "Boot CPU is unpluggable");
2112 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2113 hhc
->unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2120 error_propagate(errp
, local_err
);
2124 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
2125 DeviceState
*dev
, Error
**errp
)
2127 CPUArchId
*found_cpu
;
2128 HotplugHandlerClass
*hhc
;
2129 Error
*local_err
= NULL
;
2130 X86CPU
*cpu
= X86_CPU(dev
);
2131 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2133 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
2134 hhc
->unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2140 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2141 found_cpu
->cpu
= NULL
;
2142 object_unparent(OBJECT(dev
));
2144 /* decrement the number of CPUs */
2146 /* Update the number of CPUs in CMOS */
2147 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2148 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2150 error_propagate(errp
, local_err
);
2153 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
2154 DeviceState
*dev
, Error
**errp
)
2158 CPUArchId
*cpu_slot
;
2159 X86CPUTopoInfo topo
;
2160 X86CPU
*cpu
= X86_CPU(dev
);
2161 MachineState
*ms
= MACHINE(hotplug_dev
);
2162 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2164 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
2165 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
2170 /* if APIC ID is not set, set it based on socket/core/thread properties */
2171 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
2172 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
2174 if (cpu
->socket_id
< 0) {
2175 error_setg(errp
, "CPU socket-id is not set");
2177 } else if (cpu
->socket_id
> max_socket
) {
2178 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
2179 cpu
->socket_id
, max_socket
);
2182 if (cpu
->core_id
< 0) {
2183 error_setg(errp
, "CPU core-id is not set");
2185 } else if (cpu
->core_id
> (smp_cores
- 1)) {
2186 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
2187 cpu
->core_id
, smp_cores
- 1);
2190 if (cpu
->thread_id
< 0) {
2191 error_setg(errp
, "CPU thread-id is not set");
2193 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
2194 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
2195 cpu
->thread_id
, smp_threads
- 1);
2199 topo
.pkg_id
= cpu
->socket_id
;
2200 topo
.core_id
= cpu
->core_id
;
2201 topo
.smt_id
= cpu
->thread_id
;
2202 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
2205 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2207 MachineState
*ms
= MACHINE(pcms
);
2209 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2210 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2211 " APIC ID %" PRIu32
", valid index range 0:%d",
2212 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
2213 ms
->possible_cpus
->len
- 1);
2217 if (cpu_slot
->cpu
) {
2218 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2223 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2224 * so that machine_query_hotpluggable_cpus would show correct values
2226 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2227 * once -smp refactoring is complete and there will be CPU private
2228 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2229 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2230 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2231 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2232 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2235 cpu
->socket_id
= topo
.pkg_id
;
2237 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2238 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2239 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2242 cpu
->core_id
= topo
.core_id
;
2244 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2245 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2246 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2249 cpu
->thread_id
= topo
.smt_id
;
2251 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2252 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2257 cs
->cpu_index
= idx
;
2259 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2262 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2263 DeviceState
*dev
, Error
**errp
)
2265 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2266 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2267 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2268 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2272 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2273 DeviceState
*dev
, Error
**errp
)
2275 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2276 pc_memory_plug(hotplug_dev
, dev
, errp
);
2277 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2278 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2282 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2283 DeviceState
*dev
, Error
**errp
)
2285 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2286 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2287 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2288 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2290 error_setg(errp
, "acpi: device unplug request for not supported device"
2291 " type: %s", object_get_typename(OBJECT(dev
)));
2295 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2296 DeviceState
*dev
, Error
**errp
)
2298 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2299 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2300 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2301 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2303 error_setg(errp
, "acpi: device unplug for not supported device"
2304 " type: %s", object_get_typename(OBJECT(dev
)));
2308 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
2311 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2312 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2313 return HOTPLUG_HANDLER(machine
);
2320 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2321 const char *name
, void *opaque
,
2324 MachineState
*ms
= MACHINE(obj
);
2325 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2327 visit_type_int(v
, name
, &value
, errp
);
2330 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2331 const char *name
, void *opaque
,
2334 PCMachineState
*pcms
= PC_MACHINE(obj
);
2335 uint64_t value
= pcms
->max_ram_below_4g
;
2337 visit_type_size(v
, name
, &value
, errp
);
2340 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2341 const char *name
, void *opaque
,
2344 PCMachineState
*pcms
= PC_MACHINE(obj
);
2345 Error
*error
= NULL
;
2348 visit_type_size(v
, name
, &value
, &error
);
2350 error_propagate(errp
, error
);
2353 if (value
> 4 * GiB
) {
2355 "Machine option 'max-ram-below-4g=%"PRIu64
2356 "' expects size less than or equal to 4G", value
);
2357 error_propagate(errp
, error
);
2361 if (value
< 1 * MiB
) {
2362 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2363 "BIOS may not work with less than 1MiB", value
);
2366 pcms
->max_ram_below_4g
= value
;
2369 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2370 void *opaque
, Error
**errp
)
2372 PCMachineState
*pcms
= PC_MACHINE(obj
);
2373 OnOffAuto vmport
= pcms
->vmport
;
2375 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2378 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2379 void *opaque
, Error
**errp
)
2381 PCMachineState
*pcms
= PC_MACHINE(obj
);
2383 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2386 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2388 bool smm_available
= false;
2390 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2394 if (tcg_enabled() || qtest_enabled()) {
2395 smm_available
= true;
2396 } else if (kvm_enabled()) {
2397 smm_available
= kvm_has_smm();
2400 if (smm_available
) {
2404 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2405 error_report("System Management Mode not supported by this hypervisor.");
2411 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2412 void *opaque
, Error
**errp
)
2414 PCMachineState
*pcms
= PC_MACHINE(obj
);
2415 OnOffAuto smm
= pcms
->smm
;
2417 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2420 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2421 void *opaque
, Error
**errp
)
2423 PCMachineState
*pcms
= PC_MACHINE(obj
);
2425 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2428 static bool pc_machine_get_nvdimm(Object
*obj
, Error
**errp
)
2430 PCMachineState
*pcms
= PC_MACHINE(obj
);
2432 return pcms
->acpi_nvdimm_state
.is_enabled
;
2435 static void pc_machine_set_nvdimm(Object
*obj
, bool value
, Error
**errp
)
2437 PCMachineState
*pcms
= PC_MACHINE(obj
);
2439 pcms
->acpi_nvdimm_state
.is_enabled
= value
;
2442 static char *pc_machine_get_nvdimm_persistence(Object
*obj
, Error
**errp
)
2444 PCMachineState
*pcms
= PC_MACHINE(obj
);
2446 return g_strdup(pcms
->acpi_nvdimm_state
.persistence_string
);
2449 static void pc_machine_set_nvdimm_persistence(Object
*obj
, const char *value
,
2452 PCMachineState
*pcms
= PC_MACHINE(obj
);
2453 AcpiNVDIMMState
*nvdimm_state
= &pcms
->acpi_nvdimm_state
;
2455 if (strcmp(value
, "cpu") == 0)
2456 nvdimm_state
->persistence
= 3;
2457 else if (strcmp(value
, "mem-ctrl") == 0)
2458 nvdimm_state
->persistence
= 2;
2460 error_setg(errp
, "-machine nvdimm-persistence=%s: unsupported option",
2465 g_free(nvdimm_state
->persistence_string
);
2466 nvdimm_state
->persistence_string
= g_strdup(value
);
2469 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2471 PCMachineState
*pcms
= PC_MACHINE(obj
);
2473 return pcms
->smbus_enabled
;
2476 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2478 PCMachineState
*pcms
= PC_MACHINE(obj
);
2480 pcms
->smbus_enabled
= value
;
2483 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2485 PCMachineState
*pcms
= PC_MACHINE(obj
);
2487 return pcms
->sata_enabled
;
2490 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2492 PCMachineState
*pcms
= PC_MACHINE(obj
);
2494 pcms
->sata_enabled
= value
;
2497 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2499 PCMachineState
*pcms
= PC_MACHINE(obj
);
2501 return pcms
->pit_enabled
;
2504 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2506 PCMachineState
*pcms
= PC_MACHINE(obj
);
2508 pcms
->pit_enabled
= value
;
2511 static void pc_machine_initfn(Object
*obj
)
2513 PCMachineState
*pcms
= PC_MACHINE(obj
);
2515 pcms
->max_ram_below_4g
= 0; /* use default */
2516 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2517 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2518 /* nvdimm is disabled on default. */
2519 pcms
->acpi_nvdimm_state
.is_enabled
= false;
2520 /* acpi build is enabled by default if machine supports it */
2521 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2522 pcms
->smbus_enabled
= true;
2523 pcms
->sata_enabled
= true;
2524 pcms
->pit_enabled
= true;
2527 static void pc_machine_reset(void)
2532 qemu_devices_reset();
2534 /* Reset APIC after devices have been reset to cancel
2535 * any changes that qemu_devices_reset() might have done.
2540 if (cpu
->apic_state
) {
2541 device_reset(cpu
->apic_state
);
2546 static CpuInstanceProperties
2547 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2549 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2550 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2552 assert(cpu_index
< possible_cpus
->len
);
2553 return possible_cpus
->cpus
[cpu_index
].props
;
2556 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2558 X86CPUTopoInfo topo
;
2560 assert(idx
< ms
->possible_cpus
->len
);
2561 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2562 smp_cores
, smp_threads
, &topo
);
2563 return topo
.pkg_id
% nb_numa_nodes
;
2566 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2570 if (ms
->possible_cpus
) {
2572 * make sure that max_cpus hasn't changed since the first use, i.e.
2573 * -smp hasn't been parsed after it
2575 assert(ms
->possible_cpus
->len
== max_cpus
);
2576 return ms
->possible_cpus
;
2579 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2580 sizeof(CPUArchId
) * max_cpus
);
2581 ms
->possible_cpus
->len
= max_cpus
;
2582 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2583 X86CPUTopoInfo topo
;
2585 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2586 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2587 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2588 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2589 smp_cores
, smp_threads
, &topo
);
2590 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2591 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2592 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2593 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2594 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2595 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2597 return ms
->possible_cpus
;
2600 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2602 /* cpu index isn't used */
2606 X86CPU
*cpu
= X86_CPU(cs
);
2608 if (!cpu
->apic_state
) {
2609 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2611 apic_deliver_nmi(cpu
->apic_state
);
2616 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2618 MachineClass
*mc
= MACHINE_CLASS(oc
);
2619 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2620 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2621 NMIClass
*nc
= NMI_CLASS(oc
);
2623 pcmc
->pci_enabled
= true;
2624 pcmc
->has_acpi_build
= true;
2625 pcmc
->rsdp_in_ram
= true;
2626 pcmc
->smbios_defaults
= true;
2627 pcmc
->smbios_uuid_encoded
= true;
2628 pcmc
->gigabyte_align
= true;
2629 pcmc
->has_reserved_memory
= true;
2630 pcmc
->kvmclock_enabled
= true;
2631 pcmc
->enforce_aligned_dimm
= true;
2632 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2633 * to be used at the moment, 32K should be enough for a while. */
2634 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2635 pcmc
->save_tsc_khz
= true;
2636 pcmc
->linuxboot_dma_enabled
= true;
2637 assert(!mc
->get_hotplug_handler
);
2638 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
2639 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2640 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2641 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2642 mc
->auto_enable_numa_with_memhp
= true;
2643 mc
->has_hotpluggable_cpus
= true;
2644 mc
->default_boot_order
= "cad";
2645 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2646 mc
->block_default_type
= IF_IDE
;
2648 mc
->reset
= pc_machine_reset
;
2649 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2650 hc
->plug
= pc_machine_device_plug_cb
;
2651 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2652 hc
->unplug
= pc_machine_device_unplug_cb
;
2653 nc
->nmi_monitor_handler
= x86_nmi
;
2654 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2656 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2657 pc_machine_get_device_memory_region_size
, NULL
,
2658 NULL
, NULL
, &error_abort
);
2660 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2661 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2662 NULL
, NULL
, &error_abort
);
2664 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2665 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2667 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2668 pc_machine_get_smm
, pc_machine_set_smm
,
2669 NULL
, NULL
, &error_abort
);
2670 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2671 "Enable SMM (pc & q35)", &error_abort
);
2673 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2674 pc_machine_get_vmport
, pc_machine_set_vmport
,
2675 NULL
, NULL
, &error_abort
);
2676 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2677 "Enable vmport (pc & q35)", &error_abort
);
2679 object_class_property_add_bool(oc
, PC_MACHINE_NVDIMM
,
2680 pc_machine_get_nvdimm
, pc_machine_set_nvdimm
, &error_abort
);
2682 object_class_property_add_str(oc
, PC_MACHINE_NVDIMM_PERSIST
,
2683 pc_machine_get_nvdimm_persistence
,
2684 pc_machine_set_nvdimm_persistence
, &error_abort
);
2686 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2687 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2689 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2690 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2692 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2693 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2696 static const TypeInfo pc_machine_info
= {
2697 .name
= TYPE_PC_MACHINE
,
2698 .parent
= TYPE_MACHINE
,
2700 .instance_size
= sizeof(PCMachineState
),
2701 .instance_init
= pc_machine_initfn
,
2702 .class_size
= sizeof(PCMachineClass
),
2703 .class_init
= pc_machine_class_init
,
2704 .interfaces
= (InterfaceInfo
[]) {
2705 { TYPE_HOTPLUG_HANDLER
},
2711 static void pc_machine_register_types(void)
2713 type_register_static(&pc_machine_info
);
2716 type_init(pc_machine_register_types
)