2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/fw_cfg.h"
31 #include "hw/i386/vmport.h"
32 #include "sysemu/cpus.h"
33 #include "hw/ide/internal.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/loader.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/intc/i8259.h"
38 #include "hw/timer/i8254.h"
39 #include "hw/input/i8042.h"
40 #include "hw/audio/pcspk.h"
41 #include "sysemu/sysemu.h"
42 #include "sysemu/xen.h"
43 #include "sysemu/reset.h"
44 #include "kvm/kvm_i386.h"
45 #include "hw/xen/xen.h"
46 #include "qemu/error-report.h"
47 #include "hw/acpi/cpu_hotplug.h"
48 #include "acpi-build.h"
49 #include "hw/mem/nvdimm.h"
50 #include "hw/cxl/cxl_host.h"
52 #include "hw/i386/intel_iommu.h"
53 #include "hw/net/ne2000-isa.h"
54 #include "hw/virtio/virtio-iommu.h"
55 #include "hw/virtio/virtio-md-pci.h"
56 #include "hw/i386/kvm/xen_overlay.h"
57 #include "hw/i386/kvm/xen_evtchn.h"
58 #include "hw/i386/kvm/xen_gnttab.h"
59 #include "hw/i386/kvm/xen_xenstore.h"
60 #include "e820_memory_layout.h"
62 #include CONFIG_DEVICES
65 #include "hw/xen/xen-legacy-backend.h"
66 #include "hw/xen/xen-bus.h"
70 * Helper for setting model-id for CPU models that changed model-id
71 * depending on QEMU versions up to QEMU 2.4.
73 #define PC_CPU_MODEL_IDS(v) \
74 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
75 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
76 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
78 GlobalProperty pc_compat_8_1
[] = {};
79 const size_t pc_compat_8_1_len
= G_N_ELEMENTS(pc_compat_8_1
);
81 GlobalProperty pc_compat_8_0
[] = {
82 { "virtio-mem", "unplugged-inaccessible", "auto" },
84 const size_t pc_compat_8_0_len
= G_N_ELEMENTS(pc_compat_8_0
);
86 GlobalProperty pc_compat_7_2
[] = {
87 { "ICH9-LPC", "noreboot", "true" },
89 const size_t pc_compat_7_2_len
= G_N_ELEMENTS(pc_compat_7_2
);
91 GlobalProperty pc_compat_7_1
[] = {};
92 const size_t pc_compat_7_1_len
= G_N_ELEMENTS(pc_compat_7_1
);
94 GlobalProperty pc_compat_7_0
[] = {};
95 const size_t pc_compat_7_0_len
= G_N_ELEMENTS(pc_compat_7_0
);
97 GlobalProperty pc_compat_6_2
[] = {
98 { "virtio-mem", "unplugged-inaccessible", "off" },
100 const size_t pc_compat_6_2_len
= G_N_ELEMENTS(pc_compat_6_2
);
102 GlobalProperty pc_compat_6_1
[] = {
103 { TYPE_X86_CPU
, "hv-version-id-build", "0x1bbc" },
104 { TYPE_X86_CPU
, "hv-version-id-major", "0x0006" },
105 { TYPE_X86_CPU
, "hv-version-id-minor", "0x0001" },
106 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
108 const size_t pc_compat_6_1_len
= G_N_ELEMENTS(pc_compat_6_1
);
110 GlobalProperty pc_compat_6_0
[] = {
111 { "qemu64" "-" TYPE_X86_CPU
, "family", "6" },
112 { "qemu64" "-" TYPE_X86_CPU
, "model", "6" },
113 { "qemu64" "-" TYPE_X86_CPU
, "stepping", "3" },
114 { TYPE_X86_CPU
, "x-vendor-cpuid-only", "off" },
115 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE
, "off" },
116 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
118 const size_t pc_compat_6_0_len
= G_N_ELEMENTS(pc_compat_6_0
);
120 GlobalProperty pc_compat_5_2
[] = {
121 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
123 const size_t pc_compat_5_2_len
= G_N_ELEMENTS(pc_compat_5_2
);
125 GlobalProperty pc_compat_5_1
[] = {
126 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
127 { TYPE_X86_CPU
, "kvm-msi-ext-dest-id", "off" },
129 const size_t pc_compat_5_1_len
= G_N_ELEMENTS(pc_compat_5_1
);
131 GlobalProperty pc_compat_5_0
[] = {
133 const size_t pc_compat_5_0_len
= G_N_ELEMENTS(pc_compat_5_0
);
135 GlobalProperty pc_compat_4_2
[] = {
136 { "mch", "smbase-smram", "off" },
138 const size_t pc_compat_4_2_len
= G_N_ELEMENTS(pc_compat_4_2
);
140 GlobalProperty pc_compat_4_1
[] = {};
141 const size_t pc_compat_4_1_len
= G_N_ELEMENTS(pc_compat_4_1
);
143 GlobalProperty pc_compat_4_0
[] = {};
144 const size_t pc_compat_4_0_len
= G_N_ELEMENTS(pc_compat_4_0
);
146 GlobalProperty pc_compat_3_1
[] = {
147 { "intel-iommu", "dma-drain", "off" },
148 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "off" },
149 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "off" },
150 { "Opteron_G4" "-" TYPE_X86_CPU
, "npt", "off" },
151 { "Opteron_G4" "-" TYPE_X86_CPU
, "nrip-save", "off" },
152 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "off" },
153 { "Opteron_G5" "-" TYPE_X86_CPU
, "npt", "off" },
154 { "Opteron_G5" "-" TYPE_X86_CPU
, "nrip-save", "off" },
155 { "EPYC" "-" TYPE_X86_CPU
, "npt", "off" },
156 { "EPYC" "-" TYPE_X86_CPU
, "nrip-save", "off" },
157 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "npt", "off" },
158 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "nrip-save", "off" },
159 { "Skylake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
160 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
161 { "Skylake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
162 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
163 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
164 { "Icelake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
165 { "Icelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
166 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "stepping", "5" },
167 { TYPE_X86_CPU
, "x-intel-pt-auto-level", "off" },
169 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
171 GlobalProperty pc_compat_3_0
[] = {
172 { TYPE_X86_CPU
, "x-hv-synic-kvm-only", "on" },
173 { "Skylake-Server" "-" TYPE_X86_CPU
, "pku", "off" },
174 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "pku", "off" },
176 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
178 GlobalProperty pc_compat_2_12
[] = {
179 { TYPE_X86_CPU
, "legacy-cache", "on" },
180 { TYPE_X86_CPU
, "topoext", "off" },
181 { "EPYC-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
182 { "EPYC-IBPB-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
184 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
186 GlobalProperty pc_compat_2_11
[] = {
187 { TYPE_X86_CPU
, "x-migrate-smi-count", "off" },
188 { "Skylake-Server" "-" TYPE_X86_CPU
, "clflushopt", "off" },
190 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
192 GlobalProperty pc_compat_2_10
[] = {
193 { TYPE_X86_CPU
, "x-hv-max-vps", "0x40" },
194 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
195 { "q35-pcihost", "x-pci-hole64-fix", "off" },
197 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
199 GlobalProperty pc_compat_2_9
[] = {
200 { "mch", "extended-tseg-mbytes", "0" },
202 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
204 GlobalProperty pc_compat_2_8
[] = {
205 { TYPE_X86_CPU
, "tcg-cpuid", "off" },
206 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
207 { "ICH9-LPC", "x-smi-broadcast", "off" },
208 { TYPE_X86_CPU
, "vmware-cpuid-freq", "off" },
209 { "Haswell-" TYPE_X86_CPU
, "stepping", "1" },
211 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
213 GlobalProperty pc_compat_2_7
[] = {
214 { TYPE_X86_CPU
, "l3-cache", "off" },
215 { TYPE_X86_CPU
, "full-cpuid-auto-level", "off" },
216 { "Opteron_G3" "-" TYPE_X86_CPU
, "family", "15" },
217 { "Opteron_G3" "-" TYPE_X86_CPU
, "model", "6" },
218 { "Opteron_G3" "-" TYPE_X86_CPU
, "stepping", "1" },
219 { "isa-pcspk", "migrate", "off" },
221 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
223 GlobalProperty pc_compat_2_6
[] = {
224 { TYPE_X86_CPU
, "cpuid-0xb", "off" },
225 { "vmxnet3", "romfile", "" },
226 { TYPE_X86_CPU
, "fill-mtrr-mask", "off" },
227 { "apic-common", "legacy-instance-id", "on", }
229 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
231 GlobalProperty pc_compat_2_5
[] = {};
232 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
234 GlobalProperty pc_compat_2_4
[] = {
235 PC_CPU_MODEL_IDS("2.4.0")
236 { "Haswell-" TYPE_X86_CPU
, "abm", "off" },
237 { "Haswell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
238 { "Broadwell-" TYPE_X86_CPU
, "abm", "off" },
239 { "Broadwell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
240 { "host" "-" TYPE_X86_CPU
, "host-cache-info", "on" },
241 { TYPE_X86_CPU
, "check", "off" },
242 { "qemu64" "-" TYPE_X86_CPU
, "sse4a", "on" },
243 { "qemu64" "-" TYPE_X86_CPU
, "abm", "on" },
244 { "qemu64" "-" TYPE_X86_CPU
, "popcnt", "on" },
245 { "qemu32" "-" TYPE_X86_CPU
, "popcnt", "on" },
246 { "Opteron_G2" "-" TYPE_X86_CPU
, "rdtscp", "on" },
247 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "on" },
248 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "on" },
249 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "on", }
251 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
253 GlobalProperty pc_compat_2_3
[] = {
254 PC_CPU_MODEL_IDS("2.3.0")
255 { TYPE_X86_CPU
, "arat", "off" },
256 { "qemu64" "-" TYPE_X86_CPU
, "min-level", "4" },
257 { "kvm64" "-" TYPE_X86_CPU
, "min-level", "5" },
258 { "pentium3" "-" TYPE_X86_CPU
, "min-level", "2" },
259 { "n270" "-" TYPE_X86_CPU
, "min-level", "5" },
260 { "Conroe" "-" TYPE_X86_CPU
, "min-level", "4" },
261 { "Penryn" "-" TYPE_X86_CPU
, "min-level", "4" },
262 { "Nehalem" "-" TYPE_X86_CPU
, "min-level", "4" },
263 { "n270" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
264 { "Penryn" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
265 { "Conroe" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
266 { "Nehalem" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
267 { "Westmere" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
268 { "SandyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
269 { "IvyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
270 { "Haswell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
271 { "Haswell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
272 { "Broadwell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
273 { "Broadwell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
274 { TYPE_X86_CPU
, "kvm-no-smi-migration", "on" },
276 const size_t pc_compat_2_3_len
= G_N_ELEMENTS(pc_compat_2_3
);
278 GlobalProperty pc_compat_2_2
[] = {
279 PC_CPU_MODEL_IDS("2.2.0")
280 { "kvm64" "-" TYPE_X86_CPU
, "vme", "off" },
281 { "kvm32" "-" TYPE_X86_CPU
, "vme", "off" },
282 { "Conroe" "-" TYPE_X86_CPU
, "vme", "off" },
283 { "Penryn" "-" TYPE_X86_CPU
, "vme", "off" },
284 { "Nehalem" "-" TYPE_X86_CPU
, "vme", "off" },
285 { "Westmere" "-" TYPE_X86_CPU
, "vme", "off" },
286 { "SandyBridge" "-" TYPE_X86_CPU
, "vme", "off" },
287 { "Haswell" "-" TYPE_X86_CPU
, "vme", "off" },
288 { "Broadwell" "-" TYPE_X86_CPU
, "vme", "off" },
289 { "Opteron_G1" "-" TYPE_X86_CPU
, "vme", "off" },
290 { "Opteron_G2" "-" TYPE_X86_CPU
, "vme", "off" },
291 { "Opteron_G3" "-" TYPE_X86_CPU
, "vme", "off" },
292 { "Opteron_G4" "-" TYPE_X86_CPU
, "vme", "off" },
293 { "Opteron_G5" "-" TYPE_X86_CPU
, "vme", "off" },
294 { "Haswell" "-" TYPE_X86_CPU
, "f16c", "off" },
295 { "Haswell" "-" TYPE_X86_CPU
, "rdrand", "off" },
296 { "Broadwell" "-" TYPE_X86_CPU
, "f16c", "off" },
297 { "Broadwell" "-" TYPE_X86_CPU
, "rdrand", "off" },
299 const size_t pc_compat_2_2_len
= G_N_ELEMENTS(pc_compat_2_2
);
301 GlobalProperty pc_compat_2_1
[] = {
302 PC_CPU_MODEL_IDS("2.1.0")
303 { "coreduo" "-" TYPE_X86_CPU
, "vmx", "on" },
304 { "core2duo" "-" TYPE_X86_CPU
, "vmx", "on" },
306 const size_t pc_compat_2_1_len
= G_N_ELEMENTS(pc_compat_2_1
);
308 GlobalProperty pc_compat_2_0
[] = {
309 PC_CPU_MODEL_IDS("2.0.0")
310 { "virtio-scsi-pci", "any_layout", "off" },
311 { "PIIX4_PM", "memory-hotplug-support", "off" },
312 { "apic", "version", "0x11" },
313 { "nec-usb-xhci", "superspeed-ports-first", "off" },
314 { "nec-usb-xhci", "force-pcie-endcap", "on" },
315 { "pci-serial", "prog_if", "0" },
316 { "pci-serial-2x", "prog_if", "0" },
317 { "pci-serial-4x", "prog_if", "0" },
318 { "virtio-net-pci", "guest_announce", "off" },
319 { "ICH9-LPC", "memory-hotplug-support", "off" },
321 const size_t pc_compat_2_0_len
= G_N_ELEMENTS(pc_compat_2_0
);
323 GSIState
*pc_gsi_create(qemu_irq
**irqs
, bool pci_enabled
)
327 s
= g_new0(GSIState
, 1);
328 if (kvm_ioapic_in_kernel()) {
329 kvm_pc_setup_irq_routing(pci_enabled
);
331 *irqs
= qemu_allocate_irqs(gsi_handler
, s
, IOAPIC_NUM_PINS
);
336 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
341 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
343 return 0xffffffffffffffffULL
;
346 /* MS-DOS compatibility mode FPU exception support */
347 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
355 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
357 return 0xffffffffffffffffULL
;
360 /* PC cmos mappings */
362 #define REG_EQUIPMENT_BYTE 0x14
364 static void cmos_init_hd(MC146818RtcState
*s
, int type_ofs
, int info_ofs
,
365 int16_t cylinders
, int8_t heads
, int8_t sectors
)
367 mc146818rtc_set_cmos_data(s
, type_ofs
, 47);
368 mc146818rtc_set_cmos_data(s
, info_ofs
, cylinders
);
369 mc146818rtc_set_cmos_data(s
, info_ofs
+ 1, cylinders
>> 8);
370 mc146818rtc_set_cmos_data(s
, info_ofs
+ 2, heads
);
371 mc146818rtc_set_cmos_data(s
, info_ofs
+ 3, 0xff);
372 mc146818rtc_set_cmos_data(s
, info_ofs
+ 4, 0xff);
373 mc146818rtc_set_cmos_data(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
374 mc146818rtc_set_cmos_data(s
, info_ofs
+ 6, cylinders
);
375 mc146818rtc_set_cmos_data(s
, info_ofs
+ 7, cylinders
>> 8);
376 mc146818rtc_set_cmos_data(s
, info_ofs
+ 8, sectors
);
379 /* convert boot_device letter to something recognizable by the bios */
380 static int boot_device2nibble(char boot_device
)
382 switch(boot_device
) {
385 return 0x01; /* floppy boot */
387 return 0x02; /* hard drive boot */
389 return 0x03; /* CD-ROM boot */
391 return 0x04; /* Network boot */
396 static void set_boot_dev(MC146818RtcState
*s
, const char *boot_device
,
399 #define PC_MAX_BOOT_DEVICES 3
400 int nbds
, bds
[3] = { 0, };
403 nbds
= strlen(boot_device
);
404 if (nbds
> PC_MAX_BOOT_DEVICES
) {
405 error_setg(errp
, "Too many boot devices for PC");
408 for (i
= 0; i
< nbds
; i
++) {
409 bds
[i
] = boot_device2nibble(boot_device
[i
]);
411 error_setg(errp
, "Invalid boot device for PC: '%c'",
416 mc146818rtc_set_cmos_data(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
417 mc146818rtc_set_cmos_data(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
420 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
422 set_boot_dev(opaque
, boot_device
, errp
);
425 static void pc_cmos_init_floppy(MC146818RtcState
*rtc_state
, ISADevice
*floppy
)
428 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
429 FLOPPY_DRIVE_TYPE_NONE
};
433 for (i
= 0; i
< 2; i
++) {
434 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
437 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
438 cmos_get_fd_drive_type(fd_type
[1]);
439 mc146818rtc_set_cmos_data(rtc_state
, 0x10, val
);
441 val
= mc146818rtc_get_cmos_data(rtc_state
, REG_EQUIPMENT_BYTE
);
443 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
446 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
453 val
|= 0x01; /* 1 drive, ready for boot */
456 val
|= 0x41; /* 2 drives, ready for boot */
459 mc146818rtc_set_cmos_data(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
462 typedef struct pc_cmos_init_late_arg
{
463 MC146818RtcState
*rtc_state
;
465 } pc_cmos_init_late_arg
;
467 typedef struct check_fdc_state
{
472 static int check_fdc(Object
*obj
, void *opaque
)
474 CheckFdcState
*state
= opaque
;
477 Error
*local_err
= NULL
;
479 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
484 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
485 if (local_err
|| iobase
!= 0x3f0) {
486 error_free(local_err
);
491 state
->multiple
= true;
493 state
->floppy
= ISA_DEVICE(obj
);
498 static const char * const fdc_container_path
[] = {
499 "/unattached", "/peripheral", "/peripheral-anon"
503 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
506 static ISADevice
*pc_find_fdc0(void)
510 CheckFdcState state
= { 0 };
512 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
513 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
514 object_child_foreach(container
, check_fdc
, &state
);
517 if (state
.multiple
) {
518 warn_report("multiple floppy disk controllers with "
519 "iobase=0x3f0 have been found");
520 error_printf("the one being picked for CMOS setup might not reflect "
527 static void pc_cmos_init_late(void *opaque
)
529 pc_cmos_init_late_arg
*arg
= opaque
;
530 MC146818RtcState
*s
= arg
->rtc_state
;
532 int8_t heads
, sectors
;
537 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
538 &cylinders
, &heads
, §ors
) >= 0) {
539 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
542 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
543 &cylinders
, &heads
, §ors
) >= 0) {
544 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
547 mc146818rtc_set_cmos_data(s
, 0x12, val
);
550 for (i
= 0; i
< 4; i
++) {
551 /* NOTE: ide_get_geometry() returns the physical
552 geometry. It is always such that: 1 <= sects <= 63, 1
553 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
554 geometry can be different if a translation is done. */
555 if (arg
->idebus
[i
/ 2] &&
556 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
557 &cylinders
, &heads
, §ors
) >= 0) {
558 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
559 assert((trans
& ~3) == 0);
560 val
|= trans
<< (i
* 2);
563 mc146818rtc_set_cmos_data(s
, 0x39, val
);
565 pc_cmos_init_floppy(s
, pc_find_fdc0());
567 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
570 void pc_cmos_init(PCMachineState
*pcms
,
571 BusState
*idebus0
, BusState
*idebus1
,
575 static pc_cmos_init_late_arg arg
;
576 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
577 MC146818RtcState
*s
= MC146818_RTC(rtc
);
579 /* various important CMOS locations needed by PC/Bochs bios */
582 /* base memory (first MiB) */
583 val
= MIN(x86ms
->below_4g_mem_size
/ KiB
, 640);
584 mc146818rtc_set_cmos_data(s
, 0x15, val
);
585 mc146818rtc_set_cmos_data(s
, 0x16, val
>> 8);
586 /* extended memory (next 64MiB) */
587 if (x86ms
->below_4g_mem_size
> 1 * MiB
) {
588 val
= (x86ms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
594 mc146818rtc_set_cmos_data(s
, 0x17, val
);
595 mc146818rtc_set_cmos_data(s
, 0x18, val
>> 8);
596 mc146818rtc_set_cmos_data(s
, 0x30, val
);
597 mc146818rtc_set_cmos_data(s
, 0x31, val
>> 8);
598 /* memory between 16MiB and 4GiB */
599 if (x86ms
->below_4g_mem_size
> 16 * MiB
) {
600 val
= (x86ms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
606 mc146818rtc_set_cmos_data(s
, 0x34, val
);
607 mc146818rtc_set_cmos_data(s
, 0x35, val
>> 8);
608 /* memory above 4GiB */
609 val
= x86ms
->above_4g_mem_size
/ 65536;
610 mc146818rtc_set_cmos_data(s
, 0x5b, val
);
611 mc146818rtc_set_cmos_data(s
, 0x5c, val
>> 8);
612 mc146818rtc_set_cmos_data(s
, 0x5d, val
>> 16);
614 object_property_add_link(OBJECT(pcms
), "rtc_state",
616 (Object
**)&x86ms
->rtc
,
617 object_property_allow_set_link
,
618 OBJ_PROP_LINK_STRONG
);
619 object_property_set_link(OBJECT(pcms
), "rtc_state", OBJECT(s
),
622 set_boot_dev(s
, MACHINE(pcms
)->boot_config
.order
, &error_fatal
);
625 val
|= 0x02; /* FPU is there */
626 val
|= 0x04; /* PS/2 mouse installed */
627 mc146818rtc_set_cmos_data(s
, REG_EQUIPMENT_BYTE
, val
);
629 /* hard drives and FDC */
631 arg
.idebus
[0] = idebus0
;
632 arg
.idebus
[1] = idebus1
;
633 qemu_register_reset(pc_cmos_init_late
, &arg
);
636 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
638 X86CPU
*cpu
= opaque
;
640 /* XXX: send to all CPUs ? */
641 /* XXX: add logic to handle multiple A20 line sources */
642 x86_cpu_set_a20(cpu
, level
);
645 #define NE2000_NB_MAX 6
647 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
649 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
651 static void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
653 static int nb_ne2k
= 0;
655 if (nb_ne2k
== NE2000_NB_MAX
)
657 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
658 ne2000_irq
[nb_ne2k
], nd
);
662 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
664 X86CPU
*cpu
= opaque
;
667 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
672 void pc_machine_done(Notifier
*notifier
, void *data
)
674 PCMachineState
*pcms
= container_of(notifier
,
675 PCMachineState
, machine_done
);
676 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
678 cxl_hook_up_pxb_registers(pcms
->bus
, &pcms
->cxl_devices_state
,
681 if (pcms
->cxl_devices_state
.is_enabled
) {
682 cxl_fmws_link_targets(&pcms
->cxl_devices_state
, &error_fatal
);
685 /* set the number of CPUs */
686 x86_rtc_set_cpus_count(x86ms
->rtc
, x86ms
->boot_cpus
);
688 fw_cfg_add_extra_pci_roots(pcms
->bus
, x86ms
->fw_cfg
);
692 fw_cfg_build_smbios(MACHINE(pcms
), x86ms
->fw_cfg
);
693 fw_cfg_build_feature_control(MACHINE(pcms
), x86ms
->fw_cfg
);
694 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
695 fw_cfg_modify_i16(x86ms
->fw_cfg
, FW_CFG_NB_CPUS
, x86ms
->boot_cpus
);
699 void pc_guest_info_init(PCMachineState
*pcms
)
701 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
703 x86ms
->apic_xrupt_override
= true;
704 pcms
->machine_done
.notify
= pc_machine_done
;
705 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
708 /* setup pci memory address space mapping into system address space */
709 void pc_pci_as_mapping_init(MemoryRegion
*system_memory
,
710 MemoryRegion
*pci_address_space
)
712 /* Set to lower priority than RAM */
713 memory_region_add_subregion_overlap(system_memory
, 0x0,
714 pci_address_space
, -1);
717 void xen_load_linux(PCMachineState
*pcms
)
721 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
722 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
724 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
726 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
727 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, x86ms
->boot_cpus
);
730 x86_load_linux(x86ms
, fw_cfg
, pcmc
->acpi_data_size
,
732 for (i
= 0; i
< nb_option_roms
; i
++) {
733 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
734 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
735 !strcmp(option_rom
[i
].name
, "pvh.bin") ||
736 !strcmp(option_rom
[i
].name
, "multiboot.bin") ||
737 !strcmp(option_rom
[i
].name
, "multiboot_dma.bin"));
738 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
740 x86ms
->fw_cfg
= fw_cfg
;
743 #define PC_ROM_MIN_VGA 0xc0000
744 #define PC_ROM_MIN_OPTION 0xc8000
745 #define PC_ROM_MAX 0xe0000
746 #define PC_ROM_ALIGN 0x800
747 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
749 static hwaddr
pc_above_4g_end(PCMachineState
*pcms
)
751 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
753 if (pcms
->sgx_epc
.size
!= 0) {
754 return sgx_epc_above_4g_end(&pcms
->sgx_epc
);
757 return x86ms
->above_4g_mem_start
+ x86ms
->above_4g_mem_size
;
760 static void pc_get_device_memory_range(PCMachineState
*pcms
,
762 ram_addr_t
*device_mem_size
)
764 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
765 MachineState
*machine
= MACHINE(pcms
);
769 size
= machine
->maxram_size
- machine
->ram_size
;
770 addr
= ROUND_UP(pc_above_4g_end(pcms
), 1 * GiB
);
772 if (pcmc
->enforce_aligned_dimm
) {
773 /* size device region assuming 1G page max alignment per slot */
774 size
+= (1 * GiB
) * machine
->ram_slots
;
778 *device_mem_size
= size
;
781 static uint64_t pc_get_cxl_range_start(PCMachineState
*pcms
)
783 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
787 if (pcmc
->has_reserved_memory
) {
788 pc_get_device_memory_range(pcms
, &cxl_base
, &size
);
791 cxl_base
= pc_above_4g_end(pcms
);
797 static uint64_t pc_get_cxl_range_end(PCMachineState
*pcms
)
799 uint64_t start
= pc_get_cxl_range_start(pcms
) + MiB
;
801 if (pcms
->cxl_devices_state
.fixed_windows
) {
804 start
= ROUND_UP(start
, 256 * MiB
);
805 for (it
= pcms
->cxl_devices_state
.fixed_windows
; it
; it
= it
->next
) {
806 CXLFixedWindow
*fw
= it
->data
;
814 static hwaddr
pc_max_used_gpa(PCMachineState
*pcms
, uint64_t pci_hole64_size
)
816 X86CPU
*cpu
= X86_CPU(first_cpu
);
817 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
818 MachineState
*ms
= MACHINE(pcms
);
820 if (cpu
->env
.features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
822 return pc_pci_hole64_start() + pci_hole64_size
- 1;
826 if (pcmc
->broken_32bit_mem_addr_check
) {
827 /* old value for compatibility reasons */
828 return ((hwaddr
)1 << cpu
->phys_bits
) - 1;
832 * 32-bit systems don't have hole64 but they might have a region for
833 * memory devices. Even if additional hotplugged memory devices might
834 * not be usable by most guest OSes, we need to still consider them for
835 * calculating the highest possible GPA so that we can properly report
836 * if someone configures them on a CPU that cannot possibly address them.
838 if (pcmc
->has_reserved_memory
&&
839 (ms
->ram_size
< ms
->maxram_size
)) {
841 ram_addr_t devmem_size
;
843 pc_get_device_memory_range(pcms
, &devmem_start
, &devmem_size
);
844 devmem_start
+= devmem_size
;
845 return devmem_start
- 1;
848 /* configuration without any memory hotplug */
849 return pc_above_4g_end(pcms
) - 1;
853 * AMD systems with an IOMMU have an additional hole close to the
854 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
855 * on kernel version, VFIO may or may not let you DMA map those ranges.
856 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
857 * with certain memory sizes. It's also wrong to use those IOVA ranges
858 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
859 * The ranges reserved for Hyper-Transport are:
861 * FD_0000_0000h - FF_FFFF_FFFFh
863 * The ranges represent the following:
865 * Base Address Top Address Use
867 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
868 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
869 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
870 * FD_F910_0000h FD_F91F_FFFFh System Management
871 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
872 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
873 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
874 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
875 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
876 * FE_2000_0000h FF_FFFF_FFFFh Reserved
878 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
879 * Table 3: Special Address Controls (GPA) for more information.
881 #define AMD_HT_START 0xfd00000000UL
882 #define AMD_HT_END 0xffffffffffUL
883 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
884 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
886 void pc_memory_init(PCMachineState
*pcms
,
887 MemoryRegion
*system_memory
,
888 MemoryRegion
*rom_memory
,
889 uint64_t pci_hole64_size
)
892 MemoryRegion
*option_rom_mr
;
893 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
895 MachineState
*machine
= MACHINE(pcms
);
896 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
897 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
898 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
899 hwaddr maxphysaddr
, maxusedaddr
;
900 hwaddr cxl_base
, cxl_resv_end
= 0;
901 X86CPU
*cpu
= X86_CPU(first_cpu
);
903 assert(machine
->ram_size
== x86ms
->below_4g_mem_size
+
904 x86ms
->above_4g_mem_size
);
906 linux_boot
= (machine
->kernel_filename
!= NULL
);
909 * The HyperTransport range close to the 1T boundary is unique to AMD
910 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
911 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
912 * older machine types (<= 7.0) for compatibility purposes.
914 if (IS_AMD_CPU(&cpu
->env
) && pcmc
->enforce_amd_1tb_hole
) {
915 /* Bail out if max possible address does not cross HT range */
916 if (pc_max_used_gpa(pcms
, pci_hole64_size
) >= AMD_HT_START
) {
917 x86ms
->above_4g_mem_start
= AMD_ABOVE_1TB_START
;
921 * Advertise the HT region if address space covers the reserved
922 * region or if we relocate.
924 if (cpu
->phys_bits
>= 40) {
925 e820_add_entry(AMD_HT_START
, AMD_HT_SIZE
, E820_RESERVED
);
930 * phys-bits is required to be appropriately configured
931 * to make sure max used GPA is reachable.
933 maxusedaddr
= pc_max_used_gpa(pcms
, pci_hole64_size
);
934 maxphysaddr
= ((hwaddr
)1 << cpu
->phys_bits
) - 1;
935 if (maxphysaddr
< maxusedaddr
) {
936 error_report("Address space limit 0x%"PRIx64
" < 0x%"PRIx64
937 " phys-bits too low (%u)",
938 maxphysaddr
, maxusedaddr
, cpu
->phys_bits
);
943 * Split single memory region and use aliases to address portions of it,
944 * done for backwards compatibility with older qemus.
946 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
947 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", machine
->ram
,
948 0, x86ms
->below_4g_mem_size
);
949 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
950 e820_add_entry(0, x86ms
->below_4g_mem_size
, E820_RAM
);
951 if (x86ms
->above_4g_mem_size
> 0) {
952 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
953 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g",
955 x86ms
->below_4g_mem_size
,
956 x86ms
->above_4g_mem_size
);
957 memory_region_add_subregion(system_memory
, x86ms
->above_4g_mem_start
,
959 e820_add_entry(x86ms
->above_4g_mem_start
, x86ms
->above_4g_mem_size
,
963 if (pcms
->sgx_epc
.size
!= 0) {
964 e820_add_entry(pcms
->sgx_epc
.base
, pcms
->sgx_epc
.size
, E820_RESERVED
);
967 if (!pcmc
->has_reserved_memory
&&
968 (machine
->ram_slots
||
969 (machine
->maxram_size
> machine
->ram_size
))) {
971 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
976 /* initialize device memory address space */
977 if (pcmc
->has_reserved_memory
&&
978 (machine
->ram_size
< machine
->maxram_size
)) {
979 ram_addr_t device_mem_size
;
980 hwaddr device_mem_base
;
982 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
983 error_report("unsupported amount of memory slots: %"PRIu64
,
988 if (QEMU_ALIGN_UP(machine
->maxram_size
,
989 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
990 error_report("maximum memory size must by aligned to multiple of "
991 "%d bytes", TARGET_PAGE_SIZE
);
995 pc_get_device_memory_range(pcms
, &device_mem_base
, &device_mem_size
);
997 if (device_mem_base
+ device_mem_size
< device_mem_size
) {
998 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
999 machine
->maxram_size
);
1002 machine_memory_devices_init(machine
, device_mem_base
, device_mem_size
);
1005 if (pcms
->cxl_devices_state
.is_enabled
) {
1006 MemoryRegion
*mr
= &pcms
->cxl_devices_state
.host_mr
;
1007 hwaddr cxl_size
= MiB
;
1009 cxl_base
= pc_get_cxl_range_start(pcms
);
1010 memory_region_init(mr
, OBJECT(machine
), "cxl_host_reg", cxl_size
);
1011 memory_region_add_subregion(system_memory
, cxl_base
, mr
);
1012 cxl_resv_end
= cxl_base
+ cxl_size
;
1013 if (pcms
->cxl_devices_state
.fixed_windows
) {
1014 hwaddr cxl_fmw_base
;
1017 cxl_fmw_base
= ROUND_UP(cxl_base
+ cxl_size
, 256 * MiB
);
1018 for (it
= pcms
->cxl_devices_state
.fixed_windows
; it
; it
= it
->next
) {
1019 CXLFixedWindow
*fw
= it
->data
;
1021 fw
->base
= cxl_fmw_base
;
1022 memory_region_init_io(&fw
->mr
, OBJECT(machine
), &cfmws_ops
, fw
,
1023 "cxl-fixed-memory-region", fw
->size
);
1024 memory_region_add_subregion(system_memory
, fw
->base
, &fw
->mr
);
1025 cxl_fmw_base
+= fw
->size
;
1026 cxl_resv_end
= cxl_fmw_base
;
1031 /* Initialize PC system firmware */
1032 pc_system_firmware_init(pcms
, rom_memory
);
1034 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1035 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1037 if (pcmc
->pci_enabled
) {
1038 memory_region_set_readonly(option_rom_mr
, true);
1040 memory_region_add_subregion_overlap(rom_memory
,
1045 fw_cfg
= fw_cfg_arch_create(machine
,
1046 x86ms
->boot_cpus
, x86ms
->apic_id_limit
);
1050 if (machine
->device_memory
) {
1051 uint64_t *val
= g_malloc(sizeof(*val
));
1052 uint64_t res_mem_end
= machine
->device_memory
->base
;
1054 if (!pcmc
->broken_reserved_end
) {
1055 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1058 if (pcms
->cxl_devices_state
.is_enabled
) {
1059 res_mem_end
= cxl_resv_end
;
1061 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1062 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1066 x86_load_linux(x86ms
, fw_cfg
, pcmc
->acpi_data_size
,
1070 for (i
= 0; i
< nb_option_roms
; i
++) {
1071 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1073 x86ms
->fw_cfg
= fw_cfg
;
1075 /* Init default IOAPIC address space */
1076 x86ms
->ioapic_as
= &address_space_memory
;
1078 /* Init ACPI memory hotplug IO base address */
1079 pcms
->memhp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
1083 * The 64bit pci hole starts after "above 4G RAM" and
1084 * potentially the space reserved for memory hotplug.
1086 uint64_t pc_pci_hole64_start(void)
1088 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1089 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1090 MachineState
*ms
= MACHINE(pcms
);
1091 uint64_t hole64_start
= 0;
1092 ram_addr_t size
= 0;
1094 if (pcms
->cxl_devices_state
.is_enabled
) {
1095 hole64_start
= pc_get_cxl_range_end(pcms
);
1096 } else if (pcmc
->has_reserved_memory
&& (ms
->ram_size
< ms
->maxram_size
)) {
1097 pc_get_device_memory_range(pcms
, &hole64_start
, &size
);
1098 if (!pcmc
->broken_reserved_end
) {
1099 hole64_start
+= size
;
1102 hole64_start
= pc_above_4g_end(pcms
);
1105 return ROUND_UP(hole64_start
, 1 * GiB
);
1108 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1110 DeviceState
*dev
= NULL
;
1112 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1114 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1115 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1116 } else if (isa_bus
) {
1117 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1118 dev
= isadev
? DEVICE(isadev
) : NULL
;
1120 rom_reset_order_override();
1124 static const MemoryRegionOps ioport80_io_ops
= {
1125 .write
= ioport80_write
,
1126 .read
= ioport80_read
,
1127 .endianness
= DEVICE_NATIVE_ENDIAN
,
1129 .min_access_size
= 1,
1130 .max_access_size
= 1,
1134 static const MemoryRegionOps ioportF0_io_ops
= {
1135 .write
= ioportF0_write
,
1136 .read
= ioportF0_read
,
1137 .endianness
= DEVICE_NATIVE_ENDIAN
,
1139 .min_access_size
= 1,
1140 .max_access_size
= 1,
1144 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
,
1145 bool create_i8042
, bool no_vmport
)
1148 DriveInfo
*fd
[MAX_FD
];
1150 ISADevice
*fdc
, *i8042
, *port92
, *vmmouse
;
1152 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1153 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1155 for (i
= 0; i
< MAX_FD
; i
++) {
1156 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1157 create_fdctrl
|= !!fd
[i
];
1159 if (create_fdctrl
) {
1160 fdc
= isa_new(TYPE_ISA_FDC
);
1162 isa_realize_and_unref(fdc
, isa_bus
, &error_fatal
);
1163 isa_fdc_init_drives(fdc
, fd
);
1167 if (!create_i8042
) {
1171 i8042
= isa_create_simple(isa_bus
, TYPE_I8042
);
1173 isa_create_simple(isa_bus
, TYPE_VMPORT
);
1174 vmmouse
= isa_try_new("vmmouse");
1179 object_property_set_link(OBJECT(vmmouse
), TYPE_I8042
, OBJECT(i8042
),
1181 isa_realize_and_unref(vmmouse
, isa_bus
, &error_fatal
);
1183 port92
= isa_create_simple(isa_bus
, TYPE_PORT92
);
1185 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1186 i8042_setup_a20_line(i8042
, a20_line
[0]);
1187 qdev_connect_gpio_out_named(DEVICE(port92
),
1188 PORT92_A20_LINE
, 0, a20_line
[1]);
1192 void pc_basic_device_init(struct PCMachineState
*pcms
,
1193 ISABus
*isa_bus
, qemu_irq
*gsi
,
1194 ISADevice
*rtc_state
,
1199 DeviceState
*hpet
= NULL
;
1200 int pit_isa_irq
= 0;
1201 qemu_irq pit_alt_irq
= NULL
;
1202 qemu_irq rtc_irq
= NULL
;
1203 ISADevice
*pit
= NULL
;
1204 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1205 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1206 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
1208 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1209 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1211 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1212 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1215 * Check if an HPET shall be created.
1217 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1218 * when the HPET wants to take over. Thus we have to disable the latter.
1220 if (pcms
->hpet_enabled
&& (!kvm_irqchip_in_kernel() ||
1221 kvm_has_pit_state2())) {
1222 hpet
= qdev_try_new(TYPE_HPET
);
1224 error_report("couldn't create HPET device");
1228 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1229 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1230 * the property, use whatever mask they specified.
1232 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1235 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1237 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet
), &error_fatal
);
1238 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1240 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1241 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1244 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1245 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1249 qdev_connect_gpio_out(DEVICE(rtc_state
), 0, rtc_irq
);
1251 uint32_t irq
= object_property_get_uint(OBJECT(rtc_state
),
1254 isa_connect_gpio_out(rtc_state
, 0, irq
);
1256 object_property_add_alias(OBJECT(pcms
), "rtc-time", OBJECT(rtc_state
),
1259 #ifdef CONFIG_XEN_EMU
1260 if (xen_mode
== XEN_EMULATE
) {
1261 xen_overlay_create();
1262 xen_evtchn_create(IOAPIC_NUM_PINS
, gsi
);
1263 xen_gnttab_create();
1264 xen_xenstore_create();
1266 pci_create_simple(pcms
->bus
, -1, "xen-platform");
1273 qemu_register_boot_set(pc_boot_set
, rtc_state
);
1275 if (!xen_enabled() &&
1276 (x86ms
->pit
== ON_OFF_AUTO_AUTO
|| x86ms
->pit
== ON_OFF_AUTO_ON
)) {
1277 if (kvm_pit_in_kernel()) {
1278 pit
= kvm_pit_init(isa_bus
, 0x40);
1280 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1283 /* connect PIT to output control line of the HPET */
1284 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1286 object_property_set_link(OBJECT(pcms
->pcspk
), "pit",
1287 OBJECT(pit
), &error_fatal
);
1288 isa_realize_and_unref(pcms
->pcspk
, isa_bus
, &error_fatal
);
1292 pc_superio_init(isa_bus
, create_fdctrl
, pcms
->i8042_enabled
,
1293 pcms
->vmport
!= ON_OFF_AUTO_ON
);
1296 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1298 MachineClass
*mc
= MACHINE_CLASS(pcmc
);
1301 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1302 for (i
= 0; i
< nb_nics
; i
++) {
1303 NICInfo
*nd
= &nd_table
[i
];
1304 const char *model
= nd
->model
? nd
->model
: mc
->default_nic
;
1306 if (g_str_equal(model
, "ne2k_isa")) {
1307 pc_init_ne2k_isa(isa_bus
, nd
);
1309 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1312 rom_reset_order_override();
1315 void pc_i8259_create(ISABus
*isa_bus
, qemu_irq
*i8259_irqs
)
1319 if (kvm_pic_in_kernel()) {
1320 i8259
= kvm_i8259_init(isa_bus
);
1321 } else if (xen_enabled()) {
1322 i8259
= xen_interrupt_controller_init();
1324 i8259
= i8259_init(isa_bus
, x86_allocate_cpu_irq());
1327 for (size_t i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1328 i8259_irqs
[i
] = i8259
[i
];
1334 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1337 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1338 const X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1339 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1340 const MachineState
*ms
= MACHINE(hotplug_dev
);
1341 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1342 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
1343 Error
*local_err
= NULL
;
1346 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1347 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1348 * addition to cover this case.
1350 if (!x86ms
->acpi_dev
|| !x86_machine_is_acpi_enabled(x86ms
)) {
1352 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1356 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
1357 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1361 hotplug_handler_pre_plug(x86ms
->acpi_dev
, dev
, &local_err
);
1363 error_propagate(errp
, local_err
);
1367 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
1368 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
1371 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1372 DeviceState
*dev
, Error
**errp
)
1374 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1375 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1376 MachineState
*ms
= MACHINE(hotplug_dev
);
1377 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1379 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
));
1382 nvdimm_plug(ms
->nvdimms_state
);
1385 hotplug_handler_plug(x86ms
->acpi_dev
, dev
, &error_abort
);
1388 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1389 DeviceState
*dev
, Error
**errp
)
1391 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1394 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1395 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1396 * addition to cover this case.
1398 if (!x86ms
->acpi_dev
|| !x86_machine_is_acpi_enabled(x86ms
)) {
1400 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1404 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1405 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
1409 hotplug_handler_unplug_request(x86ms
->acpi_dev
, dev
,
1413 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
1414 DeviceState
*dev
, Error
**errp
)
1416 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1417 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1418 Error
*local_err
= NULL
;
1420 hotplug_handler_unplug(x86ms
->acpi_dev
, dev
, &local_err
);
1425 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
1426 qdev_unrealize(dev
);
1428 error_propagate(errp
, local_err
);
1431 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
1432 DeviceState
*dev
, Error
**errp
)
1434 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1435 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
1436 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1437 x86_cpu_pre_plug(hotplug_dev
, dev
, errp
);
1438 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
1439 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
1440 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
1441 /* Declare the APIC range as the reserved MSI region */
1442 char *resv_prop_str
= g_strdup_printf("0xfee00000:0xfeefffff:%d",
1443 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
1445 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
1446 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
1447 resv_prop_str
, errp
);
1448 g_free(resv_prop_str
);
1451 if (object_dynamic_cast(OBJECT(dev
), TYPE_X86_IOMMU_DEVICE
) ||
1452 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
1453 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1456 error_setg(errp
, "QEMU does not support multiple vIOMMUs "
1464 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1465 DeviceState
*dev
, Error
**errp
)
1467 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1468 pc_memory_plug(hotplug_dev
, dev
, errp
);
1469 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1470 x86_cpu_plug(hotplug_dev
, dev
, errp
);
1471 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
1472 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
1476 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1477 DeviceState
*dev
, Error
**errp
)
1479 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1480 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
1481 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1482 x86_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
1483 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
1484 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
1487 error_setg(errp
, "acpi: device unplug request for not supported device"
1488 " type: %s", object_get_typename(OBJECT(dev
)));
1492 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
1493 DeviceState
*dev
, Error
**errp
)
1495 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1496 pc_memory_unplug(hotplug_dev
, dev
, errp
);
1497 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1498 x86_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
1499 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
1500 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
1502 error_setg(errp
, "acpi: device unplug for not supported device"
1503 " type: %s", object_get_typename(OBJECT(dev
)));
1507 static HotplugHandler
*pc_get_hotplug_handler(MachineState
*machine
,
1510 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
1511 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
) ||
1512 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
1513 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
) ||
1514 object_dynamic_cast(OBJECT(dev
), TYPE_X86_IOMMU_DEVICE
)) {
1515 return HOTPLUG_HANDLER(machine
);
1521 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
1522 void *opaque
, Error
**errp
)
1524 PCMachineState
*pcms
= PC_MACHINE(obj
);
1525 OnOffAuto vmport
= pcms
->vmport
;
1527 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
1530 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
1531 void *opaque
, Error
**errp
)
1533 PCMachineState
*pcms
= PC_MACHINE(obj
);
1535 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
1538 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
1540 PCMachineState
*pcms
= PC_MACHINE(obj
);
1542 return pcms
->smbus_enabled
;
1545 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
1547 PCMachineState
*pcms
= PC_MACHINE(obj
);
1549 pcms
->smbus_enabled
= value
;
1552 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
1554 PCMachineState
*pcms
= PC_MACHINE(obj
);
1556 return pcms
->sata_enabled
;
1559 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
1561 PCMachineState
*pcms
= PC_MACHINE(obj
);
1563 pcms
->sata_enabled
= value
;
1566 static bool pc_machine_get_hpet(Object
*obj
, Error
**errp
)
1568 PCMachineState
*pcms
= PC_MACHINE(obj
);
1570 return pcms
->hpet_enabled
;
1573 static void pc_machine_set_hpet(Object
*obj
, bool value
, Error
**errp
)
1575 PCMachineState
*pcms
= PC_MACHINE(obj
);
1577 pcms
->hpet_enabled
= value
;
1580 static bool pc_machine_get_i8042(Object
*obj
, Error
**errp
)
1582 PCMachineState
*pcms
= PC_MACHINE(obj
);
1584 return pcms
->i8042_enabled
;
1587 static void pc_machine_set_i8042(Object
*obj
, bool value
, Error
**errp
)
1589 PCMachineState
*pcms
= PC_MACHINE(obj
);
1591 pcms
->i8042_enabled
= value
;
1594 static bool pc_machine_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
1596 PCMachineState
*pcms
= PC_MACHINE(obj
);
1598 return pcms
->default_bus_bypass_iommu
;
1601 static void pc_machine_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
1604 PCMachineState
*pcms
= PC_MACHINE(obj
);
1606 pcms
->default_bus_bypass_iommu
= value
;
1609 static void pc_machine_get_smbios_ep(Object
*obj
, Visitor
*v
, const char *name
,
1610 void *opaque
, Error
**errp
)
1612 PCMachineState
*pcms
= PC_MACHINE(obj
);
1613 SmbiosEntryPointType smbios_entry_point_type
= pcms
->smbios_entry_point_type
;
1615 visit_type_SmbiosEntryPointType(v
, name
, &smbios_entry_point_type
, errp
);
1618 static void pc_machine_set_smbios_ep(Object
*obj
, Visitor
*v
, const char *name
,
1619 void *opaque
, Error
**errp
)
1621 PCMachineState
*pcms
= PC_MACHINE(obj
);
1623 visit_type_SmbiosEntryPointType(v
, name
, &pcms
->smbios_entry_point_type
, errp
);
1626 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1627 const char *name
, void *opaque
,
1630 PCMachineState
*pcms
= PC_MACHINE(obj
);
1631 uint64_t value
= pcms
->max_ram_below_4g
;
1633 visit_type_size(v
, name
, &value
, errp
);
1636 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1637 const char *name
, void *opaque
,
1640 PCMachineState
*pcms
= PC_MACHINE(obj
);
1643 if (!visit_type_size(v
, name
, &value
, errp
)) {
1646 if (value
> 4 * GiB
) {
1648 "Machine option 'max-ram-below-4g=%"PRIu64
1649 "' expects size less than or equal to 4G", value
);
1653 if (value
< 1 * MiB
) {
1654 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
1655 "BIOS may not work with less than 1MiB", value
);
1658 pcms
->max_ram_below_4g
= value
;
1661 static void pc_machine_get_max_fw_size(Object
*obj
, Visitor
*v
,
1662 const char *name
, void *opaque
,
1665 PCMachineState
*pcms
= PC_MACHINE(obj
);
1666 uint64_t value
= pcms
->max_fw_size
;
1668 visit_type_size(v
, name
, &value
, errp
);
1671 static void pc_machine_set_max_fw_size(Object
*obj
, Visitor
*v
,
1672 const char *name
, void *opaque
,
1675 PCMachineState
*pcms
= PC_MACHINE(obj
);
1678 if (!visit_type_size(v
, name
, &value
, errp
)) {
1683 * We don't have a theoretically justifiable exact lower bound on the base
1684 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1685 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1686 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1689 if (value
> 16 * MiB
) {
1691 "User specified max allowed firmware size %" PRIu64
" is "
1692 "greater than 16MiB. If combined firmware size exceeds "
1693 "16MiB the system may not boot, or experience intermittent"
1694 "stability issues.",
1699 pcms
->max_fw_size
= value
;
1703 static void pc_machine_initfn(Object
*obj
)
1705 PCMachineState
*pcms
= PC_MACHINE(obj
);
1706 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1708 #ifdef CONFIG_VMPORT
1709 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
1711 pcms
->vmport
= ON_OFF_AUTO_OFF
;
1712 #endif /* CONFIG_VMPORT */
1713 pcms
->max_ram_below_4g
= 0; /* use default */
1714 pcms
->smbios_entry_point_type
= pcmc
->default_smbios_ep_type
;
1716 /* acpi build is enabled by default if machine supports it */
1717 pcms
->acpi_build_enabled
= pcmc
->has_acpi_build
;
1718 pcms
->smbus_enabled
= true;
1719 pcms
->sata_enabled
= true;
1720 pcms
->i8042_enabled
= true;
1721 pcms
->max_fw_size
= 8 * MiB
;
1723 pcms
->hpet_enabled
= true;
1725 pcms
->default_bus_bypass_iommu
= false;
1727 pc_system_flash_create(pcms
);
1728 pcms
->pcspk
= isa_new(TYPE_PC_SPEAKER
);
1729 object_property_add_alias(OBJECT(pcms
), "pcspk-audiodev",
1730 OBJECT(pcms
->pcspk
), "audiodev");
1731 cxl_machine_init(obj
, &pcms
->cxl_devices_state
);
1734 int pc_machine_kvm_type(MachineState
*machine
, const char *kvm_type
)
1739 static void pc_machine_reset(MachineState
*machine
, ShutdownCause reason
)
1744 qemu_devices_reset(reason
);
1746 /* Reset APIC after devices have been reset to cancel
1747 * any changes that qemu_devices_reset() might have done.
1752 x86_cpu_after_reset(cpu
);
1756 static void pc_machine_wakeup(MachineState
*machine
)
1758 cpu_synchronize_all_states();
1759 pc_machine_reset(machine
, SHUTDOWN_CAUSE_NONE
);
1760 cpu_synchronize_all_post_reset();
1763 static bool pc_hotplug_allowed(MachineState
*ms
, DeviceState
*dev
, Error
**errp
)
1765 X86IOMMUState
*iommu
= x86_iommu_get_default();
1766 IntelIOMMUState
*intel_iommu
;
1769 object_dynamic_cast((Object
*)iommu
, TYPE_INTEL_IOMMU_DEVICE
) &&
1770 object_dynamic_cast((Object
*)dev
, "vfio-pci")) {
1771 intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
1772 if (!intel_iommu
->caching_mode
) {
1773 error_setg(errp
, "Device assignment is not allowed without "
1774 "enabling caching-mode=on for Intel IOMMU.");
1782 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
1784 MachineClass
*mc
= MACHINE_CLASS(oc
);
1785 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
1786 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1788 pcmc
->pci_enabled
= true;
1789 pcmc
->has_acpi_build
= true;
1790 pcmc
->rsdp_in_ram
= true;
1791 pcmc
->smbios_defaults
= true;
1792 pcmc
->smbios_uuid_encoded
= true;
1793 pcmc
->gigabyte_align
= true;
1794 pcmc
->has_reserved_memory
= true;
1795 pcmc
->kvmclock_enabled
= true;
1796 pcmc
->enforce_aligned_dimm
= true;
1797 pcmc
->enforce_amd_1tb_hole
= true;
1798 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1799 * to be used at the moment, 32K should be enough for a while. */
1800 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
1801 pcmc
->pvh_enabled
= true;
1802 pcmc
->kvmclock_create_always
= true;
1803 pcmc
->resizable_acpi_blob
= true;
1804 assert(!mc
->get_hotplug_handler
);
1805 mc
->get_hotplug_handler
= pc_get_hotplug_handler
;
1806 mc
->hotplug_allowed
= pc_hotplug_allowed
;
1807 mc
->cpu_index_to_instance_props
= x86_cpu_index_to_props
;
1808 mc
->get_default_cpu_node_id
= x86_get_default_cpu_node_id
;
1809 mc
->possible_cpu_arch_ids
= x86_possible_cpu_arch_ids
;
1810 mc
->auto_enable_numa_with_memhp
= true;
1811 mc
->auto_enable_numa_with_memdev
= true;
1812 mc
->has_hotpluggable_cpus
= true;
1813 mc
->default_boot_order
= "cad";
1814 mc
->block_default_type
= IF_IDE
;
1816 mc
->reset
= pc_machine_reset
;
1817 mc
->wakeup
= pc_machine_wakeup
;
1818 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
1819 hc
->plug
= pc_machine_device_plug_cb
;
1820 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
1821 hc
->unplug
= pc_machine_device_unplug_cb
;
1822 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
1823 mc
->nvdimm_supported
= true;
1824 mc
->smp_props
.dies_supported
= true;
1825 mc
->default_ram_id
= "pc.ram";
1826 pcmc
->default_smbios_ep_type
= SMBIOS_ENTRY_POINT_TYPE_64
;
1828 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
1829 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
1831 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
1832 "Maximum ram below the 4G boundary (32bit boundary)");
1834 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
1835 pc_machine_get_vmport
, pc_machine_set_vmport
,
1837 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
1838 "Enable vmport (pc & q35)");
1840 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
1841 pc_machine_get_smbus
, pc_machine_set_smbus
);
1842 object_class_property_set_description(oc
, PC_MACHINE_SMBUS
,
1843 "Enable/disable system management bus");
1845 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
1846 pc_machine_get_sata
, pc_machine_set_sata
);
1847 object_class_property_set_description(oc
, PC_MACHINE_SATA
,
1848 "Enable/disable Serial ATA bus");
1850 object_class_property_add_bool(oc
, "hpet",
1851 pc_machine_get_hpet
, pc_machine_set_hpet
);
1852 object_class_property_set_description(oc
, "hpet",
1853 "Enable/disable high precision event timer emulation");
1855 object_class_property_add_bool(oc
, PC_MACHINE_I8042
,
1856 pc_machine_get_i8042
, pc_machine_set_i8042
);
1858 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
1859 pc_machine_get_default_bus_bypass_iommu
,
1860 pc_machine_set_default_bus_bypass_iommu
);
1862 object_class_property_add(oc
, PC_MACHINE_MAX_FW_SIZE
, "size",
1863 pc_machine_get_max_fw_size
, pc_machine_set_max_fw_size
,
1865 object_class_property_set_description(oc
, PC_MACHINE_MAX_FW_SIZE
,
1866 "Maximum combined firmware size");
1868 object_class_property_add(oc
, PC_MACHINE_SMBIOS_EP
, "str",
1869 pc_machine_get_smbios_ep
, pc_machine_set_smbios_ep
,
1871 object_class_property_set_description(oc
, PC_MACHINE_SMBIOS_EP
,
1872 "SMBIOS Entry Point type [32, 64]");
1875 static const TypeInfo pc_machine_info
= {
1876 .name
= TYPE_PC_MACHINE
,
1877 .parent
= TYPE_X86_MACHINE
,
1879 .instance_size
= sizeof(PCMachineState
),
1880 .instance_init
= pc_machine_initfn
,
1881 .class_size
= sizeof(PCMachineClass
),
1882 .class_init
= pc_machine_class_init
,
1883 .interfaces
= (InterfaceInfo
[]) {
1884 { TYPE_HOTPLUG_HANDLER
},
1889 static void pc_machine_register_types(void)
1891 type_register_static(&pc_machine_info
);
1894 type_init(pc_machine_register_types
)