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Merge tag 'pull-xenfv.for-upstream-20231107' of git://git.infradead.org/users/dwmw2...
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/internal.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qemu/error-report.h"
48 #include "hw/acpi/cpu_hotplug.h"
49 #include "acpi-build.h"
50 #include "hw/mem/nvdimm.h"
51 #include "hw/cxl/cxl_host.h"
52 #include "hw/usb.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/net/ne2000-isa.h"
55 #include "hw/virtio/virtio-iommu.h"
56 #include "hw/virtio/virtio-md-pci.h"
57 #include "hw/i386/kvm/xen_overlay.h"
58 #include "hw/i386/kvm/xen_evtchn.h"
59 #include "hw/i386/kvm/xen_gnttab.h"
60 #include "hw/i386/kvm/xen_xenstore.h"
61 #include "hw/mem/memory-device.h"
62 #include "e820_memory_layout.h"
63 #include "trace.h"
64 #include CONFIG_DEVICES
65
66 #ifdef CONFIG_XEN_EMU
67 #include "hw/xen/xen-legacy-backend.h"
68 #include "hw/xen/xen-bus.h"
69 #endif
70
71 /*
72 * Helper for setting model-id for CPU models that changed model-id
73 * depending on QEMU versions up to QEMU 2.4.
74 */
75 #define PC_CPU_MODEL_IDS(v) \
76 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
77 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
78 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
79
80 GlobalProperty pc_compat_8_1[] = {};
81 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
82
83 GlobalProperty pc_compat_8_0[] = {
84 { "virtio-mem", "unplugged-inaccessible", "auto" },
85 };
86 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
87
88 GlobalProperty pc_compat_7_2[] = {
89 { "ICH9-LPC", "noreboot", "true" },
90 };
91 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
92
93 GlobalProperty pc_compat_7_1[] = {};
94 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
95
96 GlobalProperty pc_compat_7_0[] = {};
97 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
98
99 GlobalProperty pc_compat_6_2[] = {
100 { "virtio-mem", "unplugged-inaccessible", "off" },
101 };
102 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
103
104 GlobalProperty pc_compat_6_1[] = {
105 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
106 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
107 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
108 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
109 };
110 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
111
112 GlobalProperty pc_compat_6_0[] = {
113 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
114 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
115 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
116 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
117 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
118 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
119 };
120 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
121
122 GlobalProperty pc_compat_5_2[] = {
123 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
124 };
125 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
126
127 GlobalProperty pc_compat_5_1[] = {
128 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
129 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
130 };
131 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
132
133 GlobalProperty pc_compat_5_0[] = {
134 };
135 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
136
137 GlobalProperty pc_compat_4_2[] = {
138 { "mch", "smbase-smram", "off" },
139 };
140 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
141
142 GlobalProperty pc_compat_4_1[] = {};
143 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
144
145 GlobalProperty pc_compat_4_0[] = {};
146 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
147
148 GlobalProperty pc_compat_3_1[] = {
149 { "intel-iommu", "dma-drain", "off" },
150 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
151 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
152 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
153 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
154 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
155 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
156 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
157 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
158 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
159 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
160 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
161 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
162 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
163 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
164 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
165 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
168 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
169 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
170 };
171 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
172
173 GlobalProperty pc_compat_3_0[] = {
174 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
175 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
176 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
177 };
178 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
179
180 GlobalProperty pc_compat_2_12[] = {
181 { TYPE_X86_CPU, "legacy-cache", "on" },
182 { TYPE_X86_CPU, "topoext", "off" },
183 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
184 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
185 };
186 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
187
188 GlobalProperty pc_compat_2_11[] = {
189 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
190 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
191 };
192 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
193
194 GlobalProperty pc_compat_2_10[] = {
195 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
196 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
197 { "q35-pcihost", "x-pci-hole64-fix", "off" },
198 };
199 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
200
201 GlobalProperty pc_compat_2_9[] = {
202 { "mch", "extended-tseg-mbytes", "0" },
203 };
204 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
205
206 GlobalProperty pc_compat_2_8[] = {
207 { TYPE_X86_CPU, "tcg-cpuid", "off" },
208 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
209 { "ICH9-LPC", "x-smi-broadcast", "off" },
210 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
211 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
212 };
213 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
214
215 GlobalProperty pc_compat_2_7[] = {
216 { TYPE_X86_CPU, "l3-cache", "off" },
217 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
218 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
219 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
220 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
221 { "isa-pcspk", "migrate", "off" },
222 };
223 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
224
225 GlobalProperty pc_compat_2_6[] = {
226 { TYPE_X86_CPU, "cpuid-0xb", "off" },
227 { "vmxnet3", "romfile", "" },
228 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
229 { "apic-common", "legacy-instance-id", "on", }
230 };
231 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
232
233 GlobalProperty pc_compat_2_5[] = {};
234 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
235
236 GlobalProperty pc_compat_2_4[] = {
237 PC_CPU_MODEL_IDS("2.4.0")
238 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
239 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
240 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
241 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
242 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
243 { TYPE_X86_CPU, "check", "off" },
244 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
245 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
246 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
247 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
248 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
249 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
250 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
251 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
252 };
253 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
254
255 GlobalProperty pc_compat_2_3[] = {
256 PC_CPU_MODEL_IDS("2.3.0")
257 { TYPE_X86_CPU, "arat", "off" },
258 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
259 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
260 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
261 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
262 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
263 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
264 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
265 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
266 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
267 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
268 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
276 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
277 };
278 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
279
280 GlobalProperty pc_compat_2_2[] = {
281 PC_CPU_MODEL_IDS("2.2.0")
282 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
283 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
284 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
285 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
286 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
287 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
288 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
297 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
298 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
299 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
300 };
301 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
302
303 GlobalProperty pc_compat_2_1[] = {
304 PC_CPU_MODEL_IDS("2.1.0")
305 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
306 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
307 };
308 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
309
310 GlobalProperty pc_compat_2_0[] = {
311 PC_CPU_MODEL_IDS("2.0.0")
312 { "virtio-scsi-pci", "any_layout", "off" },
313 { "PIIX4_PM", "memory-hotplug-support", "off" },
314 { "apic", "version", "0x11" },
315 { "nec-usb-xhci", "superspeed-ports-first", "off" },
316 { "nec-usb-xhci", "force-pcie-endcap", "on" },
317 { "pci-serial", "prog_if", "0" },
318 { "pci-serial-2x", "prog_if", "0" },
319 { "pci-serial-4x", "prog_if", "0" },
320 { "virtio-net-pci", "guest_announce", "off" },
321 { "ICH9-LPC", "memory-hotplug-support", "off" },
322 };
323 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
324
325 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
326 {
327 GSIState *s;
328
329 s = g_new0(GSIState, 1);
330 if (kvm_ioapic_in_kernel()) {
331 kvm_pc_setup_irq_routing(pci_enabled);
332 }
333 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
334
335 return s;
336 }
337
338 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
339 unsigned size)
340 {
341 }
342
343 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
344 {
345 return 0xffffffffffffffffULL;
346 }
347
348 /* MS-DOS compatibility mode FPU exception support */
349 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
350 unsigned size)
351 {
352 if (tcg_enabled()) {
353 cpu_set_ignne();
354 }
355 }
356
357 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
358 {
359 return 0xffffffffffffffffULL;
360 }
361
362 /* PC cmos mappings */
363
364 #define REG_EQUIPMENT_BYTE 0x14
365
366 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
367 int16_t cylinders, int8_t heads, int8_t sectors)
368 {
369 mc146818rtc_set_cmos_data(s, type_ofs, 47);
370 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
371 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
372 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
373 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
374 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
375 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
376 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
377 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
378 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
379 }
380
381 /* convert boot_device letter to something recognizable by the bios */
382 static int boot_device2nibble(char boot_device)
383 {
384 switch(boot_device) {
385 case 'a':
386 case 'b':
387 return 0x01; /* floppy boot */
388 case 'c':
389 return 0x02; /* hard drive boot */
390 case 'd':
391 return 0x03; /* CD-ROM boot */
392 case 'n':
393 return 0x04; /* Network boot */
394 }
395 return 0;
396 }
397
398 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
399 Error **errp)
400 {
401 #define PC_MAX_BOOT_DEVICES 3
402 int nbds, bds[3] = { 0, };
403 int i;
404
405 nbds = strlen(boot_device);
406 if (nbds > PC_MAX_BOOT_DEVICES) {
407 error_setg(errp, "Too many boot devices for PC");
408 return;
409 }
410 for (i = 0; i < nbds; i++) {
411 bds[i] = boot_device2nibble(boot_device[i]);
412 if (bds[i] == 0) {
413 error_setg(errp, "Invalid boot device for PC: '%c'",
414 boot_device[i]);
415 return;
416 }
417 }
418 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
419 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
420 }
421
422 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
423 {
424 set_boot_dev(opaque, boot_device, errp);
425 }
426
427 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
428 {
429 int val, nb, i;
430 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
431 FLOPPY_DRIVE_TYPE_NONE };
432
433 /* floppy type */
434 if (floppy) {
435 for (i = 0; i < 2; i++) {
436 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
437 }
438 }
439 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
440 cmos_get_fd_drive_type(fd_type[1]);
441 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
442
443 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
444 nb = 0;
445 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
446 nb++;
447 }
448 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
449 nb++;
450 }
451 switch (nb) {
452 case 0:
453 break;
454 case 1:
455 val |= 0x01; /* 1 drive, ready for boot */
456 break;
457 case 2:
458 val |= 0x41; /* 2 drives, ready for boot */
459 break;
460 }
461 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
462 }
463
464 typedef struct pc_cmos_init_late_arg {
465 MC146818RtcState *rtc_state;
466 BusState *idebus[2];
467 } pc_cmos_init_late_arg;
468
469 typedef struct check_fdc_state {
470 ISADevice *floppy;
471 bool multiple;
472 } CheckFdcState;
473
474 static int check_fdc(Object *obj, void *opaque)
475 {
476 CheckFdcState *state = opaque;
477 Object *fdc;
478 uint32_t iobase;
479 Error *local_err = NULL;
480
481 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
482 if (!fdc) {
483 return 0;
484 }
485
486 iobase = object_property_get_uint(obj, "iobase", &local_err);
487 if (local_err || iobase != 0x3f0) {
488 error_free(local_err);
489 return 0;
490 }
491
492 if (state->floppy) {
493 state->multiple = true;
494 } else {
495 state->floppy = ISA_DEVICE(obj);
496 }
497 return 0;
498 }
499
500 static const char * const fdc_container_path[] = {
501 "/unattached", "/peripheral", "/peripheral-anon"
502 };
503
504 /*
505 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
506 * and ACPI objects.
507 */
508 static ISADevice *pc_find_fdc0(void)
509 {
510 int i;
511 Object *container;
512 CheckFdcState state = { 0 };
513
514 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
515 container = container_get(qdev_get_machine(), fdc_container_path[i]);
516 object_child_foreach(container, check_fdc, &state);
517 }
518
519 if (state.multiple) {
520 warn_report("multiple floppy disk controllers with "
521 "iobase=0x3f0 have been found");
522 error_printf("the one being picked for CMOS setup might not reflect "
523 "your intent");
524 }
525
526 return state.floppy;
527 }
528
529 static void pc_cmos_init_late(void *opaque)
530 {
531 pc_cmos_init_late_arg *arg = opaque;
532 MC146818RtcState *s = arg->rtc_state;
533 int16_t cylinders;
534 int8_t heads, sectors;
535 int val;
536 int i, trans;
537
538 val = 0;
539 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
540 &cylinders, &heads, &sectors) >= 0) {
541 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
542 val |= 0xf0;
543 }
544 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
545 &cylinders, &heads, &sectors) >= 0) {
546 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
547 val |= 0x0f;
548 }
549 mc146818rtc_set_cmos_data(s, 0x12, val);
550
551 val = 0;
552 for (i = 0; i < 4; i++) {
553 /* NOTE: ide_get_geometry() returns the physical
554 geometry. It is always such that: 1 <= sects <= 63, 1
555 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
556 geometry can be different if a translation is done. */
557 if (arg->idebus[i / 2] &&
558 ide_get_geometry(arg->idebus[i / 2], i % 2,
559 &cylinders, &heads, &sectors) >= 0) {
560 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
561 assert((trans & ~3) == 0);
562 val |= trans << (i * 2);
563 }
564 }
565 mc146818rtc_set_cmos_data(s, 0x39, val);
566
567 pc_cmos_init_floppy(s, pc_find_fdc0());
568
569 qemu_unregister_reset(pc_cmos_init_late, opaque);
570 }
571
572 void pc_cmos_init(PCMachineState *pcms,
573 BusState *idebus0, BusState *idebus1,
574 ISADevice *rtc)
575 {
576 int val;
577 static pc_cmos_init_late_arg arg;
578 X86MachineState *x86ms = X86_MACHINE(pcms);
579 MC146818RtcState *s = MC146818_RTC(rtc);
580
581 /* various important CMOS locations needed by PC/Bochs bios */
582
583 /* memory size */
584 /* base memory (first MiB) */
585 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
586 mc146818rtc_set_cmos_data(s, 0x15, val);
587 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
588 /* extended memory (next 64MiB) */
589 if (x86ms->below_4g_mem_size > 1 * MiB) {
590 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
591 } else {
592 val = 0;
593 }
594 if (val > 65535)
595 val = 65535;
596 mc146818rtc_set_cmos_data(s, 0x17, val);
597 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
598 mc146818rtc_set_cmos_data(s, 0x30, val);
599 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
600 /* memory between 16MiB and 4GiB */
601 if (x86ms->below_4g_mem_size > 16 * MiB) {
602 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
603 } else {
604 val = 0;
605 }
606 if (val > 65535)
607 val = 65535;
608 mc146818rtc_set_cmos_data(s, 0x34, val);
609 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
610 /* memory above 4GiB */
611 val = x86ms->above_4g_mem_size / 65536;
612 mc146818rtc_set_cmos_data(s, 0x5b, val);
613 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
614 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
615
616 object_property_add_link(OBJECT(pcms), "rtc_state",
617 TYPE_ISA_DEVICE,
618 (Object **)&x86ms->rtc,
619 object_property_allow_set_link,
620 OBJ_PROP_LINK_STRONG);
621 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
622 &error_abort);
623
624 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
625
626 val = 0;
627 val |= 0x02; /* FPU is there */
628 val |= 0x04; /* PS/2 mouse installed */
629 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
630
631 /* hard drives and FDC */
632 arg.rtc_state = s;
633 arg.idebus[0] = idebus0;
634 arg.idebus[1] = idebus1;
635 qemu_register_reset(pc_cmos_init_late, &arg);
636 }
637
638 static void handle_a20_line_change(void *opaque, int irq, int level)
639 {
640 X86CPU *cpu = opaque;
641
642 /* XXX: send to all CPUs ? */
643 /* XXX: add logic to handle multiple A20 line sources */
644 x86_cpu_set_a20(cpu, level);
645 }
646
647 #define NE2000_NB_MAX 6
648
649 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
650 0x280, 0x380 };
651 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
652
653 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
654 {
655 static int nb_ne2k = 0;
656
657 if (nb_ne2k == NE2000_NB_MAX)
658 return;
659 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
660 ne2000_irq[nb_ne2k], nd);
661 nb_ne2k++;
662 }
663
664 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
665 {
666 X86CPU *cpu = opaque;
667
668 if (level) {
669 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
670 }
671 }
672
673 static
674 void pc_machine_done(Notifier *notifier, void *data)
675 {
676 PCMachineState *pcms = container_of(notifier,
677 PCMachineState, machine_done);
678 X86MachineState *x86ms = X86_MACHINE(pcms);
679
680 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
681 &error_fatal);
682
683 if (pcms->cxl_devices_state.is_enabled) {
684 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
685 }
686
687 /* set the number of CPUs */
688 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
689
690 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
691
692 acpi_setup();
693 if (x86ms->fw_cfg) {
694 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
695 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
696 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
697 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
698 }
699 }
700
701 void pc_guest_info_init(PCMachineState *pcms)
702 {
703 X86MachineState *x86ms = X86_MACHINE(pcms);
704
705 x86ms->apic_xrupt_override = true;
706 pcms->machine_done.notify = pc_machine_done;
707 qemu_add_machine_init_done_notifier(&pcms->machine_done);
708 }
709
710 /* setup pci memory address space mapping into system address space */
711 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
712 MemoryRegion *pci_address_space)
713 {
714 /* Set to lower priority than RAM */
715 memory_region_add_subregion_overlap(system_memory, 0x0,
716 pci_address_space, -1);
717 }
718
719 void xen_load_linux(PCMachineState *pcms)
720 {
721 int i;
722 FWCfgState *fw_cfg;
723 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
724 X86MachineState *x86ms = X86_MACHINE(pcms);
725
726 assert(MACHINE(pcms)->kernel_filename != NULL);
727
728 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
729 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
730 rom_set_fw(fw_cfg);
731
732 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
733 pcmc->pvh_enabled);
734 for (i = 0; i < nb_option_roms; i++) {
735 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
736 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
737 !strcmp(option_rom[i].name, "pvh.bin") ||
738 !strcmp(option_rom[i].name, "multiboot.bin") ||
739 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
740 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
741 }
742 x86ms->fw_cfg = fw_cfg;
743 }
744
745 #define PC_ROM_MIN_VGA 0xc0000
746 #define PC_ROM_MIN_OPTION 0xc8000
747 #define PC_ROM_MAX 0xe0000
748 #define PC_ROM_ALIGN 0x800
749 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
750
751 static hwaddr pc_above_4g_end(PCMachineState *pcms)
752 {
753 X86MachineState *x86ms = X86_MACHINE(pcms);
754
755 if (pcms->sgx_epc.size != 0) {
756 return sgx_epc_above_4g_end(&pcms->sgx_epc);
757 }
758
759 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
760 }
761
762 static void pc_get_device_memory_range(PCMachineState *pcms,
763 hwaddr *base,
764 ram_addr_t *device_mem_size)
765 {
766 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
767 MachineState *machine = MACHINE(pcms);
768 ram_addr_t size;
769 hwaddr addr;
770
771 size = machine->maxram_size - machine->ram_size;
772 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
773
774 if (pcmc->enforce_aligned_dimm) {
775 /* size device region assuming 1G page max alignment per slot */
776 size += (1 * GiB) * machine->ram_slots;
777 }
778
779 *base = addr;
780 *device_mem_size = size;
781 }
782
783 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
784 {
785 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
786 MachineState *ms = MACHINE(pcms);
787 hwaddr cxl_base;
788 ram_addr_t size;
789
790 if (pcmc->has_reserved_memory &&
791 (ms->ram_size < ms->maxram_size)) {
792 pc_get_device_memory_range(pcms, &cxl_base, &size);
793 cxl_base += size;
794 } else {
795 cxl_base = pc_above_4g_end(pcms);
796 }
797
798 return cxl_base;
799 }
800
801 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
802 {
803 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
804
805 if (pcms->cxl_devices_state.fixed_windows) {
806 GList *it;
807
808 start = ROUND_UP(start, 256 * MiB);
809 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
810 CXLFixedWindow *fw = it->data;
811 start += fw->size;
812 }
813 }
814
815 return start;
816 }
817
818 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
819 {
820 X86CPU *cpu = X86_CPU(first_cpu);
821 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
822 MachineState *ms = MACHINE(pcms);
823
824 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
825 /* 64-bit systems */
826 return pc_pci_hole64_start() + pci_hole64_size - 1;
827 }
828
829 /* 32-bit systems */
830 if (pcmc->broken_32bit_mem_addr_check) {
831 /* old value for compatibility reasons */
832 return ((hwaddr)1 << cpu->phys_bits) - 1;
833 }
834
835 /*
836 * 32-bit systems don't have hole64 but they might have a region for
837 * memory devices. Even if additional hotplugged memory devices might
838 * not be usable by most guest OSes, we need to still consider them for
839 * calculating the highest possible GPA so that we can properly report
840 * if someone configures them on a CPU that cannot possibly address them.
841 */
842 if (pcmc->has_reserved_memory &&
843 (ms->ram_size < ms->maxram_size)) {
844 hwaddr devmem_start;
845 ram_addr_t devmem_size;
846
847 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
848 devmem_start += devmem_size;
849 return devmem_start - 1;
850 }
851
852 /* configuration without any memory hotplug */
853 return pc_above_4g_end(pcms) - 1;
854 }
855
856 /*
857 * AMD systems with an IOMMU have an additional hole close to the
858 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
859 * on kernel version, VFIO may or may not let you DMA map those ranges.
860 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
861 * with certain memory sizes. It's also wrong to use those IOVA ranges
862 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
863 * The ranges reserved for Hyper-Transport are:
864 *
865 * FD_0000_0000h - FF_FFFF_FFFFh
866 *
867 * The ranges represent the following:
868 *
869 * Base Address Top Address Use
870 *
871 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
872 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
873 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
874 * FD_F910_0000h FD_F91F_FFFFh System Management
875 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
876 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
877 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
878 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
879 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
880 * FE_2000_0000h FF_FFFF_FFFFh Reserved
881 *
882 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
883 * Table 3: Special Address Controls (GPA) for more information.
884 */
885 #define AMD_HT_START 0xfd00000000UL
886 #define AMD_HT_END 0xffffffffffUL
887 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
888 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
889
890 void pc_memory_init(PCMachineState *pcms,
891 MemoryRegion *system_memory,
892 MemoryRegion *rom_memory,
893 uint64_t pci_hole64_size)
894 {
895 int linux_boot, i;
896 MemoryRegion *option_rom_mr;
897 MemoryRegion *ram_below_4g, *ram_above_4g;
898 FWCfgState *fw_cfg;
899 MachineState *machine = MACHINE(pcms);
900 MachineClass *mc = MACHINE_GET_CLASS(machine);
901 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
902 X86MachineState *x86ms = X86_MACHINE(pcms);
903 hwaddr maxphysaddr, maxusedaddr;
904 hwaddr cxl_base, cxl_resv_end = 0;
905 X86CPU *cpu = X86_CPU(first_cpu);
906
907 assert(machine->ram_size == x86ms->below_4g_mem_size +
908 x86ms->above_4g_mem_size);
909
910 linux_boot = (machine->kernel_filename != NULL);
911
912 /*
913 * The HyperTransport range close to the 1T boundary is unique to AMD
914 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
915 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
916 * older machine types (<= 7.0) for compatibility purposes.
917 */
918 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
919 /* Bail out if max possible address does not cross HT range */
920 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
921 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
922 }
923
924 /*
925 * Advertise the HT region if address space covers the reserved
926 * region or if we relocate.
927 */
928 if (cpu->phys_bits >= 40) {
929 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
930 }
931 }
932
933 /*
934 * phys-bits is required to be appropriately configured
935 * to make sure max used GPA is reachable.
936 */
937 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
938 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
939 if (maxphysaddr < maxusedaddr) {
940 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
941 " phys-bits too low (%u)",
942 maxphysaddr, maxusedaddr, cpu->phys_bits);
943 exit(EXIT_FAILURE);
944 }
945
946 /*
947 * Split single memory region and use aliases to address portions of it,
948 * done for backwards compatibility with older qemus.
949 */
950 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
951 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
952 0, x86ms->below_4g_mem_size);
953 memory_region_add_subregion(system_memory, 0, ram_below_4g);
954 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
955 if (x86ms->above_4g_mem_size > 0) {
956 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
957 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
958 machine->ram,
959 x86ms->below_4g_mem_size,
960 x86ms->above_4g_mem_size);
961 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
962 ram_above_4g);
963 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
964 E820_RAM);
965 }
966
967 if (pcms->sgx_epc.size != 0) {
968 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
969 }
970
971 if (!pcmc->has_reserved_memory &&
972 (machine->ram_slots ||
973 (machine->maxram_size > machine->ram_size))) {
974
975 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
976 mc->name);
977 exit(EXIT_FAILURE);
978 }
979
980 /* initialize device memory address space */
981 if (pcmc->has_reserved_memory &&
982 (machine->ram_size < machine->maxram_size)) {
983 ram_addr_t device_mem_size;
984 hwaddr device_mem_base;
985
986 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
987 error_report("unsupported amount of memory slots: %"PRIu64,
988 machine->ram_slots);
989 exit(EXIT_FAILURE);
990 }
991
992 if (QEMU_ALIGN_UP(machine->maxram_size,
993 TARGET_PAGE_SIZE) != machine->maxram_size) {
994 error_report("maximum memory size must by aligned to multiple of "
995 "%d bytes", TARGET_PAGE_SIZE);
996 exit(EXIT_FAILURE);
997 }
998
999 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
1000
1001 if (device_mem_base + device_mem_size < device_mem_size) {
1002 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1003 machine->maxram_size);
1004 exit(EXIT_FAILURE);
1005 }
1006 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
1007 }
1008
1009 if (pcms->cxl_devices_state.is_enabled) {
1010 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1011 hwaddr cxl_size = MiB;
1012
1013 cxl_base = pc_get_cxl_range_start(pcms);
1014 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1015 memory_region_add_subregion(system_memory, cxl_base, mr);
1016 cxl_resv_end = cxl_base + cxl_size;
1017 if (pcms->cxl_devices_state.fixed_windows) {
1018 hwaddr cxl_fmw_base;
1019 GList *it;
1020
1021 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1022 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1023 CXLFixedWindow *fw = it->data;
1024
1025 fw->base = cxl_fmw_base;
1026 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1027 "cxl-fixed-memory-region", fw->size);
1028 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1029 cxl_fmw_base += fw->size;
1030 cxl_resv_end = cxl_fmw_base;
1031 }
1032 }
1033 }
1034
1035 /* Initialize PC system firmware */
1036 pc_system_firmware_init(pcms, rom_memory);
1037
1038 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1039 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1040 &error_fatal);
1041 if (pcmc->pci_enabled) {
1042 memory_region_set_readonly(option_rom_mr, true);
1043 }
1044 memory_region_add_subregion_overlap(rom_memory,
1045 PC_ROM_MIN_VGA,
1046 option_rom_mr,
1047 1);
1048
1049 fw_cfg = fw_cfg_arch_create(machine,
1050 x86ms->boot_cpus, x86ms->apic_id_limit);
1051
1052 rom_set_fw(fw_cfg);
1053
1054 if (machine->device_memory) {
1055 uint64_t *val = g_malloc(sizeof(*val));
1056 uint64_t res_mem_end = machine->device_memory->base;
1057
1058 if (!pcmc->broken_reserved_end) {
1059 res_mem_end += memory_region_size(&machine->device_memory->mr);
1060 }
1061
1062 if (pcms->cxl_devices_state.is_enabled) {
1063 res_mem_end = cxl_resv_end;
1064 }
1065 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1066 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1067 }
1068
1069 if (linux_boot) {
1070 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1071 pcmc->pvh_enabled);
1072 }
1073
1074 for (i = 0; i < nb_option_roms; i++) {
1075 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1076 }
1077 x86ms->fw_cfg = fw_cfg;
1078
1079 /* Init default IOAPIC address space */
1080 x86ms->ioapic_as = &address_space_memory;
1081
1082 /* Init ACPI memory hotplug IO base address */
1083 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1084 }
1085
1086 /*
1087 * The 64bit pci hole starts after "above 4G RAM" and
1088 * potentially the space reserved for memory hotplug.
1089 */
1090 uint64_t pc_pci_hole64_start(void)
1091 {
1092 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1093 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1094 MachineState *ms = MACHINE(pcms);
1095 uint64_t hole64_start = 0;
1096 ram_addr_t size = 0;
1097
1098 if (pcms->cxl_devices_state.is_enabled) {
1099 hole64_start = pc_get_cxl_range_end(pcms);
1100 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1101 pc_get_device_memory_range(pcms, &hole64_start, &size);
1102 if (!pcmc->broken_reserved_end) {
1103 hole64_start += size;
1104 }
1105 } else {
1106 hole64_start = pc_above_4g_end(pcms);
1107 }
1108
1109 return ROUND_UP(hole64_start, 1 * GiB);
1110 }
1111
1112 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1113 {
1114 DeviceState *dev = NULL;
1115
1116 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1117 if (pci_bus) {
1118 PCIDevice *pcidev = pci_vga_init(pci_bus);
1119 dev = pcidev ? &pcidev->qdev : NULL;
1120 } else if (isa_bus) {
1121 ISADevice *isadev = isa_vga_init(isa_bus);
1122 dev = isadev ? DEVICE(isadev) : NULL;
1123 }
1124 rom_reset_order_override();
1125 return dev;
1126 }
1127
1128 static const MemoryRegionOps ioport80_io_ops = {
1129 .write = ioport80_write,
1130 .read = ioport80_read,
1131 .endianness = DEVICE_NATIVE_ENDIAN,
1132 .impl = {
1133 .min_access_size = 1,
1134 .max_access_size = 1,
1135 },
1136 };
1137
1138 static const MemoryRegionOps ioportF0_io_ops = {
1139 .write = ioportF0_write,
1140 .read = ioportF0_read,
1141 .endianness = DEVICE_NATIVE_ENDIAN,
1142 .impl = {
1143 .min_access_size = 1,
1144 .max_access_size = 1,
1145 },
1146 };
1147
1148 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1149 bool create_i8042, bool no_vmport)
1150 {
1151 int i;
1152 DriveInfo *fd[MAX_FD];
1153 qemu_irq *a20_line;
1154 ISADevice *fdc, *i8042, *port92, *vmmouse;
1155
1156 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1157 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1158
1159 for (i = 0; i < MAX_FD; i++) {
1160 fd[i] = drive_get(IF_FLOPPY, 0, i);
1161 create_fdctrl |= !!fd[i];
1162 }
1163 if (create_fdctrl) {
1164 fdc = isa_new(TYPE_ISA_FDC);
1165 if (fdc) {
1166 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1167 isa_fdc_init_drives(fdc, fd);
1168 }
1169 }
1170
1171 if (!create_i8042) {
1172 return;
1173 }
1174
1175 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1176 if (!no_vmport) {
1177 isa_create_simple(isa_bus, TYPE_VMPORT);
1178 vmmouse = isa_try_new("vmmouse");
1179 } else {
1180 vmmouse = NULL;
1181 }
1182 if (vmmouse) {
1183 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1184 &error_abort);
1185 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1186 }
1187 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1188
1189 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1190 i8042_setup_a20_line(i8042, a20_line[0]);
1191 qdev_connect_gpio_out_named(DEVICE(port92),
1192 PORT92_A20_LINE, 0, a20_line[1]);
1193 g_free(a20_line);
1194 }
1195
1196 void pc_basic_device_init(struct PCMachineState *pcms,
1197 ISABus *isa_bus, qemu_irq *gsi,
1198 ISADevice *rtc_state,
1199 bool create_fdctrl,
1200 uint32_t hpet_irqs)
1201 {
1202 int i;
1203 DeviceState *hpet = NULL;
1204 int pit_isa_irq = 0;
1205 qemu_irq pit_alt_irq = NULL;
1206 ISADevice *pit = NULL;
1207 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1208 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1209 X86MachineState *x86ms = X86_MACHINE(pcms);
1210
1211 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1212 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1213
1214 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1215 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1216
1217 /*
1218 * Check if an HPET shall be created.
1219 */
1220 if (pcms->hpet_enabled) {
1221 qemu_irq rtc_irq;
1222
1223 hpet = qdev_try_new(TYPE_HPET);
1224 if (!hpet) {
1225 error_report("couldn't create HPET device");
1226 exit(1);
1227 }
1228 /*
1229 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1230 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1231 * the property, use whatever mask they specified.
1232 */
1233 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1234 HPET_INTCAP, NULL);
1235 if (!compat) {
1236 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1237 }
1238 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1239 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1240
1241 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1242 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1243 }
1244 pit_isa_irq = -1;
1245 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1246 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1247
1248 /* overwrite connection created by south bridge */
1249 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1250 }
1251
1252 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1253 "date");
1254
1255 #ifdef CONFIG_XEN_EMU
1256 if (xen_mode == XEN_EMULATE) {
1257 xen_overlay_create();
1258 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1259 xen_gnttab_create();
1260 xen_xenstore_create();
1261 if (pcms->bus) {
1262 pci_create_simple(pcms->bus, -1, "xen-platform");
1263 }
1264 pcms->xenbus = xen_bus_init();
1265 xen_be_init();
1266 }
1267 #endif
1268
1269 qemu_register_boot_set(pc_boot_set, rtc_state);
1270
1271 if (!xen_enabled() &&
1272 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1273 if (kvm_pit_in_kernel()) {
1274 pit = kvm_pit_init(isa_bus, 0x40);
1275 } else {
1276 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1277 }
1278 if (hpet) {
1279 /* connect PIT to output control line of the HPET */
1280 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1281 }
1282 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1283 OBJECT(pit), &error_fatal);
1284 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1285 }
1286
1287 /* Super I/O */
1288 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1289 pcms->vmport != ON_OFF_AUTO_ON);
1290 }
1291
1292 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus,
1293 BusState *xen_bus)
1294 {
1295 MachineClass *mc = MACHINE_CLASS(pcmc);
1296 int i;
1297
1298 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1299 for (i = 0; i < nb_nics; i++) {
1300 NICInfo *nd = &nd_table[i];
1301 const char *model = nd->model ? nd->model : mc->default_nic;
1302
1303 if (xen_bus && (!nd->model || g_str_equal(model, "xen-net-device"))) {
1304 DeviceState *dev = qdev_new("xen-net-device");
1305 qdev_set_nic_properties(dev, nd);
1306 qdev_realize_and_unref(dev, xen_bus, &error_fatal);
1307 } else if (g_str_equal(model, "ne2k_isa")) {
1308 pc_init_ne2k_isa(isa_bus, nd);
1309 } else {
1310 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1311 }
1312 }
1313 rom_reset_order_override();
1314 }
1315
1316 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1317 {
1318 qemu_irq *i8259;
1319
1320 if (kvm_pic_in_kernel()) {
1321 i8259 = kvm_i8259_init(isa_bus);
1322 } else if (xen_enabled()) {
1323 i8259 = xen_interrupt_controller_init();
1324 } else {
1325 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1326 }
1327
1328 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1329 i8259_irqs[i] = i8259[i];
1330 }
1331
1332 g_free(i8259);
1333 }
1334
1335 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1336 Error **errp)
1337 {
1338 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1339 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1340 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1341 const MachineState *ms = MACHINE(hotplug_dev);
1342 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1343 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1344 Error *local_err = NULL;
1345
1346 /*
1347 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1348 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1349 * addition to cover this case.
1350 */
1351 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1352 error_setg(errp,
1353 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1354 return;
1355 }
1356
1357 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1358 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1359 return;
1360 }
1361
1362 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1363 if (local_err) {
1364 error_propagate(errp, local_err);
1365 return;
1366 }
1367
1368 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1369 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1370 }
1371
1372 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1373 DeviceState *dev, Error **errp)
1374 {
1375 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1376 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1377 MachineState *ms = MACHINE(hotplug_dev);
1378 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1379
1380 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1381
1382 if (is_nvdimm) {
1383 nvdimm_plug(ms->nvdimms_state);
1384 }
1385
1386 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1387 }
1388
1389 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1390 DeviceState *dev, Error **errp)
1391 {
1392 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1393
1394 /*
1395 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1396 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1397 * addition to cover this case.
1398 */
1399 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1400 error_setg(errp,
1401 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1402 return;
1403 }
1404
1405 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1406 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1407 return;
1408 }
1409
1410 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1411 errp);
1412 }
1413
1414 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1415 DeviceState *dev, Error **errp)
1416 {
1417 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1418 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1419 Error *local_err = NULL;
1420
1421 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1422 if (local_err) {
1423 goto out;
1424 }
1425
1426 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1427 qdev_unrealize(dev);
1428 out:
1429 error_propagate(errp, local_err);
1430 }
1431
1432 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1433 DeviceState *dev, Error **errp)
1434 {
1435 /* The vmbus handler has no hotplug handler; we should never end up here. */
1436 g_assert(!dev->hotplugged);
1437 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1438 errp);
1439 }
1440
1441 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1442 DeviceState *dev, Error **errp)
1443 {
1444 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1445 }
1446
1447 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1448 DeviceState *dev, Error **errp)
1449 {
1450 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1451 pc_memory_pre_plug(hotplug_dev, dev, errp);
1452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1453 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1455 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1457 /* Declare the APIC range as the reserved MSI region */
1458 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1459 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1460
1461 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1462 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1463 resv_prop_str, errp);
1464 g_free(resv_prop_str);
1465 }
1466
1467 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1468 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1469 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1470
1471 if (pcms->iommu) {
1472 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1473 "for x86 yet.");
1474 return;
1475 }
1476 pcms->iommu = dev;
1477 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1478 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1479 }
1480 }
1481
1482 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1483 DeviceState *dev, Error **errp)
1484 {
1485 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1486 pc_memory_plug(hotplug_dev, dev, errp);
1487 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1488 x86_cpu_plug(hotplug_dev, dev, errp);
1489 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1490 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1491 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1492 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1493 }
1494 }
1495
1496 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1497 DeviceState *dev, Error **errp)
1498 {
1499 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1500 pc_memory_unplug_request(hotplug_dev, dev, errp);
1501 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1502 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1503 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1504 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1505 errp);
1506 } else {
1507 error_setg(errp, "acpi: device unplug request for not supported device"
1508 " type: %s", object_get_typename(OBJECT(dev)));
1509 }
1510 }
1511
1512 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1513 DeviceState *dev, Error **errp)
1514 {
1515 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1516 pc_memory_unplug(hotplug_dev, dev, errp);
1517 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1518 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1519 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1520 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1521 } else {
1522 error_setg(errp, "acpi: device unplug for not supported device"
1523 " type: %s", object_get_typename(OBJECT(dev)));
1524 }
1525 }
1526
1527 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1528 DeviceState *dev)
1529 {
1530 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1531 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1532 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1533 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1534 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1535 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1536 return HOTPLUG_HANDLER(machine);
1537 }
1538
1539 return NULL;
1540 }
1541
1542 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1543 void *opaque, Error **errp)
1544 {
1545 PCMachineState *pcms = PC_MACHINE(obj);
1546 OnOffAuto vmport = pcms->vmport;
1547
1548 visit_type_OnOffAuto(v, name, &vmport, errp);
1549 }
1550
1551 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1552 void *opaque, Error **errp)
1553 {
1554 PCMachineState *pcms = PC_MACHINE(obj);
1555
1556 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1557 }
1558
1559 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1560 {
1561 PCMachineState *pcms = PC_MACHINE(obj);
1562
1563 return pcms->smbus_enabled;
1564 }
1565
1566 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1567 {
1568 PCMachineState *pcms = PC_MACHINE(obj);
1569
1570 pcms->smbus_enabled = value;
1571 }
1572
1573 static bool pc_machine_get_sata(Object *obj, Error **errp)
1574 {
1575 PCMachineState *pcms = PC_MACHINE(obj);
1576
1577 return pcms->sata_enabled;
1578 }
1579
1580 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1581 {
1582 PCMachineState *pcms = PC_MACHINE(obj);
1583
1584 pcms->sata_enabled = value;
1585 }
1586
1587 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1588 {
1589 PCMachineState *pcms = PC_MACHINE(obj);
1590
1591 return pcms->hpet_enabled;
1592 }
1593
1594 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1595 {
1596 PCMachineState *pcms = PC_MACHINE(obj);
1597
1598 pcms->hpet_enabled = value;
1599 }
1600
1601 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1602 {
1603 PCMachineState *pcms = PC_MACHINE(obj);
1604
1605 return pcms->i8042_enabled;
1606 }
1607
1608 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1609 {
1610 PCMachineState *pcms = PC_MACHINE(obj);
1611
1612 pcms->i8042_enabled = value;
1613 }
1614
1615 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1616 {
1617 PCMachineState *pcms = PC_MACHINE(obj);
1618
1619 return pcms->default_bus_bypass_iommu;
1620 }
1621
1622 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1623 Error **errp)
1624 {
1625 PCMachineState *pcms = PC_MACHINE(obj);
1626
1627 pcms->default_bus_bypass_iommu = value;
1628 }
1629
1630 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1631 void *opaque, Error **errp)
1632 {
1633 PCMachineState *pcms = PC_MACHINE(obj);
1634 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1635
1636 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1637 }
1638
1639 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1640 void *opaque, Error **errp)
1641 {
1642 PCMachineState *pcms = PC_MACHINE(obj);
1643
1644 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1645 }
1646
1647 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1648 const char *name, void *opaque,
1649 Error **errp)
1650 {
1651 PCMachineState *pcms = PC_MACHINE(obj);
1652 uint64_t value = pcms->max_ram_below_4g;
1653
1654 visit_type_size(v, name, &value, errp);
1655 }
1656
1657 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1658 const char *name, void *opaque,
1659 Error **errp)
1660 {
1661 PCMachineState *pcms = PC_MACHINE(obj);
1662 uint64_t value;
1663
1664 if (!visit_type_size(v, name, &value, errp)) {
1665 return;
1666 }
1667 if (value > 4 * GiB) {
1668 error_setg(errp,
1669 "Machine option 'max-ram-below-4g=%"PRIu64
1670 "' expects size less than or equal to 4G", value);
1671 return;
1672 }
1673
1674 if (value < 1 * MiB) {
1675 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1676 "BIOS may not work with less than 1MiB", value);
1677 }
1678
1679 pcms->max_ram_below_4g = value;
1680 }
1681
1682 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1683 const char *name, void *opaque,
1684 Error **errp)
1685 {
1686 PCMachineState *pcms = PC_MACHINE(obj);
1687 uint64_t value = pcms->max_fw_size;
1688
1689 visit_type_size(v, name, &value, errp);
1690 }
1691
1692 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1693 const char *name, void *opaque,
1694 Error **errp)
1695 {
1696 PCMachineState *pcms = PC_MACHINE(obj);
1697 uint64_t value;
1698
1699 if (!visit_type_size(v, name, &value, errp)) {
1700 return;
1701 }
1702
1703 /*
1704 * We don't have a theoretically justifiable exact lower bound on the base
1705 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1706 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1707 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1708 * 16MiB in size.
1709 */
1710 if (value > 16 * MiB) {
1711 error_setg(errp,
1712 "User specified max allowed firmware size %" PRIu64 " is "
1713 "greater than 16MiB. If combined firmware size exceeds "
1714 "16MiB the system may not boot, or experience intermittent"
1715 "stability issues.",
1716 value);
1717 return;
1718 }
1719
1720 pcms->max_fw_size = value;
1721 }
1722
1723
1724 static void pc_machine_initfn(Object *obj)
1725 {
1726 PCMachineState *pcms = PC_MACHINE(obj);
1727 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1728
1729 #ifdef CONFIG_VMPORT
1730 pcms->vmport = ON_OFF_AUTO_AUTO;
1731 #else
1732 pcms->vmport = ON_OFF_AUTO_OFF;
1733 #endif /* CONFIG_VMPORT */
1734 pcms->max_ram_below_4g = 0; /* use default */
1735 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1736 pcms->south_bridge = pcmc->default_south_bridge;
1737
1738 /* acpi build is enabled by default if machine supports it */
1739 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1740 pcms->smbus_enabled = true;
1741 pcms->sata_enabled = true;
1742 pcms->i8042_enabled = true;
1743 pcms->max_fw_size = 8 * MiB;
1744 #ifdef CONFIG_HPET
1745 pcms->hpet_enabled = true;
1746 #endif
1747 pcms->default_bus_bypass_iommu = false;
1748
1749 pc_system_flash_create(pcms);
1750 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1751 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1752 OBJECT(pcms->pcspk), "audiodev");
1753 cxl_machine_init(obj, &pcms->cxl_devices_state);
1754 }
1755
1756 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1757 {
1758 return 0;
1759 }
1760
1761 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1762 {
1763 CPUState *cs;
1764 X86CPU *cpu;
1765
1766 qemu_devices_reset(reason);
1767
1768 /* Reset APIC after devices have been reset to cancel
1769 * any changes that qemu_devices_reset() might have done.
1770 */
1771 CPU_FOREACH(cs) {
1772 cpu = X86_CPU(cs);
1773
1774 x86_cpu_after_reset(cpu);
1775 }
1776 }
1777
1778 static void pc_machine_wakeup(MachineState *machine)
1779 {
1780 cpu_synchronize_all_states();
1781 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1782 cpu_synchronize_all_post_reset();
1783 }
1784
1785 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1786 {
1787 X86IOMMUState *iommu = x86_iommu_get_default();
1788 IntelIOMMUState *intel_iommu;
1789
1790 if (iommu &&
1791 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1792 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1793 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1794 if (!intel_iommu->caching_mode) {
1795 error_setg(errp, "Device assignment is not allowed without "
1796 "enabling caching-mode=on for Intel IOMMU.");
1797 return false;
1798 }
1799 }
1800
1801 return true;
1802 }
1803
1804 static void pc_machine_class_init(ObjectClass *oc, void *data)
1805 {
1806 MachineClass *mc = MACHINE_CLASS(oc);
1807 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1808 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1809
1810 pcmc->pci_enabled = true;
1811 pcmc->has_acpi_build = true;
1812 pcmc->rsdp_in_ram = true;
1813 pcmc->smbios_defaults = true;
1814 pcmc->smbios_uuid_encoded = true;
1815 pcmc->gigabyte_align = true;
1816 pcmc->has_reserved_memory = true;
1817 pcmc->kvmclock_enabled = true;
1818 pcmc->enforce_aligned_dimm = true;
1819 pcmc->enforce_amd_1tb_hole = true;
1820 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1821 * to be used at the moment, 32K should be enough for a while. */
1822 pcmc->acpi_data_size = 0x20000 + 0x8000;
1823 pcmc->pvh_enabled = true;
1824 pcmc->kvmclock_create_always = true;
1825 pcmc->resizable_acpi_blob = true;
1826 assert(!mc->get_hotplug_handler);
1827 mc->get_hotplug_handler = pc_get_hotplug_handler;
1828 mc->hotplug_allowed = pc_hotplug_allowed;
1829 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1830 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1831 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1832 mc->auto_enable_numa_with_memhp = true;
1833 mc->auto_enable_numa_with_memdev = true;
1834 mc->has_hotpluggable_cpus = true;
1835 mc->default_boot_order = "cad";
1836 mc->block_default_type = IF_IDE;
1837 mc->max_cpus = 255;
1838 mc->reset = pc_machine_reset;
1839 mc->wakeup = pc_machine_wakeup;
1840 hc->pre_plug = pc_machine_device_pre_plug_cb;
1841 hc->plug = pc_machine_device_plug_cb;
1842 hc->unplug_request = pc_machine_device_unplug_request_cb;
1843 hc->unplug = pc_machine_device_unplug_cb;
1844 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1845 mc->nvdimm_supported = true;
1846 mc->smp_props.dies_supported = true;
1847 mc->default_ram_id = "pc.ram";
1848 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1849
1850 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1851 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1852 NULL, NULL);
1853 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1854 "Maximum ram below the 4G boundary (32bit boundary)");
1855
1856 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1857 pc_machine_get_vmport, pc_machine_set_vmport,
1858 NULL, NULL);
1859 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1860 "Enable vmport (pc & q35)");
1861
1862 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1863 pc_machine_get_smbus, pc_machine_set_smbus);
1864 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1865 "Enable/disable system management bus");
1866
1867 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1868 pc_machine_get_sata, pc_machine_set_sata);
1869 object_class_property_set_description(oc, PC_MACHINE_SATA,
1870 "Enable/disable Serial ATA bus");
1871
1872 object_class_property_add_bool(oc, "hpet",
1873 pc_machine_get_hpet, pc_machine_set_hpet);
1874 object_class_property_set_description(oc, "hpet",
1875 "Enable/disable high precision event timer emulation");
1876
1877 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1878 pc_machine_get_i8042, pc_machine_set_i8042);
1879
1880 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1881 pc_machine_get_default_bus_bypass_iommu,
1882 pc_machine_set_default_bus_bypass_iommu);
1883
1884 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1885 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1886 NULL, NULL);
1887 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1888 "Maximum combined firmware size");
1889
1890 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1891 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1892 NULL, NULL);
1893 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1894 "SMBIOS Entry Point type [32, 64]");
1895 }
1896
1897 static const TypeInfo pc_machine_info = {
1898 .name = TYPE_PC_MACHINE,
1899 .parent = TYPE_X86_MACHINE,
1900 .abstract = true,
1901 .instance_size = sizeof(PCMachineState),
1902 .instance_init = pc_machine_initfn,
1903 .class_size = sizeof(PCMachineClass),
1904 .class_init = pc_machine_class_init,
1905 .interfaces = (InterfaceInfo[]) {
1906 { TYPE_HOTPLUG_HANDLER },
1907 { }
1908 },
1909 };
1910
1911 static void pc_machine_register_types(void)
1912 {
1913 type_register_static(&pc_machine_info);
1914 }
1915
1916 type_init(pc_machine_register_types)
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