hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/i386/x86.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "hw/i386/fw_cfg.h"
  34 #include "sysemu/cpus.h"
  35 #include "hw/block/fdc.h"
  36 #include "hw/ide.h"
  37 #include "hw/pci/pci.h"
  38 #include "hw/pci/pci_bus.h"
  39 #include "hw/nvram/fw_cfg.h"
  40 #include "hw/timer/hpet.h"
  41 #include "hw/firmware/smbios.h"
  42 #include "hw/loader.h"
  43 #include "elf.h"
  44 #include "migration/vmstate.h"
  45 #include "multiboot.h"
  46 #include "hw/rtc/mc146818rtc.h"
  47 #include "hw/intc/i8259.h"
  48 #include "hw/dma/i8257.h"
  49 #include "hw/timer/i8254.h"
  50 #include "hw/input/i8042.h"
  51 #include "hw/irq.h"
  52 #include "hw/audio/pcspk.h"
  53 #include "hw/pci/msi.h"
  54 #include "hw/sysbus.h"
  55 #include "sysemu/sysemu.h"
  56 #include "sysemu/tcg.h"
  57 #include "sysemu/numa.h"
  58 #include "sysemu/kvm.h"
  59 #include "sysemu/qtest.h"
  60 #include "sysemu/reset.h"
  61 #include "sysemu/runstate.h"
  62 #include "kvm_i386.h"
  63 #include "hw/xen/xen.h"
  64 #include "hw/xen/start_info.h"
  65 #include "ui/qemu-spice.h"
  66 #include "exec/memory.h"
  67 #include "exec/address-spaces.h"
  68 #include "sysemu/arch_init.h"
  69 #include "qemu/bitmap.h"
  70 #include "qemu/config-file.h"
  71 #include "qemu/error-report.h"
  72 #include "qemu/option.h"
  73 #include "qemu/cutils.h"
  74 #include "hw/acpi/acpi.h"
  75 #include "hw/acpi/cpu_hotplug.h"
  76 #include "hw/boards.h"
  77 #include "acpi-build.h"
  78 #include "hw/mem/pc-dimm.h"
  79 #include "qapi/error.h"
  80 #include "qapi/qapi-visit-common.h"
  81 #include "qapi/visitor.h"
  82 #include "hw/core/cpu.h"
  83 #include "hw/usb.h"
  84 #include "hw/i386/intel_iommu.h"
  85 #include "hw/net/ne2000-isa.h"
  86 #include "standard-headers/asm-x86/bootparam.h"
  87 #include "hw/virtio/virtio-pmem-pci.h"
  88 #include "hw/mem/memory-device.h"
  89 #include "sysemu/replay.h"
  90 #include "qapi/qmp/qerror.h"
  91 #include "config-devices.h"
  92 #include "e820_memory_layout.h"
  93 #include "fw_cfg.h"
  94 #include "trace.h"
  95
  96 GlobalProperty pc_compat_4_2[] = {};
  97 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
  98
  99 GlobalProperty pc_compat_4_1[] = {};
 100 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
 101
 102 GlobalProperty pc_compat_4_0[] = {};
 103 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
 104
 105 GlobalProperty pc_compat_3_1[] = {
 106     { "intel-iommu", "dma-drain", "off" },
 107     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
 108     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
 109     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
 110     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
 111     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
 112     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
 113     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
 114     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
 115     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
 116     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
 117     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
 118     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
 119     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
 120     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
 121     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
 122     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
 123     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
 124     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
 125     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
 126     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
 127 };
 128 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
 129
 130 GlobalProperty pc_compat_3_0[] = {
 131     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
 132     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
 133     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
 134 };
 135 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
 136
 137 GlobalProperty pc_compat_2_12[] = {
 138     { TYPE_X86_CPU, "legacy-cache", "on" },
 139     { TYPE_X86_CPU, "topoext", "off" },
 140     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
 141     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
 142 };
 143 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
 144
 145 GlobalProperty pc_compat_2_11[] = {
 146     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
 147     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
 148 };
 149 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
 150
 151 GlobalProperty pc_compat_2_10[] = {
 152     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
 153     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
 154     { "q35-pcihost", "x-pci-hole64-fix", "off" },
 155 };
 156 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
 157
 158 GlobalProperty pc_compat_2_9[] = {
 159     { "mch", "extended-tseg-mbytes", "0" },
 160 };
 161 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
 162
 163 GlobalProperty pc_compat_2_8[] = {
 164     { TYPE_X86_CPU, "tcg-cpuid", "off" },
 165     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
 166     { "ICH9-LPC", "x-smi-broadcast", "off" },
 167     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
 168     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
 169 };
 170 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
 171
 172 GlobalProperty pc_compat_2_7[] = {
 173     { TYPE_X86_CPU, "l3-cache", "off" },
 174     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
 175     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
 176     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
 177     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
 178     { "isa-pcspk", "migrate", "off" },
 179 };
 180 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
 181
 182 GlobalProperty pc_compat_2_6[] = {
 183     { TYPE_X86_CPU, "cpuid-0xb", "off" },
 184     { "vmxnet3", "romfile", "" },
 185     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
 186     { "apic-common", "legacy-instance-id", "on", }
 187 };
 188 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
 189
 190 GlobalProperty pc_compat_2_5[] = {};
 191 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
 192
 193 GlobalProperty pc_compat_2_4[] = {
 194     PC_CPU_MODEL_IDS("2.4.0")
 195     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
 196     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
 197     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
 198     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
 199     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
 200     { TYPE_X86_CPU, "check", "off" },
 201     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
 202     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
 203     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
 204     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
 205     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
 206     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
 207     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
 208     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
 209 };
 210 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
 211
 212 GlobalProperty pc_compat_2_3[] = {
 213     PC_CPU_MODEL_IDS("2.3.0")
 214     { TYPE_X86_CPU, "arat", "off" },
 215     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
 216     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
 217     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
 218     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
 219     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
 220     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
 221     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
 222     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 223     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 224     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 225     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 226     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 227     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 228     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 229     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 230     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 231     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 232     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 233     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
 234 };
 235 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
 236
 237 GlobalProperty pc_compat_2_2[] = {
 238     PC_CPU_MODEL_IDS("2.2.0")
 239     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
 240     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
 241     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
 242     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
 243     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
 244     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
 245     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
 246     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
 247     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
 248     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
 249     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
 250     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
 251     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
 252     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
 253     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
 254     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
 255     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
 256     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
 257 };
 258 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
 259
 260 GlobalProperty pc_compat_2_1[] = {
 261     PC_CPU_MODEL_IDS("2.1.0")
 262     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
 263     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
 264 };
 265 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
 266
 267 GlobalProperty pc_compat_2_0[] = {
 268     PC_CPU_MODEL_IDS("2.0.0")
 269     { "virtio-scsi-pci", "any_layout", "off" },
 270     { "PIIX4_PM", "memory-hotplug-support", "off" },
 271     { "apic", "version", "0x11" },
 272     { "nec-usb-xhci", "superspeed-ports-first", "off" },
 273     { "nec-usb-xhci", "force-pcie-endcap", "on" },
 274     { "pci-serial", "prog_if", "0" },
 275     { "pci-serial-2x", "prog_if", "0" },
 276     { "pci-serial-4x", "prog_if", "0" },
 277     { "virtio-net-pci", "guest_announce", "off" },
 278     { "ICH9-LPC", "memory-hotplug-support", "off" },
 279     { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
 280     { "ioh3420", COMPAT_PROP_PCP, "off" },
 281 };
 282 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
 283
 284 GlobalProperty pc_compat_1_7[] = {
 285     PC_CPU_MODEL_IDS("1.7.0")
 286     { TYPE_USB_DEVICE, "msos-desc", "no" },
 287     { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
 288     { "hpet", HPET_INTCAP, "4" },
 289 };
 290 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
 291
 292 GlobalProperty pc_compat_1_6[] = {
 293     PC_CPU_MODEL_IDS("1.6.0")
 294     { "e1000", "mitigation", "off" },
 295     { "qemu64-" TYPE_X86_CPU, "model", "2" },
 296     { "qemu32-" TYPE_X86_CPU, "model", "3" },
 297     { "i440FX-pcihost", "short_root_bus", "1" },
 298     { "q35-pcihost", "short_root_bus", "1" },
 299 };
 300 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
 301
 302 GlobalProperty pc_compat_1_5[] = {
 303     PC_CPU_MODEL_IDS("1.5.0")
 304     { "Conroe-" TYPE_X86_CPU, "model", "2" },
 305     { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
 306     { "Penryn-" TYPE_X86_CPU, "model", "2" },
 307     { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
 308     { "Nehalem-" TYPE_X86_CPU, "model", "2" },
 309     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
 310     { "virtio-net-pci", "any_layout", "off" },
 311     { TYPE_X86_CPU, "pmu", "on" },
 312     { "i440FX-pcihost", "short_root_bus", "0" },
 313     { "q35-pcihost", "short_root_bus", "0" },
 314 };
 315 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
 316
 317 GlobalProperty pc_compat_1_4[] = {
 318     PC_CPU_MODEL_IDS("1.4.0")
 319     { "scsi-hd", "discard_granularity", "0" },
 320     { "scsi-cd", "discard_granularity", "0" },
 321     { "scsi-disk", "discard_granularity", "0" },
 322     { "ide-hd", "discard_granularity", "0" },
 323     { "ide-cd", "discard_granularity", "0" },
 324     { "ide-drive", "discard_granularity", "0" },
 325     { "virtio-blk-pci", "discard_granularity", "0" },
 326     /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
 327     { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
 328     { "virtio-net-pci", "ctrl_guest_offloads", "off" },
 329     { "e1000", "romfile", "pxe-e1000.rom" },
 330     { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
 331     { "pcnet", "romfile", "pxe-pcnet.rom" },
 332     { "rtl8139", "romfile", "pxe-rtl8139.rom" },
 333     { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
 334     { "486-" TYPE_X86_CPU, "model", "0" },
 335     { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
 336     { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
 337 };
 338 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
 339
 340 void gsi_handler(void *opaque, int n, int level)
 341 {
 342     GSIState *s = opaque;
 343
 344     trace_pc_gsi_interrupt(n, level);
 345     if (n < ISA_NUM_IRQS) {
 346         qemu_set_irq(s->i8259_irq[n], level);
 347     }
 348     qemu_set_irq(s->ioapic_irq[n], level);
 349 }
 350
 351 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
 352 {
 353     GSIState *s;
 354
 355     s = g_new0(GSIState, 1);
 356     if (kvm_ioapic_in_kernel()) {
 357         kvm_pc_setup_irq_routing(pci_enabled);
 358         *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
 359     } else {
 360         *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
 361     }
 362
 363     return s;
 364 }
 365
 366 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 367                            unsigned size)
 368 {
 369 }
 370
 371 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 372 {
 373     return 0xffffffffffffffffULL;
 374 }
 375
 376 /* MSDOS compatibility mode FPU exception support */
 377 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 378                            unsigned size)
 379 {
 380     if (tcg_enabled()) {
 381         cpu_set_ignne();
 382     }
 383 }
 384
 385 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 386 {
 387     return 0xffffffffffffffffULL;
 388 }
 389
 390 /* TSC handling */
 391 uint64_t cpu_get_tsc(CPUX86State *env)
 392 {
 393     return cpu_get_ticks();
 394 }
 395
 396 /* IRQ handling */
 397 int cpu_get_pic_interrupt(CPUX86State *env)
 398 {
 399     X86CPU *cpu = env_archcpu(env);
 400     int intno;
 401
 402     if (!kvm_irqchip_in_kernel()) {
 403         intno = apic_get_interrupt(cpu->apic_state);
 404         if (intno >= 0) {
 405             return intno;
 406         }
 407         /* read the irq from the PIC */
 408         if (!apic_accept_pic_intr(cpu->apic_state)) {
 409             return -1;
 410         }
 411     }
 412
 413     intno = pic_read_irq(isa_pic);
 414     return intno;
 415 }
 416
 417 static void pic_irq_request(void *opaque, int irq, int level)
 418 {
 419     CPUState *cs = first_cpu;
 420     X86CPU *cpu = X86_CPU(cs);
 421
 422     trace_pc_pic_interrupt(irq, level);
 423     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 424         CPU_FOREACH(cs) {
 425             cpu = X86_CPU(cs);
 426             if (apic_accept_pic_intr(cpu->apic_state)) {
 427                 apic_deliver_pic_intr(cpu->apic_state, level);
 428             }
 429         }
 430     } else {
 431         if (level) {
 432             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 433         } else {
 434             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 435         }
 436     }
 437 }
 438
 439 /* PC cmos mappings */
 440
 441 #define REG_EQUIPMENT_BYTE          0x14
 442
 443 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 444 {
 445     int val;
 446
 447     switch (fd0) {
 448     case FLOPPY_DRIVE_TYPE_144:
 449         /* 1.44 Mb 3"5 drive */
 450         val = 4;
 451         break;
 452     case FLOPPY_DRIVE_TYPE_288:
 453         /* 2.88 Mb 3"5 drive */
 454         val = 5;
 455         break;
 456     case FLOPPY_DRIVE_TYPE_120:
 457         /* 1.2 Mb 5"5 drive */
 458         val = 2;
 459         break;
 460     case FLOPPY_DRIVE_TYPE_NONE:
 461     default:
 462         val = 0;
 463         break;
 464     }
 465     return val;
 466 }
 467
 468 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 469                          int16_t cylinders, int8_t heads, int8_t sectors)
 470 {
 471     rtc_set_memory(s, type_ofs, 47);
 472     rtc_set_memory(s, info_ofs, cylinders);
 473     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 474     rtc_set_memory(s, info_ofs + 2, heads);
 475     rtc_set_memory(s, info_ofs + 3, 0xff);
 476     rtc_set_memory(s, info_ofs + 4, 0xff);
 477     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 478     rtc_set_memory(s, info_ofs + 6, cylinders);
 479     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 480     rtc_set_memory(s, info_ofs + 8, sectors);
 481 }
 482
 483 /* convert boot_device letter to something recognizable by the bios */
 484 static int boot_device2nibble(char boot_device)
 485 {
 486     switch(boot_device) {
 487     case 'a':
 488     case 'b':
 489         return 0x01; /* floppy boot */
 490     case 'c':
 491         return 0x02; /* hard drive boot */
 492     case 'd':
 493         return 0x03; /* CD-ROM boot */
 494     case 'n':
 495         return 0x04; /* Network boot */
 496     }
 497     return 0;
 498 }
 499
 500 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 501 {
 502 #define PC_MAX_BOOT_DEVICES 3
 503     int nbds, bds[3] = { 0, };
 504     int i;
 505
 506     nbds = strlen(boot_device);
 507     if (nbds > PC_MAX_BOOT_DEVICES) {
 508         error_setg(errp, "Too many boot devices for PC");
 509         return;
 510     }
 511     for (i = 0; i < nbds; i++) {
 512         bds[i] = boot_device2nibble(boot_device[i]);
 513         if (bds[i] == 0) {
 514             error_setg(errp, "Invalid boot device for PC: '%c'",
 515                        boot_device[i]);
 516             return;
 517         }
 518     }
 519     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 520     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 521 }
 522
 523 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 524 {
 525     set_boot_dev(opaque, boot_device, errp);
 526 }
 527
 528 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 529 {
 530     int val, nb, i;
 531     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 532                                    FLOPPY_DRIVE_TYPE_NONE };
 533
 534     /* floppy type */
 535     if (floppy) {
 536         for (i = 0; i < 2; i++) {
 537             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 538         }
 539     }
 540     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 541         cmos_get_fd_drive_type(fd_type[1]);
 542     rtc_set_memory(rtc_state, 0x10, val);
 543
 544     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 545     nb = 0;
 546     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 547         nb++;
 548     }
 549     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 550         nb++;
 551     }
 552     switch (nb) {
 553     case 0:
 554         break;
 555     case 1:
 556         val |= 0x01; /* 1 drive, ready for boot */
 557         break;
 558     case 2:
 559         val |= 0x41; /* 2 drives, ready for boot */
 560         break;
 561     }
 562     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 563 }
 564
 565 typedef struct pc_cmos_init_late_arg {
 566     ISADevice *rtc_state;
 567     BusState *idebus[2];
 568 } pc_cmos_init_late_arg;
 569
 570 typedef struct check_fdc_state {
 571     ISADevice *floppy;
 572     bool multiple;
 573 } CheckFdcState;
 574
 575 static int check_fdc(Object *obj, void *opaque)
 576 {
 577     CheckFdcState *state = opaque;
 578     Object *fdc;
 579     uint32_t iobase;
 580     Error *local_err = NULL;
 581
 582     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 583     if (!fdc) {
 584         return 0;
 585     }
 586
 587     iobase = object_property_get_uint(obj, "iobase", &local_err);
 588     if (local_err || iobase != 0x3f0) {
 589         error_free(local_err);
 590         return 0;
 591     }
 592
 593     if (state->floppy) {
 594         state->multiple = true;
 595     } else {
 596         state->floppy = ISA_DEVICE(obj);
 597     }
 598     return 0;
 599 }
 600
 601 static const char * const fdc_container_path[] = {
 602     "/unattached", "/peripheral", "/peripheral-anon"
 603 };
 604
 605 /*
 606  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 607  * and ACPI objects.
 608  */
 609 ISADevice *pc_find_fdc0(void)
 610 {
 611     int i;
 612     Object *container;
 613     CheckFdcState state = { 0 };
 614
 615     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 616         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 617         object_child_foreach(container, check_fdc, &state);
 618     }
 619
 620     if (state.multiple) {
 621         warn_report("multiple floppy disk controllers with "
 622                     "iobase=0x3f0 have been found");
 623         error_printf("the one being picked for CMOS setup might not reflect "
 624                      "your intent");
 625     }
 626
 627     return state.floppy;
 628 }
 629
 630 static void pc_cmos_init_late(void *opaque)
 631 {
 632     pc_cmos_init_late_arg *arg = opaque;
 633     ISADevice *s = arg->rtc_state;
 634     int16_t cylinders;
 635     int8_t heads, sectors;
 636     int val;
 637     int i, trans;
 638
 639     val = 0;
 640     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 641                                            &cylinders, &heads, &sectors) >= 0) {
 642         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 643         val |= 0xf0;
 644     }
 645     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 646                                            &cylinders, &heads, &sectors) >= 0) {
 647         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 648         val |= 0x0f;
 649     }
 650     rtc_set_memory(s, 0x12, val);
 651
 652     val = 0;
 653     for (i = 0; i < 4; i++) {
 654         /* NOTE: ide_get_geometry() returns the physical
 655            geometry.  It is always such that: 1 <= sects <= 63, 1
 656            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 657            geometry can be different if a translation is done. */
 658         if (arg->idebus[i / 2] &&
 659             ide_get_geometry(arg->idebus[i / 2], i % 2,
 660                              &cylinders, &heads, &sectors) >= 0) {
 661             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 662             assert((trans & ~3) == 0);
 663             val |= trans << (i * 2);
 664         }
 665     }
 666     rtc_set_memory(s, 0x39, val);
 667
 668     pc_cmos_init_floppy(s, pc_find_fdc0());
 669
 670     qemu_unregister_reset(pc_cmos_init_late, opaque);
 671 }
 672
 673 void pc_cmos_init(PCMachineState *pcms,
 674                   BusState *idebus0, BusState *idebus1,
 675                   ISADevice *s)
 676 {
 677     int val;
 678     static pc_cmos_init_late_arg arg;
 679     X86MachineState *x86ms = X86_MACHINE(pcms);
 680
 681     /* various important CMOS locations needed by PC/Bochs bios */
 682
 683     /* memory size */
 684     /* base memory (first MiB) */
 685     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
 686     rtc_set_memory(s, 0x15, val);
 687     rtc_set_memory(s, 0x16, val >> 8);
 688     /* extended memory (next 64MiB) */
 689     if (x86ms->below_4g_mem_size > 1 * MiB) {
 690         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
 691     } else {
 692         val = 0;
 693     }
 694     if (val > 65535)
 695         val = 65535;
 696     rtc_set_memory(s, 0x17, val);
 697     rtc_set_memory(s, 0x18, val >> 8);
 698     rtc_set_memory(s, 0x30, val);
 699     rtc_set_memory(s, 0x31, val >> 8);
 700     /* memory between 16MiB and 4GiB */
 701     if (x86ms->below_4g_mem_size > 16 * MiB) {
 702         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 703     } else {
 704         val = 0;
 705     }
 706     if (val > 65535)
 707         val = 65535;
 708     rtc_set_memory(s, 0x34, val);
 709     rtc_set_memory(s, 0x35, val >> 8);
 710     /* memory above 4GiB */
 711     val = x86ms->above_4g_mem_size / 65536;
 712     rtc_set_memory(s, 0x5b, val);
 713     rtc_set_memory(s, 0x5c, val >> 8);
 714     rtc_set_memory(s, 0x5d, val >> 16);
 715
 716     object_property_add_link(OBJECT(pcms), "rtc_state",
 717                              TYPE_ISA_DEVICE,
 718                              (Object **)&x86ms->rtc,
 719                              object_property_allow_set_link,
 720                              OBJ_PROP_LINK_STRONG, &error_abort);
 721     object_property_set_link(OBJECT(pcms), OBJECT(s),
 722                              "rtc_state", &error_abort);
 723
 724     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 725
 726     val = 0;
 727     val |= 0x02; /* FPU is there */
 728     val |= 0x04; /* PS/2 mouse installed */
 729     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 730
 731     /* hard drives and FDC */
 732     arg.rtc_state = s;
 733     arg.idebus[0] = idebus0;
 734     arg.idebus[1] = idebus1;
 735     qemu_register_reset(pc_cmos_init_late, &arg);
 736 }
 737
 738 #define TYPE_PORT92 "port92"
 739 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 740
 741 /* port 92 stuff: could be split off */
 742 typedef struct Port92State {
 743     ISADevice parent_obj;
 744
 745     MemoryRegion io;
 746     uint8_t outport;
 747     qemu_irq a20_out;
 748 } Port92State;
 749
 750 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 751                          unsigned size)
 752 {
 753     Port92State *s = opaque;
 754     int oldval = s->outport;
 755
 756     trace_port92_write(val);
 757     s->outport = val;
 758     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 759     if ((val & 1) && !(oldval & 1)) {
 760         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 761     }
 762 }
 763
 764 static uint64_t port92_read(void *opaque, hwaddr addr,
 765                             unsigned size)
 766 {
 767     Port92State *s = opaque;
 768     uint32_t ret;
 769
 770     ret = s->outport;
 771     trace_port92_read(ret);
 772     return ret;
 773 }
 774
 775 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 776 {
 777     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 778 }
 779
 780 static const VMStateDescription vmstate_port92_isa = {
 781     .name = "port92",
 782     .version_id = 1,
 783     .minimum_version_id = 1,
 784     .fields = (VMStateField[]) {
 785         VMSTATE_UINT8(outport, Port92State),
 786         VMSTATE_END_OF_LIST()
 787     }
 788 };
 789
 790 static void port92_reset(DeviceState *d)
 791 {
 792     Port92State *s = PORT92(d);
 793
 794     s->outport &= ~1;
 795 }
 796
 797 static const MemoryRegionOps port92_ops = {
 798     .read = port92_read,
 799     .write = port92_write,
 800     .impl = {
 801         .min_access_size = 1,
 802         .max_access_size = 1,
 803     },
 804     .endianness = DEVICE_LITTLE_ENDIAN,
 805 };
 806
 807 static void port92_initfn(Object *obj)
 808 {
 809     Port92State *s = PORT92(obj);
 810
 811     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 812
 813     s->outport = 0;
 814
 815     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 816 }
 817
 818 static void port92_realizefn(DeviceState *dev, Error **errp)
 819 {
 820     ISADevice *isadev = ISA_DEVICE(dev);
 821     Port92State *s = PORT92(dev);
 822
 823     isa_register_ioport(isadev, &s->io, 0x92);
 824 }
 825
 826 static void port92_class_initfn(ObjectClass *klass, void *data)
 827 {
 828     DeviceClass *dc = DEVICE_CLASS(klass);
 829
 830     dc->realize = port92_realizefn;
 831     dc->reset = port92_reset;
 832     dc->vmsd = &vmstate_port92_isa;
 833     /*
 834      * Reason: unlike ordinary ISA devices, this one needs additional
 835      * wiring: its A20 output line needs to be wired up by
 836      * port92_init().
 837      */
 838     dc->user_creatable = false;
 839 }
 840
 841 static const TypeInfo port92_info = {
 842     .name          = TYPE_PORT92,
 843     .parent        = TYPE_ISA_DEVICE,
 844     .instance_size = sizeof(Port92State),
 845     .instance_init = port92_initfn,
 846     .class_init    = port92_class_initfn,
 847 };
 848
 849 static void port92_register_types(void)
 850 {
 851     type_register_static(&port92_info);
 852 }
 853
 854 type_init(port92_register_types)
 855
 856 static void handle_a20_line_change(void *opaque, int irq, int level)
 857 {
 858     X86CPU *cpu = opaque;
 859
 860     /* XXX: send to all CPUs ? */
 861     /* XXX: add logic to handle multiple A20 line sources */
 862     x86_cpu_set_a20(cpu, level);
 863 }
 864
 865 #define NE2000_NB_MAX 6
 866
 867 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 868                                               0x280, 0x380 };
 869 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 870
 871 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 872 {
 873     static int nb_ne2k = 0;
 874
 875     if (nb_ne2k == NE2000_NB_MAX)
 876         return;
 877     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 878                     ne2000_irq[nb_ne2k], nd);
 879     nb_ne2k++;
 880 }
 881
 882 DeviceState *cpu_get_current_apic(void)
 883 {
 884     if (current_cpu) {
 885         X86CPU *cpu = X86_CPU(current_cpu);
 886         return cpu->apic_state;
 887     } else {
 888         return NULL;
 889     }
 890 }
 891
 892 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 893 {
 894     X86CPU *cpu = opaque;
 895
 896     if (level) {
 897         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 898     }
 899 }
 900
 901 /*
 902  * This function is very similar to smp_parse()
 903  * in hw/core/machine.c but includes CPU die support.
 904  */
 905 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
 906 {
 907     X86MachineState *x86ms = X86_MACHINE(ms);
 908
 909     if (opts) {
 910         unsigned cpus    = qemu_opt_get_number(opts, "cpus", 0);
 911         unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
 912         unsigned dies = qemu_opt_get_number(opts, "dies", 1);
 913         unsigned cores   = qemu_opt_get_number(opts, "cores", 0);
 914         unsigned threads = qemu_opt_get_number(opts, "threads", 0);
 915
 916         /* compute missing values, prefer sockets over cores over threads */
 917         if (cpus == 0 || sockets == 0) {
 918             cores = cores > 0 ? cores : 1;
 919             threads = threads > 0 ? threads : 1;
 920             if (cpus == 0) {
 921                 sockets = sockets > 0 ? sockets : 1;
 922                 cpus = cores * threads * dies * sockets;
 923             } else {
 924                 ms->smp.max_cpus =
 925                         qemu_opt_get_number(opts, "maxcpus", cpus);
 926                 sockets = ms->smp.max_cpus / (cores * threads * dies);
 927             }
 928         } else if (cores == 0) {
 929             threads = threads > 0 ? threads : 1;
 930             cores = cpus / (sockets * dies * threads);
 931             cores = cores > 0 ? cores : 1;
 932         } else if (threads == 0) {
 933             threads = cpus / (cores * dies * sockets);
 934             threads = threads > 0 ? threads : 1;
 935         } else if (sockets * dies * cores * threads < cpus) {
 936             error_report("cpu topology: "
 937                          "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
 938                          "smp_cpus (%u)",
 939                          sockets, dies, cores, threads, cpus);
 940             exit(1);
 941         }
 942
 943         ms->smp.max_cpus =
 944                 qemu_opt_get_number(opts, "maxcpus", cpus);
 945
 946         if (ms->smp.max_cpus < cpus) {
 947             error_report("maxcpus must be equal to or greater than smp");
 948             exit(1);
 949         }
 950
 951         if (sockets * dies * cores * threads > ms->smp.max_cpus) {
 952             error_report("cpu topology: "
 953                          "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
 954                          "maxcpus (%u)",
 955                          sockets, dies, cores, threads,
 956                          ms->smp.max_cpus);
 957             exit(1);
 958         }
 959
 960         if (sockets * dies * cores * threads != ms->smp.max_cpus) {
 961             warn_report("Invalid CPU topology deprecated: "
 962                         "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
 963                         "!= maxcpus (%u)",
 964                         sockets, dies, cores, threads,
 965                         ms->smp.max_cpus);
 966         }
 967
 968         ms->smp.cpus = cpus;
 969         ms->smp.cores = cores;
 970         ms->smp.threads = threads;
 971         x86ms->smp_dies = dies;
 972     }
 973
 974     if (ms->smp.cpus > 1) {
 975         Error *blocker = NULL;
 976         error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
 977         replay_add_blocker(blocker);
 978     }
 979 }
 980
 981 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
 982 {
 983     X86MachineState *x86ms = X86_MACHINE(ms);
 984     int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
 985     Error *local_err = NULL;
 986
 987     if (id < 0) {
 988         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
 989         return;
 990     }
 991
 992     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
 993         error_setg(errp, "Unable to add CPU: %" PRIi64
 994                    ", resulting APIC ID (%" PRIi64 ") is too large",
 995                    id, apic_id);
 996         return;
 997     }
 998
 999
1000     x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
1001     if (local_err) {
1002         error_propagate(errp, local_err);
1003         return;
1004     }
1005 }
1006
1007 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1008 {
1009     if (cpus_count > 0xff) {
1010         /* If the number of CPUs can't be represented in 8 bits, the
1011          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1012          * to make old BIOSes fail more predictably.
1013          */
1014         rtc_set_memory(rtc, 0x5f, 0);
1015     } else {
1016         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1017     }
1018 }
1019
1020 static
1021 void pc_machine_done(Notifier *notifier, void *data)
1022 {
1023     PCMachineState *pcms = container_of(notifier,
1024                                         PCMachineState, machine_done);
1025     X86MachineState *x86ms = X86_MACHINE(pcms);
1026     PCIBus *bus = pcms->bus;
1027
1028     /* set the number of CPUs */
1029     rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1030
1031     if (bus) {
1032         int extra_hosts = 0;
1033
1034         QLIST_FOREACH(bus, &bus->child, sibling) {
1035             /* look for expander root buses */
1036             if (pci_bus_is_root(bus)) {
1037                 extra_hosts++;
1038             }
1039         }
1040         if (extra_hosts && x86ms->fw_cfg) {
1041             uint64_t *val = g_malloc(sizeof(*val));
1042             *val = cpu_to_le64(extra_hosts);
1043             fw_cfg_add_file(x86ms->fw_cfg,
1044                     "etc/extra-pci-roots", val, sizeof(*val));
1045         }
1046     }
1047
1048     acpi_setup();
1049     if (x86ms->fw_cfg) {
1050         fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
1051         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
1052         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1053         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1054     }
1055
1056     if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
1057         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1058
1059         if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1060             iommu->intr_eim != ON_OFF_AUTO_ON) {
1061             error_report("current -smp configuration requires "
1062                          "Extended Interrupt Mode enabled. "
1063                          "You can add an IOMMU using: "
1064                          "-device intel-iommu,intremap=on,eim=on");
1065             exit(EXIT_FAILURE);
1066         }
1067     }
1068 }
1069
1070 void pc_guest_info_init(PCMachineState *pcms)
1071 {
1072     int i;
1073     MachineState *ms = MACHINE(pcms);
1074     X86MachineState *x86ms = X86_MACHINE(pcms);
1075
1076     x86ms->apic_xrupt_override = kvm_allows_irq0_override();
1077     pcms->numa_nodes = ms->numa_state->num_nodes;
1078     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1079                                     sizeof *pcms->node_mem);
1080     for (i = 0; i < ms->numa_state->num_nodes; i++) {
1081         pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
1082     }
1083
1084     pcms->machine_done.notify = pc_machine_done;
1085     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1086 }
1087
1088 /* setup pci memory address space mapping into system address space */
1089 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1090                             MemoryRegion *pci_address_space)
1091 {
1092     /* Set to lower priority than RAM */
1093     memory_region_add_subregion_overlap(system_memory, 0x0,
1094                                         pci_address_space, -1);
1095 }
1096
1097 void xen_load_linux(PCMachineState *pcms)
1098 {
1099     int i;
1100     FWCfgState *fw_cfg;
1101     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1102     X86MachineState *x86ms = X86_MACHINE(pcms);
1103
1104     assert(MACHINE(pcms)->kernel_filename != NULL);
1105
1106     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1107     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1108     rom_set_fw(fw_cfg);
1109
1110     x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1111                    pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1112     for (i = 0; i < nb_option_roms; i++) {
1113         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1114                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1115                !strcmp(option_rom[i].name, "pvh.bin") ||
1116                !strcmp(option_rom[i].name, "multiboot.bin"));
1117         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1118     }
1119     x86ms->fw_cfg = fw_cfg;
1120 }
1121
1122 void pc_memory_init(PCMachineState *pcms,
1123                     MemoryRegion *system_memory,
1124                     MemoryRegion *rom_memory,
1125                     MemoryRegion **ram_memory)
1126 {
1127     int linux_boot, i;
1128     MemoryRegion *ram, *option_rom_mr;
1129     MemoryRegion *ram_below_4g, *ram_above_4g;
1130     FWCfgState *fw_cfg;
1131     MachineState *machine = MACHINE(pcms);
1132     MachineClass *mc = MACHINE_GET_CLASS(machine);
1133     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1134     X86MachineState *x86ms = X86_MACHINE(pcms);
1135
1136     assert(machine->ram_size == x86ms->below_4g_mem_size +
1137                                 x86ms->above_4g_mem_size);
1138
1139     linux_boot = (machine->kernel_filename != NULL);
1140
1141     /* Allocate RAM.  We allocate it as a single memory region and use
1142      * aliases to address portions of it, mostly for backwards compatibility
1143      * with older qemus that used qemu_ram_alloc().
1144      */
1145     ram = g_malloc(sizeof(*ram));
1146     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1147                                          machine->ram_size);
1148     *ram_memory = ram;
1149     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1150     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1151                              0, x86ms->below_4g_mem_size);
1152     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1153     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1154     if (x86ms->above_4g_mem_size > 0) {
1155         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1156         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1157                                  x86ms->below_4g_mem_size,
1158                                  x86ms->above_4g_mem_size);
1159         memory_region_add_subregion(system_memory, 0x100000000ULL,
1160                                     ram_above_4g);
1161         e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
1162     }
1163
1164     if (!pcmc->has_reserved_memory &&
1165         (machine->ram_slots ||
1166          (machine->maxram_size > machine->ram_size))) {
1167
1168         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1169                      mc->name);
1170         exit(EXIT_FAILURE);
1171     }
1172
1173     /* always allocate the device memory information */
1174     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1175
1176     /* initialize device memory address space */
1177     if (pcmc->has_reserved_memory &&
1178         (machine->ram_size < machine->maxram_size)) {
1179         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1180
1181         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1182             error_report("unsupported amount of memory slots: %"PRIu64,
1183                          machine->ram_slots);
1184             exit(EXIT_FAILURE);
1185         }
1186
1187         if (QEMU_ALIGN_UP(machine->maxram_size,
1188                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1189             error_report("maximum memory size must by aligned to multiple of "
1190                          "%d bytes", TARGET_PAGE_SIZE);
1191             exit(EXIT_FAILURE);
1192         }
1193
1194         machine->device_memory->base =
1195             ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1196
1197         if (pcmc->enforce_aligned_dimm) {
1198             /* size device region assuming 1G page max alignment per slot */
1199             device_mem_size += (1 * GiB) * machine->ram_slots;
1200         }
1201
1202         if ((machine->device_memory->base + device_mem_size) <
1203             device_mem_size) {
1204             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1205                          machine->maxram_size);
1206             exit(EXIT_FAILURE);
1207         }
1208
1209         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1210                            "device-memory", device_mem_size);
1211         memory_region_add_subregion(system_memory, machine->device_memory->base,
1212                                     &machine->device_memory->mr);
1213     }
1214
1215     /* Initialize PC system firmware */
1216     pc_system_firmware_init(pcms, rom_memory);
1217
1218     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1219     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1220                            &error_fatal);
1221     if (pcmc->pci_enabled) {
1222         memory_region_set_readonly(option_rom_mr, true);
1223     }
1224     memory_region_add_subregion_overlap(rom_memory,
1225                                         PC_ROM_MIN_VGA,
1226                                         option_rom_mr,
1227                                         1);
1228
1229     fw_cfg = fw_cfg_arch_create(machine,
1230                                 x86ms->boot_cpus, x86ms->apic_id_limit);
1231
1232     rom_set_fw(fw_cfg);
1233
1234     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1235         uint64_t *val = g_malloc(sizeof(*val));
1236         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1237         uint64_t res_mem_end = machine->device_memory->base;
1238
1239         if (!pcmc->broken_reserved_end) {
1240             res_mem_end += memory_region_size(&machine->device_memory->mr);
1241         }
1242         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1243         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1244     }
1245
1246     if (linux_boot) {
1247         x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1248                        pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1249     }
1250
1251     for (i = 0; i < nb_option_roms; i++) {
1252         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1253     }
1254     x86ms->fw_cfg = fw_cfg;
1255
1256     /* Init default IOAPIC address space */
1257     x86ms->ioapic_as = &address_space_memory;
1258
1259     /* Init ACPI memory hotplug IO base address */
1260     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1261 }
1262
1263 /*
1264  * The 64bit pci hole starts after "above 4G RAM" and
1265  * potentially the space reserved for memory hotplug.
1266  */
1267 uint64_t pc_pci_hole64_start(void)
1268 {
1269     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1270     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1271     MachineState *ms = MACHINE(pcms);
1272     X86MachineState *x86ms = X86_MACHINE(pcms);
1273     uint64_t hole64_start = 0;
1274
1275     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1276         hole64_start = ms->device_memory->base;
1277         if (!pcmc->broken_reserved_end) {
1278             hole64_start += memory_region_size(&ms->device_memory->mr);
1279         }
1280     } else {
1281         hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1282     }
1283
1284     return ROUND_UP(hole64_start, 1 * GiB);
1285 }
1286
1287 qemu_irq pc_allocate_cpu_irq(void)
1288 {
1289     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1290 }
1291
1292 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1293 {
1294     DeviceState *dev = NULL;
1295
1296     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1297     if (pci_bus) {
1298         PCIDevice *pcidev = pci_vga_init(pci_bus);
1299         dev = pcidev ? &pcidev->qdev : NULL;
1300     } else if (isa_bus) {
1301         ISADevice *isadev = isa_vga_init(isa_bus);
1302         dev = isadev ? DEVICE(isadev) : NULL;
1303     }
1304     rom_reset_order_override();
1305     return dev;
1306 }
1307
1308 static const MemoryRegionOps ioport80_io_ops = {
1309     .write = ioport80_write,
1310     .read = ioport80_read,
1311     .endianness = DEVICE_NATIVE_ENDIAN,
1312     .impl = {
1313         .min_access_size = 1,
1314         .max_access_size = 1,
1315     },
1316 };
1317
1318 static const MemoryRegionOps ioportF0_io_ops = {
1319     .write = ioportF0_write,
1320     .read = ioportF0_read,
1321     .endianness = DEVICE_NATIVE_ENDIAN,
1322     .impl = {
1323         .min_access_size = 1,
1324         .max_access_size = 1,
1325     },
1326 };
1327
1328 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1329 {
1330     int i;
1331     DriveInfo *fd[MAX_FD];
1332     qemu_irq *a20_line;
1333     ISADevice *i8042, *port92, *vmmouse;
1334
1335     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1336     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1337
1338     for (i = 0; i < MAX_FD; i++) {
1339         fd[i] = drive_get(IF_FLOPPY, 0, i);
1340         create_fdctrl |= !!fd[i];
1341     }
1342     if (create_fdctrl) {
1343         fdctrl_init_isa(isa_bus, fd);
1344     }
1345
1346     i8042 = isa_create_simple(isa_bus, "i8042");
1347     if (!no_vmport) {
1348         vmport_init(isa_bus);
1349         vmmouse = isa_try_create(isa_bus, "vmmouse");
1350     } else {
1351         vmmouse = NULL;
1352     }
1353     if (vmmouse) {
1354         DeviceState *dev = DEVICE(vmmouse);
1355         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1356         qdev_init_nofail(dev);
1357     }
1358     port92 = isa_create_simple(isa_bus, "port92");
1359
1360     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1361     i8042_setup_a20_line(i8042, a20_line[0]);
1362     port92_init(port92, a20_line[1]);
1363     g_free(a20_line);
1364 }
1365
1366 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1367                           ISADevice **rtc_state,
1368                           bool create_fdctrl,
1369                           bool no_vmport,
1370                           bool has_pit,
1371                           uint32_t hpet_irqs)
1372 {
1373     int i;
1374     DeviceState *hpet = NULL;
1375     int pit_isa_irq = 0;
1376     qemu_irq pit_alt_irq = NULL;
1377     qemu_irq rtc_irq = NULL;
1378     ISADevice *pit = NULL;
1379     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1380     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1381
1382     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1383     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1384
1385     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1386     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1387
1388     /*
1389      * Check if an HPET shall be created.
1390      *
1391      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1392      * when the HPET wants to take over. Thus we have to disable the latter.
1393      */
1394     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1395         /* In order to set property, here not using sysbus_try_create_simple */
1396         hpet = qdev_try_create(NULL, TYPE_HPET);
1397         if (hpet) {
1398             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1399              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1400              * IRQ8 and IRQ2.
1401              */
1402             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1403                     HPET_INTCAP, NULL);
1404             if (!compat) {
1405                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1406             }
1407             qdev_init_nofail(hpet);
1408             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1409
1410             for (i = 0; i < GSI_NUM_PINS; i++) {
1411                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1412             }
1413             pit_isa_irq = -1;
1414             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1415             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1416         }
1417     }
1418     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1419
1420     qemu_register_boot_set(pc_boot_set, *rtc_state);
1421
1422     if (!xen_enabled() && has_pit) {
1423         if (kvm_pit_in_kernel()) {
1424             pit = kvm_pit_init(isa_bus, 0x40);
1425         } else {
1426             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1427         }
1428         if (hpet) {
1429             /* connect PIT to output control line of the HPET */
1430             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1431         }
1432         pcspk_init(isa_bus, pit);
1433     }
1434
1435     i8257_dma_init(isa_bus, 0);
1436
1437     /* Super I/O */
1438     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1439 }
1440
1441 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1442 {
1443     int i;
1444
1445     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1446     for (i = 0; i < nb_nics; i++) {
1447         NICInfo *nd = &nd_table[i];
1448         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1449
1450         if (g_str_equal(model, "ne2k_isa")) {
1451             pc_init_ne2k_isa(isa_bus, nd);
1452         } else {
1453             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1454         }
1455     }
1456     rom_reset_order_override();
1457 }
1458
1459 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1460 {
1461     qemu_irq *i8259;
1462
1463     if (kvm_pic_in_kernel()) {
1464         i8259 = kvm_i8259_init(isa_bus);
1465     } else if (xen_enabled()) {
1466         i8259 = xen_interrupt_controller_init();
1467     } else {
1468         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
1469     }
1470
1471     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1472         i8259_irqs[i] = i8259[i];
1473     }
1474
1475     g_free(i8259);
1476 }
1477
1478 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1479 {
1480     DeviceState *dev;
1481     SysBusDevice *d;
1482     unsigned int i;
1483
1484     if (kvm_ioapic_in_kernel()) {
1485         dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
1486     } else {
1487         dev = qdev_create(NULL, TYPE_IOAPIC);
1488     }
1489     if (parent_name) {
1490         object_property_add_child(object_resolve_path(parent_name, NULL),
1491                                   "ioapic", OBJECT(dev), NULL);
1492     }
1493     qdev_init_nofail(dev);
1494     d = SYS_BUS_DEVICE(dev);
1495     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1496
1497     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1498         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1499     }
1500 }
1501
1502 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1503                                Error **errp)
1504 {
1505     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1506     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1507     const MachineState *ms = MACHINE(hotplug_dev);
1508     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1509     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1510     Error *local_err = NULL;
1511
1512     /*
1513      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1514      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1515      * addition to cover this case.
1516      */
1517     if (!pcms->acpi_dev || !acpi_enabled) {
1518         error_setg(errp,
1519                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1520         return;
1521     }
1522
1523     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1524         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1525         return;
1526     }
1527
1528     hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1529     if (local_err) {
1530         error_propagate(errp, local_err);
1531         return;
1532     }
1533
1534     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1535                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1536 }
1537
1538 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1539                            DeviceState *dev, Error **errp)
1540 {
1541     Error *local_err = NULL;
1542     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1543     MachineState *ms = MACHINE(hotplug_dev);
1544     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1545
1546     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1547     if (local_err) {
1548         goto out;
1549     }
1550
1551     if (is_nvdimm) {
1552         nvdimm_plug(ms->nvdimms_state);
1553     }
1554
1555     hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1556 out:
1557     error_propagate(errp, local_err);
1558 }
1559
1560 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1561                                      DeviceState *dev, Error **errp)
1562 {
1563     Error *local_err = NULL;
1564     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1565
1566     /*
1567      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1568      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1569      * addition to cover this case.
1570      */
1571     if (!pcms->acpi_dev || !acpi_enabled) {
1572         error_setg(&local_err,
1573                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1574         goto out;
1575     }
1576
1577     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1578         error_setg(&local_err,
1579                    "nvdimm device hot unplug is not supported yet.");
1580         goto out;
1581     }
1582
1583     hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1584                                    &local_err);
1585 out:
1586     error_propagate(errp, local_err);
1587 }
1588
1589 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1590                              DeviceState *dev, Error **errp)
1591 {
1592     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1593     Error *local_err = NULL;
1594
1595     hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1596     if (local_err) {
1597         goto out;
1598     }
1599
1600     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1601     object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1602  out:
1603     error_propagate(errp, local_err);
1604 }
1605
1606 static int pc_apic_cmp(const void *a, const void *b)
1607 {
1608    CPUArchId *apic_a = (CPUArchId *)a;
1609    CPUArchId *apic_b = (CPUArchId *)b;
1610
1611    return apic_a->arch_id - apic_b->arch_id;
1612 }
1613
1614 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1615  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1616  * entry corresponding to CPU's apic_id returns NULL.
1617  */
1618 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1619 {
1620     CPUArchId apic_id, *found_cpu;
1621
1622     apic_id.arch_id = id;
1623     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1624         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1625         pc_apic_cmp);
1626     if (found_cpu && idx) {
1627         *idx = found_cpu - ms->possible_cpus->cpus;
1628     }
1629     return found_cpu;
1630 }
1631
1632 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1633                         DeviceState *dev, Error **errp)
1634 {
1635     CPUArchId *found_cpu;
1636     Error *local_err = NULL;
1637     X86CPU *cpu = X86_CPU(dev);
1638     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1639     X86MachineState *x86ms = X86_MACHINE(pcms);
1640
1641     if (pcms->acpi_dev) {
1642         hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1643         if (local_err) {
1644             goto out;
1645         }
1646     }
1647
1648     /* increment the number of CPUs */
1649     x86ms->boot_cpus++;
1650     if (x86ms->rtc) {
1651         rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1652     }
1653     if (x86ms->fw_cfg) {
1654         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1655     }
1656
1657     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1658     found_cpu->cpu = OBJECT(dev);
1659 out:
1660     error_propagate(errp, local_err);
1661 }
1662 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1663                                      DeviceState *dev, Error **errp)
1664 {
1665     int idx = -1;
1666     Error *local_err = NULL;
1667     X86CPU *cpu = X86_CPU(dev);
1668     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1669
1670     if (!pcms->acpi_dev) {
1671         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1672         goto out;
1673     }
1674
1675     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1676     assert(idx != -1);
1677     if (idx == 0) {
1678         error_setg(&local_err, "Boot CPU is unpluggable");
1679         goto out;
1680     }
1681
1682     hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1683                                    &local_err);
1684     if (local_err) {
1685         goto out;
1686     }
1687
1688  out:
1689     error_propagate(errp, local_err);
1690
1691 }
1692
1693 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1694                              DeviceState *dev, Error **errp)
1695 {
1696     CPUArchId *found_cpu;
1697     Error *local_err = NULL;
1698     X86CPU *cpu = X86_CPU(dev);
1699     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1700     X86MachineState *x86ms = X86_MACHINE(pcms);
1701
1702     hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1703     if (local_err) {
1704         goto out;
1705     }
1706
1707     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1708     found_cpu->cpu = NULL;
1709     object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1710
1711     /* decrement the number of CPUs */
1712     x86ms->boot_cpus--;
1713     /* Update the number of CPUs in CMOS */
1714     rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1715     fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1716  out:
1717     error_propagate(errp, local_err);
1718 }
1719
1720 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1721                             DeviceState *dev, Error **errp)
1722 {
1723     int idx;
1724     CPUState *cs;
1725     CPUArchId *cpu_slot;
1726     X86CPUTopoInfo topo;
1727     X86CPU *cpu = X86_CPU(dev);
1728     CPUX86State *env = &cpu->env;
1729     MachineState *ms = MACHINE(hotplug_dev);
1730     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1731     X86MachineState *x86ms = X86_MACHINE(pcms);
1732     unsigned int smp_cores = ms->smp.cores;
1733     unsigned int smp_threads = ms->smp.threads;
1734
1735     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1736         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1737                    ms->cpu_type);
1738         return;
1739     }
1740
1741     env->nr_dies = x86ms->smp_dies;
1742
1743     /*
1744      * If APIC ID is not set,
1745      * set it based on socket/die/core/thread properties.
1746      */
1747     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1748         int max_socket = (ms->smp.max_cpus - 1) /
1749                                 smp_threads / smp_cores / x86ms->smp_dies;
1750
1751         /*
1752          * die-id was optional in QEMU 4.0 and older, so keep it optional
1753          * if there's only one die per socket.
1754          */
1755         if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1756             cpu->die_id = 0;
1757         }
1758
1759         if (cpu->socket_id < 0) {
1760             error_setg(errp, "CPU socket-id is not set");
1761             return;
1762         } else if (cpu->socket_id > max_socket) {
1763             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1764                        cpu->socket_id, max_socket);
1765             return;
1766         }
1767         if (cpu->die_id < 0) {
1768             error_setg(errp, "CPU die-id is not set");
1769             return;
1770         } else if (cpu->die_id > x86ms->smp_dies - 1) {
1771             error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1772                        cpu->die_id, x86ms->smp_dies - 1);
1773             return;
1774         }
1775         if (cpu->core_id < 0) {
1776             error_setg(errp, "CPU core-id is not set");
1777             return;
1778         } else if (cpu->core_id > (smp_cores - 1)) {
1779             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1780                        cpu->core_id, smp_cores - 1);
1781             return;
1782         }
1783         if (cpu->thread_id < 0) {
1784             error_setg(errp, "CPU thread-id is not set");
1785             return;
1786         } else if (cpu->thread_id > (smp_threads - 1)) {
1787             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1788                        cpu->thread_id, smp_threads - 1);
1789             return;
1790         }
1791
1792         topo.pkg_id = cpu->socket_id;
1793         topo.die_id = cpu->die_id;
1794         topo.core_id = cpu->core_id;
1795         topo.smt_id = cpu->thread_id;
1796         cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1797                                             smp_threads, &topo);
1798     }
1799
1800     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1801     if (!cpu_slot) {
1802         MachineState *ms = MACHINE(pcms);
1803
1804         x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1805                                  smp_cores, smp_threads, &topo);
1806         error_setg(errp,
1807             "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1808             " APIC ID %" PRIu32 ", valid index range 0:%d",
1809             topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1810             cpu->apic_id, ms->possible_cpus->len - 1);
1811         return;
1812     }
1813
1814     if (cpu_slot->cpu) {
1815         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1816                    idx, cpu->apic_id);
1817         return;
1818     }
1819
1820     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1821      * so that machine_query_hotpluggable_cpus would show correct values
1822      */
1823     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1824      * once -smp refactoring is complete and there will be CPU private
1825      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1826     x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1827                              smp_cores, smp_threads, &topo);
1828     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1829         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1830             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1831         return;
1832     }
1833     cpu->socket_id = topo.pkg_id;
1834
1835     if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1836         error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1837             " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1838         return;
1839     }
1840     cpu->die_id = topo.die_id;
1841
1842     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1843         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1844             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1845         return;
1846     }
1847     cpu->core_id = topo.core_id;
1848
1849     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1850         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1851             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1852         return;
1853     }
1854     cpu->thread_id = topo.smt_id;
1855
1856     if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1857         !kvm_hv_vpindex_settable()) {
1858         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1859         return;
1860     }
1861
1862     cs = CPU(cpu);
1863     cs->cpu_index = idx;
1864
1865     numa_cpu_pre_plug(cpu_slot, dev, errp);
1866 }
1867
1868 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1869                                         DeviceState *dev, Error **errp)
1870 {
1871     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1872     Error *local_err = NULL;
1873
1874     if (!hotplug_dev2) {
1875         /*
1876          * Without a bus hotplug handler, we cannot control the plug/unplug
1877          * order. This should never be the case on x86, however better add
1878          * a safety net.
1879          */
1880         error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1881         return;
1882     }
1883     /*
1884      * First, see if we can plug this memory device at all. If that
1885      * succeeds, branch of to the actual hotplug handler.
1886      */
1887     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1888                            &local_err);
1889     if (!local_err) {
1890         hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1891     }
1892     error_propagate(errp, local_err);
1893 }
1894
1895 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1896                                     DeviceState *dev, Error **errp)
1897 {
1898     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1899     Error *local_err = NULL;
1900
1901     /*
1902      * Plug the memory device first and then branch off to the actual
1903      * hotplug handler. If that one fails, we can easily undo the memory
1904      * device bits.
1905      */
1906     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1907     hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1908     if (local_err) {
1909         memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1910     }
1911     error_propagate(errp, local_err);
1912 }
1913
1914 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1915                                               DeviceState *dev, Error **errp)
1916 {
1917     /* We don't support virtio pmem hot unplug */
1918     error_setg(errp, "virtio pmem device unplug not supported.");
1919 }
1920
1921 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1922                                       DeviceState *dev, Error **errp)
1923 {
1924     /* We don't support virtio pmem hot unplug */
1925 }
1926
1927 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1928                                           DeviceState *dev, Error **errp)
1929 {
1930     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1931         pc_memory_pre_plug(hotplug_dev, dev, errp);
1932     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1933         pc_cpu_pre_plug(hotplug_dev, dev, errp);
1934     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1935         pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1936     }
1937 }
1938
1939 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1940                                       DeviceState *dev, Error **errp)
1941 {
1942     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1943         pc_memory_plug(hotplug_dev, dev, errp);
1944     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1945         pc_cpu_plug(hotplug_dev, dev, errp);
1946     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1947         pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1948     }
1949 }
1950
1951 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1952                                                 DeviceState *dev, Error **errp)
1953 {
1954     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1955         pc_memory_unplug_request(hotplug_dev, dev, errp);
1956     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1957         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1958     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1959         pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1960     } else {
1961         error_setg(errp, "acpi: device unplug request for not supported device"
1962                    " type: %s", object_get_typename(OBJECT(dev)));
1963     }
1964 }
1965
1966 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1967                                         DeviceState *dev, Error **errp)
1968 {
1969     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1970         pc_memory_unplug(hotplug_dev, dev, errp);
1971     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1972         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1973     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1974         pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1975     } else {
1976         error_setg(errp, "acpi: device unplug for not supported device"
1977                    " type: %s", object_get_typename(OBJECT(dev)));
1978     }
1979 }
1980
1981 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1982                                              DeviceState *dev)
1983 {
1984     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1985         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1986         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1987         return HOTPLUG_HANDLER(machine);
1988     }
1989
1990     return NULL;
1991 }
1992
1993 static void
1994 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1995                                          const char *name, void *opaque,
1996                                          Error **errp)
1997 {
1998     MachineState *ms = MACHINE(obj);
1999     int64_t value = 0;
2000
2001     if (ms->device_memory) {
2002         value = memory_region_size(&ms->device_memory->mr);
2003     }
2004
2005     visit_type_int(v, name, &value, errp);
2006 }
2007
2008 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2009                                   void *opaque, Error **errp)
2010 {
2011     PCMachineState *pcms = PC_MACHINE(obj);
2012     OnOffAuto vmport = pcms->vmport;
2013
2014     visit_type_OnOffAuto(v, name, &vmport, errp);
2015 }
2016
2017 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2018                                   void *opaque, Error **errp)
2019 {
2020     PCMachineState *pcms = PC_MACHINE(obj);
2021
2022     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2023 }
2024
2025 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2026 {
2027     PCMachineState *pcms = PC_MACHINE(obj);
2028
2029     return pcms->smbus_enabled;
2030 }
2031
2032 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2033 {
2034     PCMachineState *pcms = PC_MACHINE(obj);
2035
2036     pcms->smbus_enabled = value;
2037 }
2038
2039 static bool pc_machine_get_sata(Object *obj, Error **errp)
2040 {
2041     PCMachineState *pcms = PC_MACHINE(obj);
2042
2043     return pcms->sata_enabled;
2044 }
2045
2046 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2047 {
2048     PCMachineState *pcms = PC_MACHINE(obj);
2049
2050     pcms->sata_enabled = value;
2051 }
2052
2053 static bool pc_machine_get_pit(Object *obj, Error **errp)
2054 {
2055     PCMachineState *pcms = PC_MACHINE(obj);
2056
2057     return pcms->pit_enabled;
2058 }
2059
2060 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2061 {
2062     PCMachineState *pcms = PC_MACHINE(obj);
2063
2064     pcms->pit_enabled = value;
2065 }
2066
2067 static void pc_machine_initfn(Object *obj)
2068 {
2069     PCMachineState *pcms = PC_MACHINE(obj);
2070
2071 #ifdef CONFIG_VMPORT
2072     pcms->vmport = ON_OFF_AUTO_AUTO;
2073 #else
2074     pcms->vmport = ON_OFF_AUTO_OFF;
2075 #endif /* CONFIG_VMPORT */
2076     /* acpi build is enabled by default if machine supports it */
2077     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2078     pcms->smbus_enabled = true;
2079     pcms->sata_enabled = true;
2080     pcms->pit_enabled = true;
2081
2082     pc_system_flash_create(pcms);
2083 }
2084
2085 static void pc_machine_reset(MachineState *machine)
2086 {
2087     CPUState *cs;
2088     X86CPU *cpu;
2089
2090     qemu_devices_reset();
2091
2092     /* Reset APIC after devices have been reset to cancel
2093      * any changes that qemu_devices_reset() might have done.
2094      */
2095     CPU_FOREACH(cs) {
2096         cpu = X86_CPU(cs);
2097
2098         if (cpu->apic_state) {
2099             device_reset(cpu->apic_state);
2100         }
2101     }
2102 }
2103
2104 static void pc_machine_wakeup(MachineState *machine)
2105 {
2106     cpu_synchronize_all_states();
2107     pc_machine_reset(machine);
2108     cpu_synchronize_all_post_reset();
2109 }
2110
2111 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
2112 {
2113     X86IOMMUState *iommu = x86_iommu_get_default();
2114     IntelIOMMUState *intel_iommu;
2115
2116     if (iommu &&
2117         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
2118         object_dynamic_cast((Object *)dev, "vfio-pci")) {
2119         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2120         if (!intel_iommu->caching_mode) {
2121             error_setg(errp, "Device assignment is not allowed without "
2122                        "enabling caching-mode=on for Intel IOMMU.");
2123             return false;
2124         }
2125     }
2126
2127     return true;
2128 }
2129
2130 static void pc_machine_class_init(ObjectClass *oc, void *data)
2131 {
2132     MachineClass *mc = MACHINE_CLASS(oc);
2133     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2134     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2135
2136     pcmc->pci_enabled = true;
2137     pcmc->has_acpi_build = true;
2138     pcmc->rsdp_in_ram = true;
2139     pcmc->smbios_defaults = true;
2140     pcmc->smbios_uuid_encoded = true;
2141     pcmc->gigabyte_align = true;
2142     pcmc->has_reserved_memory = true;
2143     pcmc->kvmclock_enabled = true;
2144     pcmc->enforce_aligned_dimm = true;
2145     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2146      * to be used at the moment, 32K should be enough for a while.  */
2147     pcmc->acpi_data_size = 0x20000 + 0x8000;
2148     pcmc->linuxboot_dma_enabled = true;
2149     pcmc->pvh_enabled = true;
2150     assert(!mc->get_hotplug_handler);
2151     mc->get_hotplug_handler = pc_get_hotplug_handler;
2152     mc->hotplug_allowed = pc_hotplug_allowed;
2153     mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
2154     mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
2155     mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
2156     mc->auto_enable_numa_with_memhp = true;
2157     mc->has_hotpluggable_cpus = true;
2158     mc->default_boot_order = "cad";
2159     mc->hot_add_cpu = pc_hot_add_cpu;
2160     mc->smp_parse = pc_smp_parse;
2161     mc->block_default_type = IF_IDE;
2162     mc->max_cpus = 255;
2163     mc->reset = pc_machine_reset;
2164     mc->wakeup = pc_machine_wakeup;
2165     hc->pre_plug = pc_machine_device_pre_plug_cb;
2166     hc->plug = pc_machine_device_plug_cb;
2167     hc->unplug_request = pc_machine_device_unplug_request_cb;
2168     hc->unplug = pc_machine_device_unplug_cb;
2169     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2170     mc->nvdimm_supported = true;
2171     mc->numa_mem_supported = true;
2172
2173     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2174         pc_machine_get_device_memory_region_size, NULL,
2175         NULL, NULL, &error_abort);
2176
2177     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2178         pc_machine_get_vmport, pc_machine_set_vmport,
2179         NULL, NULL, &error_abort);
2180     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2181         "Enable vmport (pc & q35)", &error_abort);
2182
2183     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2184         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2185
2186     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2187         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2188
2189     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2190         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2191 }
2192
2193 static const TypeInfo pc_machine_info = {
2194     .name = TYPE_PC_MACHINE,
2195     .parent = TYPE_X86_MACHINE,
2196     .abstract = true,
2197     .instance_size = sizeof(PCMachineState),
2198     .instance_init = pc_machine_initfn,
2199     .class_size = sizeof(PCMachineClass),
2200     .class_init = pc_machine_class_init,
2201     .interfaces = (InterfaceInfo[]) {
2202          { TYPE_HOTPLUG_HANDLER },
2203          { }
2204     },
2205 };
2206
2207 static void pc_machine_register_types(void)
2208 {
2209     type_register_static(&pc_machine_info);
2210 }
2211
2212 type_init(pc_machine_register_types)