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hw/i386/pc: Wire RTC ISA IRQs in south bridges
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/fw_cfg.h"
31 #include "hw/i386/vmport.h"
32 #include "sysemu/cpus.h"
33 #include "hw/ide/internal.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/loader.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/intc/i8259.h"
38 #include "hw/timer/i8254.h"
39 #include "hw/input/i8042.h"
40 #include "hw/audio/pcspk.h"
41 #include "sysemu/sysemu.h"
42 #include "sysemu/xen.h"
43 #include "sysemu/reset.h"
44 #include "kvm/kvm_i386.h"
45 #include "hw/xen/xen.h"
46 #include "qemu/error-report.h"
47 #include "hw/acpi/cpu_hotplug.h"
48 #include "acpi-build.h"
49 #include "hw/mem/nvdimm.h"
50 #include "hw/cxl/cxl_host.h"
51 #include "hw/usb.h"
52 #include "hw/i386/intel_iommu.h"
53 #include "hw/net/ne2000-isa.h"
54 #include "hw/virtio/virtio-iommu.h"
55 #include "hw/virtio/virtio-md-pci.h"
56 #include "hw/i386/kvm/xen_overlay.h"
57 #include "hw/i386/kvm/xen_evtchn.h"
58 #include "hw/i386/kvm/xen_gnttab.h"
59 #include "hw/i386/kvm/xen_xenstore.h"
60 #include "e820_memory_layout.h"
61 #include "trace.h"
62 #include CONFIG_DEVICES
63
64 #ifdef CONFIG_XEN_EMU
65 #include "hw/xen/xen-legacy-backend.h"
66 #include "hw/xen/xen-bus.h"
67 #endif
68
69 /*
70 * Helper for setting model-id for CPU models that changed model-id
71 * depending on QEMU versions up to QEMU 2.4.
72 */
73 #define PC_CPU_MODEL_IDS(v) \
74 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
75 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
76 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
77
78 GlobalProperty pc_compat_8_1[] = {};
79 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
80
81 GlobalProperty pc_compat_8_0[] = {
82 { "virtio-mem", "unplugged-inaccessible", "auto" },
83 };
84 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
85
86 GlobalProperty pc_compat_7_2[] = {
87 { "ICH9-LPC", "noreboot", "true" },
88 };
89 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
90
91 GlobalProperty pc_compat_7_1[] = {};
92 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
93
94 GlobalProperty pc_compat_7_0[] = {};
95 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
96
97 GlobalProperty pc_compat_6_2[] = {
98 { "virtio-mem", "unplugged-inaccessible", "off" },
99 };
100 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
101
102 GlobalProperty pc_compat_6_1[] = {
103 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
104 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
105 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
106 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
107 };
108 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
109
110 GlobalProperty pc_compat_6_0[] = {
111 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
112 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
113 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
114 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
115 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
116 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
117 };
118 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
119
120 GlobalProperty pc_compat_5_2[] = {
121 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
122 };
123 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
124
125 GlobalProperty pc_compat_5_1[] = {
126 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
127 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
128 };
129 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
130
131 GlobalProperty pc_compat_5_0[] = {
132 };
133 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
134
135 GlobalProperty pc_compat_4_2[] = {
136 { "mch", "smbase-smram", "off" },
137 };
138 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
139
140 GlobalProperty pc_compat_4_1[] = {};
141 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
142
143 GlobalProperty pc_compat_4_0[] = {};
144 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
145
146 GlobalProperty pc_compat_3_1[] = {
147 { "intel-iommu", "dma-drain", "off" },
148 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
149 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
150 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
151 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
152 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
153 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
154 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
155 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
156 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
157 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
158 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
159 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
160 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
161 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
162 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
163 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
164 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
165 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
167 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
168 };
169 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
170
171 GlobalProperty pc_compat_3_0[] = {
172 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
173 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
174 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
175 };
176 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
177
178 GlobalProperty pc_compat_2_12[] = {
179 { TYPE_X86_CPU, "legacy-cache", "on" },
180 { TYPE_X86_CPU, "topoext", "off" },
181 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
182 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
183 };
184 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
185
186 GlobalProperty pc_compat_2_11[] = {
187 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
188 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
189 };
190 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
191
192 GlobalProperty pc_compat_2_10[] = {
193 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
194 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
195 { "q35-pcihost", "x-pci-hole64-fix", "off" },
196 };
197 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
198
199 GlobalProperty pc_compat_2_9[] = {
200 { "mch", "extended-tseg-mbytes", "0" },
201 };
202 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
203
204 GlobalProperty pc_compat_2_8[] = {
205 { TYPE_X86_CPU, "tcg-cpuid", "off" },
206 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
207 { "ICH9-LPC", "x-smi-broadcast", "off" },
208 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
209 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
210 };
211 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
212
213 GlobalProperty pc_compat_2_7[] = {
214 { TYPE_X86_CPU, "l3-cache", "off" },
215 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
216 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
217 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
218 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
219 { "isa-pcspk", "migrate", "off" },
220 };
221 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
222
223 GlobalProperty pc_compat_2_6[] = {
224 { TYPE_X86_CPU, "cpuid-0xb", "off" },
225 { "vmxnet3", "romfile", "" },
226 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
227 { "apic-common", "legacy-instance-id", "on", }
228 };
229 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
230
231 GlobalProperty pc_compat_2_5[] = {};
232 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
233
234 GlobalProperty pc_compat_2_4[] = {
235 PC_CPU_MODEL_IDS("2.4.0")
236 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
237 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
238 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
239 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
240 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
241 { TYPE_X86_CPU, "check", "off" },
242 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
243 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
244 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
245 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
246 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
247 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
248 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
249 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
250 };
251 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
252
253 GlobalProperty pc_compat_2_3[] = {
254 PC_CPU_MODEL_IDS("2.3.0")
255 { TYPE_X86_CPU, "arat", "off" },
256 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
257 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
258 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
259 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
260 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
261 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
262 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
263 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
264 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
265 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
266 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
267 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
268 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
275 };
276 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
277
278 GlobalProperty pc_compat_2_2[] = {
279 PC_CPU_MODEL_IDS("2.2.0")
280 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
281 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
282 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
283 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
284 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
285 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
286 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
287 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
288 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
295 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
296 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
297 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
298 };
299 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
300
301 GlobalProperty pc_compat_2_1[] = {
302 PC_CPU_MODEL_IDS("2.1.0")
303 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
304 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
305 };
306 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
307
308 GlobalProperty pc_compat_2_0[] = {
309 PC_CPU_MODEL_IDS("2.0.0")
310 { "virtio-scsi-pci", "any_layout", "off" },
311 { "PIIX4_PM", "memory-hotplug-support", "off" },
312 { "apic", "version", "0x11" },
313 { "nec-usb-xhci", "superspeed-ports-first", "off" },
314 { "nec-usb-xhci", "force-pcie-endcap", "on" },
315 { "pci-serial", "prog_if", "0" },
316 { "pci-serial-2x", "prog_if", "0" },
317 { "pci-serial-4x", "prog_if", "0" },
318 { "virtio-net-pci", "guest_announce", "off" },
319 { "ICH9-LPC", "memory-hotplug-support", "off" },
320 };
321 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
322
323 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
324 {
325 GSIState *s;
326
327 s = g_new0(GSIState, 1);
328 if (kvm_ioapic_in_kernel()) {
329 kvm_pc_setup_irq_routing(pci_enabled);
330 }
331 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
332
333 return s;
334 }
335
336 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
337 unsigned size)
338 {
339 }
340
341 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
342 {
343 return 0xffffffffffffffffULL;
344 }
345
346 /* MS-DOS compatibility mode FPU exception support */
347 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
348 unsigned size)
349 {
350 if (tcg_enabled()) {
351 cpu_set_ignne();
352 }
353 }
354
355 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
356 {
357 return 0xffffffffffffffffULL;
358 }
359
360 /* PC cmos mappings */
361
362 #define REG_EQUIPMENT_BYTE 0x14
363
364 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
365 int16_t cylinders, int8_t heads, int8_t sectors)
366 {
367 mc146818rtc_set_cmos_data(s, type_ofs, 47);
368 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
369 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
370 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
371 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
372 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
373 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
374 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
375 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
376 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
377 }
378
379 /* convert boot_device letter to something recognizable by the bios */
380 static int boot_device2nibble(char boot_device)
381 {
382 switch(boot_device) {
383 case 'a':
384 case 'b':
385 return 0x01; /* floppy boot */
386 case 'c':
387 return 0x02; /* hard drive boot */
388 case 'd':
389 return 0x03; /* CD-ROM boot */
390 case 'n':
391 return 0x04; /* Network boot */
392 }
393 return 0;
394 }
395
396 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
397 Error **errp)
398 {
399 #define PC_MAX_BOOT_DEVICES 3
400 int nbds, bds[3] = { 0, };
401 int i;
402
403 nbds = strlen(boot_device);
404 if (nbds > PC_MAX_BOOT_DEVICES) {
405 error_setg(errp, "Too many boot devices for PC");
406 return;
407 }
408 for (i = 0; i < nbds; i++) {
409 bds[i] = boot_device2nibble(boot_device[i]);
410 if (bds[i] == 0) {
411 error_setg(errp, "Invalid boot device for PC: '%c'",
412 boot_device[i]);
413 return;
414 }
415 }
416 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
417 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
418 }
419
420 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
421 {
422 set_boot_dev(opaque, boot_device, errp);
423 }
424
425 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
426 {
427 int val, nb, i;
428 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
429 FLOPPY_DRIVE_TYPE_NONE };
430
431 /* floppy type */
432 if (floppy) {
433 for (i = 0; i < 2; i++) {
434 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
435 }
436 }
437 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
438 cmos_get_fd_drive_type(fd_type[1]);
439 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
440
441 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
442 nb = 0;
443 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
444 nb++;
445 }
446 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
447 nb++;
448 }
449 switch (nb) {
450 case 0:
451 break;
452 case 1:
453 val |= 0x01; /* 1 drive, ready for boot */
454 break;
455 case 2:
456 val |= 0x41; /* 2 drives, ready for boot */
457 break;
458 }
459 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
460 }
461
462 typedef struct pc_cmos_init_late_arg {
463 MC146818RtcState *rtc_state;
464 BusState *idebus[2];
465 } pc_cmos_init_late_arg;
466
467 typedef struct check_fdc_state {
468 ISADevice *floppy;
469 bool multiple;
470 } CheckFdcState;
471
472 static int check_fdc(Object *obj, void *opaque)
473 {
474 CheckFdcState *state = opaque;
475 Object *fdc;
476 uint32_t iobase;
477 Error *local_err = NULL;
478
479 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
480 if (!fdc) {
481 return 0;
482 }
483
484 iobase = object_property_get_uint(obj, "iobase", &local_err);
485 if (local_err || iobase != 0x3f0) {
486 error_free(local_err);
487 return 0;
488 }
489
490 if (state->floppy) {
491 state->multiple = true;
492 } else {
493 state->floppy = ISA_DEVICE(obj);
494 }
495 return 0;
496 }
497
498 static const char * const fdc_container_path[] = {
499 "/unattached", "/peripheral", "/peripheral-anon"
500 };
501
502 /*
503 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
504 * and ACPI objects.
505 */
506 static ISADevice *pc_find_fdc0(void)
507 {
508 int i;
509 Object *container;
510 CheckFdcState state = { 0 };
511
512 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
513 container = container_get(qdev_get_machine(), fdc_container_path[i]);
514 object_child_foreach(container, check_fdc, &state);
515 }
516
517 if (state.multiple) {
518 warn_report("multiple floppy disk controllers with "
519 "iobase=0x3f0 have been found");
520 error_printf("the one being picked for CMOS setup might not reflect "
521 "your intent");
522 }
523
524 return state.floppy;
525 }
526
527 static void pc_cmos_init_late(void *opaque)
528 {
529 pc_cmos_init_late_arg *arg = opaque;
530 MC146818RtcState *s = arg->rtc_state;
531 int16_t cylinders;
532 int8_t heads, sectors;
533 int val;
534 int i, trans;
535
536 val = 0;
537 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
538 &cylinders, &heads, &sectors) >= 0) {
539 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
540 val |= 0xf0;
541 }
542 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
543 &cylinders, &heads, &sectors) >= 0) {
544 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
545 val |= 0x0f;
546 }
547 mc146818rtc_set_cmos_data(s, 0x12, val);
548
549 val = 0;
550 for (i = 0; i < 4; i++) {
551 /* NOTE: ide_get_geometry() returns the physical
552 geometry. It is always such that: 1 <= sects <= 63, 1
553 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
554 geometry can be different if a translation is done. */
555 if (arg->idebus[i / 2] &&
556 ide_get_geometry(arg->idebus[i / 2], i % 2,
557 &cylinders, &heads, &sectors) >= 0) {
558 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
559 assert((trans & ~3) == 0);
560 val |= trans << (i * 2);
561 }
562 }
563 mc146818rtc_set_cmos_data(s, 0x39, val);
564
565 pc_cmos_init_floppy(s, pc_find_fdc0());
566
567 qemu_unregister_reset(pc_cmos_init_late, opaque);
568 }
569
570 void pc_cmos_init(PCMachineState *pcms,
571 BusState *idebus0, BusState *idebus1,
572 ISADevice *rtc)
573 {
574 int val;
575 static pc_cmos_init_late_arg arg;
576 X86MachineState *x86ms = X86_MACHINE(pcms);
577 MC146818RtcState *s = MC146818_RTC(rtc);
578
579 /* various important CMOS locations needed by PC/Bochs bios */
580
581 /* memory size */
582 /* base memory (first MiB) */
583 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
584 mc146818rtc_set_cmos_data(s, 0x15, val);
585 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
586 /* extended memory (next 64MiB) */
587 if (x86ms->below_4g_mem_size > 1 * MiB) {
588 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
589 } else {
590 val = 0;
591 }
592 if (val > 65535)
593 val = 65535;
594 mc146818rtc_set_cmos_data(s, 0x17, val);
595 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
596 mc146818rtc_set_cmos_data(s, 0x30, val);
597 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
598 /* memory between 16MiB and 4GiB */
599 if (x86ms->below_4g_mem_size > 16 * MiB) {
600 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
601 } else {
602 val = 0;
603 }
604 if (val > 65535)
605 val = 65535;
606 mc146818rtc_set_cmos_data(s, 0x34, val);
607 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
608 /* memory above 4GiB */
609 val = x86ms->above_4g_mem_size / 65536;
610 mc146818rtc_set_cmos_data(s, 0x5b, val);
611 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
612 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
613
614 object_property_add_link(OBJECT(pcms), "rtc_state",
615 TYPE_ISA_DEVICE,
616 (Object **)&x86ms->rtc,
617 object_property_allow_set_link,
618 OBJ_PROP_LINK_STRONG);
619 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
620 &error_abort);
621
622 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
623
624 val = 0;
625 val |= 0x02; /* FPU is there */
626 val |= 0x04; /* PS/2 mouse installed */
627 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
628
629 /* hard drives and FDC */
630 arg.rtc_state = s;
631 arg.idebus[0] = idebus0;
632 arg.idebus[1] = idebus1;
633 qemu_register_reset(pc_cmos_init_late, &arg);
634 }
635
636 static void handle_a20_line_change(void *opaque, int irq, int level)
637 {
638 X86CPU *cpu = opaque;
639
640 /* XXX: send to all CPUs ? */
641 /* XXX: add logic to handle multiple A20 line sources */
642 x86_cpu_set_a20(cpu, level);
643 }
644
645 #define NE2000_NB_MAX 6
646
647 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
648 0x280, 0x380 };
649 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
650
651 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
652 {
653 static int nb_ne2k = 0;
654
655 if (nb_ne2k == NE2000_NB_MAX)
656 return;
657 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
658 ne2000_irq[nb_ne2k], nd);
659 nb_ne2k++;
660 }
661
662 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
663 {
664 X86CPU *cpu = opaque;
665
666 if (level) {
667 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
668 }
669 }
670
671 static
672 void pc_machine_done(Notifier *notifier, void *data)
673 {
674 PCMachineState *pcms = container_of(notifier,
675 PCMachineState, machine_done);
676 X86MachineState *x86ms = X86_MACHINE(pcms);
677
678 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
679 &error_fatal);
680
681 if (pcms->cxl_devices_state.is_enabled) {
682 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
683 }
684
685 /* set the number of CPUs */
686 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
687
688 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
689
690 acpi_setup();
691 if (x86ms->fw_cfg) {
692 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
693 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
694 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
695 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
696 }
697 }
698
699 void pc_guest_info_init(PCMachineState *pcms)
700 {
701 X86MachineState *x86ms = X86_MACHINE(pcms);
702
703 x86ms->apic_xrupt_override = true;
704 pcms->machine_done.notify = pc_machine_done;
705 qemu_add_machine_init_done_notifier(&pcms->machine_done);
706 }
707
708 /* setup pci memory address space mapping into system address space */
709 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
710 MemoryRegion *pci_address_space)
711 {
712 /* Set to lower priority than RAM */
713 memory_region_add_subregion_overlap(system_memory, 0x0,
714 pci_address_space, -1);
715 }
716
717 void xen_load_linux(PCMachineState *pcms)
718 {
719 int i;
720 FWCfgState *fw_cfg;
721 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
722 X86MachineState *x86ms = X86_MACHINE(pcms);
723
724 assert(MACHINE(pcms)->kernel_filename != NULL);
725
726 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
727 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
728 rom_set_fw(fw_cfg);
729
730 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
731 pcmc->pvh_enabled);
732 for (i = 0; i < nb_option_roms; i++) {
733 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
734 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
735 !strcmp(option_rom[i].name, "pvh.bin") ||
736 !strcmp(option_rom[i].name, "multiboot.bin") ||
737 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
738 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
739 }
740 x86ms->fw_cfg = fw_cfg;
741 }
742
743 #define PC_ROM_MIN_VGA 0xc0000
744 #define PC_ROM_MIN_OPTION 0xc8000
745 #define PC_ROM_MAX 0xe0000
746 #define PC_ROM_ALIGN 0x800
747 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
748
749 static hwaddr pc_above_4g_end(PCMachineState *pcms)
750 {
751 X86MachineState *x86ms = X86_MACHINE(pcms);
752
753 if (pcms->sgx_epc.size != 0) {
754 return sgx_epc_above_4g_end(&pcms->sgx_epc);
755 }
756
757 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
758 }
759
760 static void pc_get_device_memory_range(PCMachineState *pcms,
761 hwaddr *base,
762 ram_addr_t *device_mem_size)
763 {
764 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
765 MachineState *machine = MACHINE(pcms);
766 ram_addr_t size;
767 hwaddr addr;
768
769 size = machine->maxram_size - machine->ram_size;
770 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
771
772 if (pcmc->enforce_aligned_dimm) {
773 /* size device region assuming 1G page max alignment per slot */
774 size += (1 * GiB) * machine->ram_slots;
775 }
776
777 *base = addr;
778 *device_mem_size = size;
779 }
780
781 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
782 {
783 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
784 hwaddr cxl_base;
785 ram_addr_t size;
786
787 if (pcmc->has_reserved_memory) {
788 pc_get_device_memory_range(pcms, &cxl_base, &size);
789 cxl_base += size;
790 } else {
791 cxl_base = pc_above_4g_end(pcms);
792 }
793
794 return cxl_base;
795 }
796
797 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
798 {
799 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
800
801 if (pcms->cxl_devices_state.fixed_windows) {
802 GList *it;
803
804 start = ROUND_UP(start, 256 * MiB);
805 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
806 CXLFixedWindow *fw = it->data;
807 start += fw->size;
808 }
809 }
810
811 return start;
812 }
813
814 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
815 {
816 X86CPU *cpu = X86_CPU(first_cpu);
817 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
818 MachineState *ms = MACHINE(pcms);
819
820 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
821 /* 64-bit systems */
822 return pc_pci_hole64_start() + pci_hole64_size - 1;
823 }
824
825 /* 32-bit systems */
826 if (pcmc->broken_32bit_mem_addr_check) {
827 /* old value for compatibility reasons */
828 return ((hwaddr)1 << cpu->phys_bits) - 1;
829 }
830
831 /*
832 * 32-bit systems don't have hole64 but they might have a region for
833 * memory devices. Even if additional hotplugged memory devices might
834 * not be usable by most guest OSes, we need to still consider them for
835 * calculating the highest possible GPA so that we can properly report
836 * if someone configures them on a CPU that cannot possibly address them.
837 */
838 if (pcmc->has_reserved_memory &&
839 (ms->ram_size < ms->maxram_size)) {
840 hwaddr devmem_start;
841 ram_addr_t devmem_size;
842
843 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
844 devmem_start += devmem_size;
845 return devmem_start - 1;
846 }
847
848 /* configuration without any memory hotplug */
849 return pc_above_4g_end(pcms) - 1;
850 }
851
852 /*
853 * AMD systems with an IOMMU have an additional hole close to the
854 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
855 * on kernel version, VFIO may or may not let you DMA map those ranges.
856 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
857 * with certain memory sizes. It's also wrong to use those IOVA ranges
858 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
859 * The ranges reserved for Hyper-Transport are:
860 *
861 * FD_0000_0000h - FF_FFFF_FFFFh
862 *
863 * The ranges represent the following:
864 *
865 * Base Address Top Address Use
866 *
867 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
868 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
869 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
870 * FD_F910_0000h FD_F91F_FFFFh System Management
871 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
872 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
873 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
874 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
875 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
876 * FE_2000_0000h FF_FFFF_FFFFh Reserved
877 *
878 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
879 * Table 3: Special Address Controls (GPA) for more information.
880 */
881 #define AMD_HT_START 0xfd00000000UL
882 #define AMD_HT_END 0xffffffffffUL
883 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
884 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
885
886 void pc_memory_init(PCMachineState *pcms,
887 MemoryRegion *system_memory,
888 MemoryRegion *rom_memory,
889 uint64_t pci_hole64_size)
890 {
891 int linux_boot, i;
892 MemoryRegion *option_rom_mr;
893 MemoryRegion *ram_below_4g, *ram_above_4g;
894 FWCfgState *fw_cfg;
895 MachineState *machine = MACHINE(pcms);
896 MachineClass *mc = MACHINE_GET_CLASS(machine);
897 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
898 X86MachineState *x86ms = X86_MACHINE(pcms);
899 hwaddr maxphysaddr, maxusedaddr;
900 hwaddr cxl_base, cxl_resv_end = 0;
901 X86CPU *cpu = X86_CPU(first_cpu);
902
903 assert(machine->ram_size == x86ms->below_4g_mem_size +
904 x86ms->above_4g_mem_size);
905
906 linux_boot = (machine->kernel_filename != NULL);
907
908 /*
909 * The HyperTransport range close to the 1T boundary is unique to AMD
910 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
911 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
912 * older machine types (<= 7.0) for compatibility purposes.
913 */
914 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
915 /* Bail out if max possible address does not cross HT range */
916 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
917 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
918 }
919
920 /*
921 * Advertise the HT region if address space covers the reserved
922 * region or if we relocate.
923 */
924 if (cpu->phys_bits >= 40) {
925 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
926 }
927 }
928
929 /*
930 * phys-bits is required to be appropriately configured
931 * to make sure max used GPA is reachable.
932 */
933 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
934 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
935 if (maxphysaddr < maxusedaddr) {
936 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
937 " phys-bits too low (%u)",
938 maxphysaddr, maxusedaddr, cpu->phys_bits);
939 exit(EXIT_FAILURE);
940 }
941
942 /*
943 * Split single memory region and use aliases to address portions of it,
944 * done for backwards compatibility with older qemus.
945 */
946 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
947 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
948 0, x86ms->below_4g_mem_size);
949 memory_region_add_subregion(system_memory, 0, ram_below_4g);
950 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
951 if (x86ms->above_4g_mem_size > 0) {
952 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
953 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
954 machine->ram,
955 x86ms->below_4g_mem_size,
956 x86ms->above_4g_mem_size);
957 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
958 ram_above_4g);
959 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
960 E820_RAM);
961 }
962
963 if (pcms->sgx_epc.size != 0) {
964 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
965 }
966
967 if (!pcmc->has_reserved_memory &&
968 (machine->ram_slots ||
969 (machine->maxram_size > machine->ram_size))) {
970
971 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
972 mc->name);
973 exit(EXIT_FAILURE);
974 }
975
976 /* initialize device memory address space */
977 if (pcmc->has_reserved_memory &&
978 (machine->ram_size < machine->maxram_size)) {
979 ram_addr_t device_mem_size;
980 hwaddr device_mem_base;
981
982 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
983 error_report("unsupported amount of memory slots: %"PRIu64,
984 machine->ram_slots);
985 exit(EXIT_FAILURE);
986 }
987
988 if (QEMU_ALIGN_UP(machine->maxram_size,
989 TARGET_PAGE_SIZE) != machine->maxram_size) {
990 error_report("maximum memory size must by aligned to multiple of "
991 "%d bytes", TARGET_PAGE_SIZE);
992 exit(EXIT_FAILURE);
993 }
994
995 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
996
997 if (device_mem_base + device_mem_size < device_mem_size) {
998 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
999 machine->maxram_size);
1000 exit(EXIT_FAILURE);
1001 }
1002 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
1003 }
1004
1005 if (pcms->cxl_devices_state.is_enabled) {
1006 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1007 hwaddr cxl_size = MiB;
1008
1009 cxl_base = pc_get_cxl_range_start(pcms);
1010 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1011 memory_region_add_subregion(system_memory, cxl_base, mr);
1012 cxl_resv_end = cxl_base + cxl_size;
1013 if (pcms->cxl_devices_state.fixed_windows) {
1014 hwaddr cxl_fmw_base;
1015 GList *it;
1016
1017 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1018 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1019 CXLFixedWindow *fw = it->data;
1020
1021 fw->base = cxl_fmw_base;
1022 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1023 "cxl-fixed-memory-region", fw->size);
1024 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1025 cxl_fmw_base += fw->size;
1026 cxl_resv_end = cxl_fmw_base;
1027 }
1028 }
1029 }
1030
1031 /* Initialize PC system firmware */
1032 pc_system_firmware_init(pcms, rom_memory);
1033
1034 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1035 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1036 &error_fatal);
1037 if (pcmc->pci_enabled) {
1038 memory_region_set_readonly(option_rom_mr, true);
1039 }
1040 memory_region_add_subregion_overlap(rom_memory,
1041 PC_ROM_MIN_VGA,
1042 option_rom_mr,
1043 1);
1044
1045 fw_cfg = fw_cfg_arch_create(machine,
1046 x86ms->boot_cpus, x86ms->apic_id_limit);
1047
1048 rom_set_fw(fw_cfg);
1049
1050 if (machine->device_memory) {
1051 uint64_t *val = g_malloc(sizeof(*val));
1052 uint64_t res_mem_end = machine->device_memory->base;
1053
1054 if (!pcmc->broken_reserved_end) {
1055 res_mem_end += memory_region_size(&machine->device_memory->mr);
1056 }
1057
1058 if (pcms->cxl_devices_state.is_enabled) {
1059 res_mem_end = cxl_resv_end;
1060 }
1061 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1062 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1063 }
1064
1065 if (linux_boot) {
1066 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1067 pcmc->pvh_enabled);
1068 }
1069
1070 for (i = 0; i < nb_option_roms; i++) {
1071 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1072 }
1073 x86ms->fw_cfg = fw_cfg;
1074
1075 /* Init default IOAPIC address space */
1076 x86ms->ioapic_as = &address_space_memory;
1077
1078 /* Init ACPI memory hotplug IO base address */
1079 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1080 }
1081
1082 /*
1083 * The 64bit pci hole starts after "above 4G RAM" and
1084 * potentially the space reserved for memory hotplug.
1085 */
1086 uint64_t pc_pci_hole64_start(void)
1087 {
1088 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1089 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1090 MachineState *ms = MACHINE(pcms);
1091 uint64_t hole64_start = 0;
1092 ram_addr_t size = 0;
1093
1094 if (pcms->cxl_devices_state.is_enabled) {
1095 hole64_start = pc_get_cxl_range_end(pcms);
1096 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1097 pc_get_device_memory_range(pcms, &hole64_start, &size);
1098 if (!pcmc->broken_reserved_end) {
1099 hole64_start += size;
1100 }
1101 } else {
1102 hole64_start = pc_above_4g_end(pcms);
1103 }
1104
1105 return ROUND_UP(hole64_start, 1 * GiB);
1106 }
1107
1108 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1109 {
1110 DeviceState *dev = NULL;
1111
1112 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1113 if (pci_bus) {
1114 PCIDevice *pcidev = pci_vga_init(pci_bus);
1115 dev = pcidev ? &pcidev->qdev : NULL;
1116 } else if (isa_bus) {
1117 ISADevice *isadev = isa_vga_init(isa_bus);
1118 dev = isadev ? DEVICE(isadev) : NULL;
1119 }
1120 rom_reset_order_override();
1121 return dev;
1122 }
1123
1124 static const MemoryRegionOps ioport80_io_ops = {
1125 .write = ioport80_write,
1126 .read = ioport80_read,
1127 .endianness = DEVICE_NATIVE_ENDIAN,
1128 .impl = {
1129 .min_access_size = 1,
1130 .max_access_size = 1,
1131 },
1132 };
1133
1134 static const MemoryRegionOps ioportF0_io_ops = {
1135 .write = ioportF0_write,
1136 .read = ioportF0_read,
1137 .endianness = DEVICE_NATIVE_ENDIAN,
1138 .impl = {
1139 .min_access_size = 1,
1140 .max_access_size = 1,
1141 },
1142 };
1143
1144 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1145 bool create_i8042, bool no_vmport)
1146 {
1147 int i;
1148 DriveInfo *fd[MAX_FD];
1149 qemu_irq *a20_line;
1150 ISADevice *fdc, *i8042, *port92, *vmmouse;
1151
1152 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1153 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1154
1155 for (i = 0; i < MAX_FD; i++) {
1156 fd[i] = drive_get(IF_FLOPPY, 0, i);
1157 create_fdctrl |= !!fd[i];
1158 }
1159 if (create_fdctrl) {
1160 fdc = isa_new(TYPE_ISA_FDC);
1161 if (fdc) {
1162 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1163 isa_fdc_init_drives(fdc, fd);
1164 }
1165 }
1166
1167 if (!create_i8042) {
1168 return;
1169 }
1170
1171 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1172 if (!no_vmport) {
1173 isa_create_simple(isa_bus, TYPE_VMPORT);
1174 vmmouse = isa_try_new("vmmouse");
1175 } else {
1176 vmmouse = NULL;
1177 }
1178 if (vmmouse) {
1179 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1180 &error_abort);
1181 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1182 }
1183 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1184
1185 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1186 i8042_setup_a20_line(i8042, a20_line[0]);
1187 qdev_connect_gpio_out_named(DEVICE(port92),
1188 PORT92_A20_LINE, 0, a20_line[1]);
1189 g_free(a20_line);
1190 }
1191
1192 void pc_basic_device_init(struct PCMachineState *pcms,
1193 ISABus *isa_bus, qemu_irq *gsi,
1194 ISADevice *rtc_state,
1195 bool create_fdctrl,
1196 uint32_t hpet_irqs)
1197 {
1198 int i;
1199 DeviceState *hpet = NULL;
1200 int pit_isa_irq = 0;
1201 qemu_irq pit_alt_irq = NULL;
1202 ISADevice *pit = NULL;
1203 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1204 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1205 X86MachineState *x86ms = X86_MACHINE(pcms);
1206
1207 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1208 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1209
1210 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1211 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1212
1213 /*
1214 * Check if an HPET shall be created.
1215 *
1216 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1217 * when the HPET wants to take over. Thus we have to disable the latter.
1218 */
1219 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1220 kvm_has_pit_state2())) {
1221 qemu_irq rtc_irq;
1222
1223 hpet = qdev_try_new(TYPE_HPET);
1224 if (!hpet) {
1225 error_report("couldn't create HPET device");
1226 exit(1);
1227 }
1228 /*
1229 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1230 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1231 * the property, use whatever mask they specified.
1232 */
1233 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1234 HPET_INTCAP, NULL);
1235 if (!compat) {
1236 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1237 }
1238 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1239 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1240
1241 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1242 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1243 }
1244 pit_isa_irq = -1;
1245 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1246 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1247
1248 /* overwrite connection created by south bridge */
1249 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1250 }
1251
1252 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1253 "date");
1254
1255 #ifdef CONFIG_XEN_EMU
1256 if (xen_mode == XEN_EMULATE) {
1257 xen_overlay_create();
1258 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1259 xen_gnttab_create();
1260 xen_xenstore_create();
1261 if (pcms->bus) {
1262 pci_create_simple(pcms->bus, -1, "xen-platform");
1263 }
1264 xen_bus_init();
1265 xen_be_init();
1266 }
1267 #endif
1268
1269 qemu_register_boot_set(pc_boot_set, rtc_state);
1270
1271 if (!xen_enabled() &&
1272 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1273 if (kvm_pit_in_kernel()) {
1274 pit = kvm_pit_init(isa_bus, 0x40);
1275 } else {
1276 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1277 }
1278 if (hpet) {
1279 /* connect PIT to output control line of the HPET */
1280 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1281 }
1282 pcspk_init(pcms->pcspk, isa_bus, pit);
1283 }
1284
1285 /* Super I/O */
1286 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1287 pcms->vmport != ON_OFF_AUTO_ON);
1288 }
1289
1290 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1291 {
1292 MachineClass *mc = MACHINE_CLASS(pcmc);
1293 int i;
1294
1295 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1296 for (i = 0; i < nb_nics; i++) {
1297 NICInfo *nd = &nd_table[i];
1298 const char *model = nd->model ? nd->model : mc->default_nic;
1299
1300 if (g_str_equal(model, "ne2k_isa")) {
1301 pc_init_ne2k_isa(isa_bus, nd);
1302 } else {
1303 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1304 }
1305 }
1306 rom_reset_order_override();
1307 }
1308
1309 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1310 {
1311 qemu_irq *i8259;
1312
1313 if (kvm_pic_in_kernel()) {
1314 i8259 = kvm_i8259_init(isa_bus);
1315 } else if (xen_enabled()) {
1316 i8259 = xen_interrupt_controller_init();
1317 } else {
1318 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1319 }
1320
1321 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1322 i8259_irqs[i] = i8259[i];
1323 }
1324
1325 g_free(i8259);
1326 }
1327
1328 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1329 Error **errp)
1330 {
1331 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1332 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1333 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1334 const MachineState *ms = MACHINE(hotplug_dev);
1335 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1336 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1337 Error *local_err = NULL;
1338
1339 /*
1340 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1341 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1342 * addition to cover this case.
1343 */
1344 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1345 error_setg(errp,
1346 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1347 return;
1348 }
1349
1350 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1351 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1352 return;
1353 }
1354
1355 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1356 if (local_err) {
1357 error_propagate(errp, local_err);
1358 return;
1359 }
1360
1361 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1362 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1363 }
1364
1365 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1366 DeviceState *dev, Error **errp)
1367 {
1368 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1369 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1370 MachineState *ms = MACHINE(hotplug_dev);
1371 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1372
1373 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1374
1375 if (is_nvdimm) {
1376 nvdimm_plug(ms->nvdimms_state);
1377 }
1378
1379 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1380 }
1381
1382 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1383 DeviceState *dev, Error **errp)
1384 {
1385 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1386
1387 /*
1388 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1389 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1390 * addition to cover this case.
1391 */
1392 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1393 error_setg(errp,
1394 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1395 return;
1396 }
1397
1398 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1399 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1400 return;
1401 }
1402
1403 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1404 errp);
1405 }
1406
1407 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1408 DeviceState *dev, Error **errp)
1409 {
1410 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1411 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1412 Error *local_err = NULL;
1413
1414 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1415 if (local_err) {
1416 goto out;
1417 }
1418
1419 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1420 qdev_unrealize(dev);
1421 out:
1422 error_propagate(errp, local_err);
1423 }
1424
1425 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1426 DeviceState *dev, Error **errp)
1427 {
1428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1429 pc_memory_pre_plug(hotplug_dev, dev, errp);
1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1431 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1433 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1435 /* Declare the APIC range as the reserved MSI region */
1436 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1437 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1438
1439 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1440 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1441 resv_prop_str, errp);
1442 g_free(resv_prop_str);
1443 }
1444
1445 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1446 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1447 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1448
1449 if (pcms->iommu) {
1450 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1451 "for x86 yet.");
1452 return;
1453 }
1454 pcms->iommu = dev;
1455 }
1456 }
1457
1458 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1459 DeviceState *dev, Error **errp)
1460 {
1461 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1462 pc_memory_plug(hotplug_dev, dev, errp);
1463 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1464 x86_cpu_plug(hotplug_dev, dev, errp);
1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1466 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1467 }
1468 }
1469
1470 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1471 DeviceState *dev, Error **errp)
1472 {
1473 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1474 pc_memory_unplug_request(hotplug_dev, dev, errp);
1475 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1476 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1477 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1478 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1479 errp);
1480 } else {
1481 error_setg(errp, "acpi: device unplug request for not supported device"
1482 " type: %s", object_get_typename(OBJECT(dev)));
1483 }
1484 }
1485
1486 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1487 DeviceState *dev, Error **errp)
1488 {
1489 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1490 pc_memory_unplug(hotplug_dev, dev, errp);
1491 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1492 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1493 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1494 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1495 } else {
1496 error_setg(errp, "acpi: device unplug for not supported device"
1497 " type: %s", object_get_typename(OBJECT(dev)));
1498 }
1499 }
1500
1501 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1502 DeviceState *dev)
1503 {
1504 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1505 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1506 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1507 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1508 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1509 return HOTPLUG_HANDLER(machine);
1510 }
1511
1512 return NULL;
1513 }
1514
1515 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1516 void *opaque, Error **errp)
1517 {
1518 PCMachineState *pcms = PC_MACHINE(obj);
1519 OnOffAuto vmport = pcms->vmport;
1520
1521 visit_type_OnOffAuto(v, name, &vmport, errp);
1522 }
1523
1524 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1525 void *opaque, Error **errp)
1526 {
1527 PCMachineState *pcms = PC_MACHINE(obj);
1528
1529 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1530 }
1531
1532 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1533 {
1534 PCMachineState *pcms = PC_MACHINE(obj);
1535
1536 return pcms->smbus_enabled;
1537 }
1538
1539 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1540 {
1541 PCMachineState *pcms = PC_MACHINE(obj);
1542
1543 pcms->smbus_enabled = value;
1544 }
1545
1546 static bool pc_machine_get_sata(Object *obj, Error **errp)
1547 {
1548 PCMachineState *pcms = PC_MACHINE(obj);
1549
1550 return pcms->sata_enabled;
1551 }
1552
1553 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1554 {
1555 PCMachineState *pcms = PC_MACHINE(obj);
1556
1557 pcms->sata_enabled = value;
1558 }
1559
1560 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1561 {
1562 PCMachineState *pcms = PC_MACHINE(obj);
1563
1564 return pcms->hpet_enabled;
1565 }
1566
1567 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1568 {
1569 PCMachineState *pcms = PC_MACHINE(obj);
1570
1571 pcms->hpet_enabled = value;
1572 }
1573
1574 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1575 {
1576 PCMachineState *pcms = PC_MACHINE(obj);
1577
1578 return pcms->i8042_enabled;
1579 }
1580
1581 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1582 {
1583 PCMachineState *pcms = PC_MACHINE(obj);
1584
1585 pcms->i8042_enabled = value;
1586 }
1587
1588 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1589 {
1590 PCMachineState *pcms = PC_MACHINE(obj);
1591
1592 return pcms->default_bus_bypass_iommu;
1593 }
1594
1595 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1596 Error **errp)
1597 {
1598 PCMachineState *pcms = PC_MACHINE(obj);
1599
1600 pcms->default_bus_bypass_iommu = value;
1601 }
1602
1603 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1604 void *opaque, Error **errp)
1605 {
1606 PCMachineState *pcms = PC_MACHINE(obj);
1607 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1608
1609 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1610 }
1611
1612 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1613 void *opaque, Error **errp)
1614 {
1615 PCMachineState *pcms = PC_MACHINE(obj);
1616
1617 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1618 }
1619
1620 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1621 const char *name, void *opaque,
1622 Error **errp)
1623 {
1624 PCMachineState *pcms = PC_MACHINE(obj);
1625 uint64_t value = pcms->max_ram_below_4g;
1626
1627 visit_type_size(v, name, &value, errp);
1628 }
1629
1630 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1631 const char *name, void *opaque,
1632 Error **errp)
1633 {
1634 PCMachineState *pcms = PC_MACHINE(obj);
1635 uint64_t value;
1636
1637 if (!visit_type_size(v, name, &value, errp)) {
1638 return;
1639 }
1640 if (value > 4 * GiB) {
1641 error_setg(errp,
1642 "Machine option 'max-ram-below-4g=%"PRIu64
1643 "' expects size less than or equal to 4G", value);
1644 return;
1645 }
1646
1647 if (value < 1 * MiB) {
1648 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1649 "BIOS may not work with less than 1MiB", value);
1650 }
1651
1652 pcms->max_ram_below_4g = value;
1653 }
1654
1655 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1656 const char *name, void *opaque,
1657 Error **errp)
1658 {
1659 PCMachineState *pcms = PC_MACHINE(obj);
1660 uint64_t value = pcms->max_fw_size;
1661
1662 visit_type_size(v, name, &value, errp);
1663 }
1664
1665 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1666 const char *name, void *opaque,
1667 Error **errp)
1668 {
1669 PCMachineState *pcms = PC_MACHINE(obj);
1670 uint64_t value;
1671
1672 if (!visit_type_size(v, name, &value, errp)) {
1673 return;
1674 }
1675
1676 /*
1677 * We don't have a theoretically justifiable exact lower bound on the base
1678 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1679 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1680 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1681 * 16MiB in size.
1682 */
1683 if (value > 16 * MiB) {
1684 error_setg(errp,
1685 "User specified max allowed firmware size %" PRIu64 " is "
1686 "greater than 16MiB. If combined firmware size exceeds "
1687 "16MiB the system may not boot, or experience intermittent"
1688 "stability issues.",
1689 value);
1690 return;
1691 }
1692
1693 pcms->max_fw_size = value;
1694 }
1695
1696
1697 static void pc_machine_initfn(Object *obj)
1698 {
1699 PCMachineState *pcms = PC_MACHINE(obj);
1700 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1701
1702 #ifdef CONFIG_VMPORT
1703 pcms->vmport = ON_OFF_AUTO_AUTO;
1704 #else
1705 pcms->vmport = ON_OFF_AUTO_OFF;
1706 #endif /* CONFIG_VMPORT */
1707 pcms->max_ram_below_4g = 0; /* use default */
1708 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1709
1710 /* acpi build is enabled by default if machine supports it */
1711 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1712 pcms->smbus_enabled = true;
1713 pcms->sata_enabled = true;
1714 pcms->i8042_enabled = true;
1715 pcms->max_fw_size = 8 * MiB;
1716 #ifdef CONFIG_HPET
1717 pcms->hpet_enabled = true;
1718 #endif
1719 pcms->default_bus_bypass_iommu = false;
1720
1721 pc_system_flash_create(pcms);
1722 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1723 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1724 OBJECT(pcms->pcspk), "audiodev");
1725 cxl_machine_init(obj, &pcms->cxl_devices_state);
1726 }
1727
1728 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1729 {
1730 return 0;
1731 }
1732
1733 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1734 {
1735 CPUState *cs;
1736 X86CPU *cpu;
1737
1738 qemu_devices_reset(reason);
1739
1740 /* Reset APIC after devices have been reset to cancel
1741 * any changes that qemu_devices_reset() might have done.
1742 */
1743 CPU_FOREACH(cs) {
1744 cpu = X86_CPU(cs);
1745
1746 x86_cpu_after_reset(cpu);
1747 }
1748 }
1749
1750 static void pc_machine_wakeup(MachineState *machine)
1751 {
1752 cpu_synchronize_all_states();
1753 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1754 cpu_synchronize_all_post_reset();
1755 }
1756
1757 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1758 {
1759 X86IOMMUState *iommu = x86_iommu_get_default();
1760 IntelIOMMUState *intel_iommu;
1761
1762 if (iommu &&
1763 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1764 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1765 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1766 if (!intel_iommu->caching_mode) {
1767 error_setg(errp, "Device assignment is not allowed without "
1768 "enabling caching-mode=on for Intel IOMMU.");
1769 return false;
1770 }
1771 }
1772
1773 return true;
1774 }
1775
1776 static void pc_machine_class_init(ObjectClass *oc, void *data)
1777 {
1778 MachineClass *mc = MACHINE_CLASS(oc);
1779 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1780 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1781
1782 pcmc->pci_enabled = true;
1783 pcmc->has_acpi_build = true;
1784 pcmc->rsdp_in_ram = true;
1785 pcmc->smbios_defaults = true;
1786 pcmc->smbios_uuid_encoded = true;
1787 pcmc->gigabyte_align = true;
1788 pcmc->has_reserved_memory = true;
1789 pcmc->kvmclock_enabled = true;
1790 pcmc->enforce_aligned_dimm = true;
1791 pcmc->enforce_amd_1tb_hole = true;
1792 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1793 * to be used at the moment, 32K should be enough for a while. */
1794 pcmc->acpi_data_size = 0x20000 + 0x8000;
1795 pcmc->pvh_enabled = true;
1796 pcmc->kvmclock_create_always = true;
1797 pcmc->resizable_acpi_blob = true;
1798 assert(!mc->get_hotplug_handler);
1799 mc->get_hotplug_handler = pc_get_hotplug_handler;
1800 mc->hotplug_allowed = pc_hotplug_allowed;
1801 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1802 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1803 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1804 mc->auto_enable_numa_with_memhp = true;
1805 mc->auto_enable_numa_with_memdev = true;
1806 mc->has_hotpluggable_cpus = true;
1807 mc->default_boot_order = "cad";
1808 mc->block_default_type = IF_IDE;
1809 mc->max_cpus = 255;
1810 mc->reset = pc_machine_reset;
1811 mc->wakeup = pc_machine_wakeup;
1812 hc->pre_plug = pc_machine_device_pre_plug_cb;
1813 hc->plug = pc_machine_device_plug_cb;
1814 hc->unplug_request = pc_machine_device_unplug_request_cb;
1815 hc->unplug = pc_machine_device_unplug_cb;
1816 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1817 mc->nvdimm_supported = true;
1818 mc->smp_props.dies_supported = true;
1819 mc->default_ram_id = "pc.ram";
1820 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1821
1822 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1823 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1824 NULL, NULL);
1825 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1826 "Maximum ram below the 4G boundary (32bit boundary)");
1827
1828 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1829 pc_machine_get_vmport, pc_machine_set_vmport,
1830 NULL, NULL);
1831 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1832 "Enable vmport (pc & q35)");
1833
1834 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1835 pc_machine_get_smbus, pc_machine_set_smbus);
1836 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1837 "Enable/disable system management bus");
1838
1839 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1840 pc_machine_get_sata, pc_machine_set_sata);
1841 object_class_property_set_description(oc, PC_MACHINE_SATA,
1842 "Enable/disable Serial ATA bus");
1843
1844 object_class_property_add_bool(oc, "hpet",
1845 pc_machine_get_hpet, pc_machine_set_hpet);
1846 object_class_property_set_description(oc, "hpet",
1847 "Enable/disable high precision event timer emulation");
1848
1849 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1850 pc_machine_get_i8042, pc_machine_set_i8042);
1851
1852 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1853 pc_machine_get_default_bus_bypass_iommu,
1854 pc_machine_set_default_bus_bypass_iommu);
1855
1856 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1857 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1858 NULL, NULL);
1859 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1860 "Maximum combined firmware size");
1861
1862 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1863 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1864 NULL, NULL);
1865 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1866 "SMBIOS Entry Point type [32, 64]");
1867 }
1868
1869 static const TypeInfo pc_machine_info = {
1870 .name = TYPE_PC_MACHINE,
1871 .parent = TYPE_X86_MACHINE,
1872 .abstract = true,
1873 .instance_size = sizeof(PCMachineState),
1874 .instance_init = pc_machine_initfn,
1875 .class_size = sizeof(PCMachineClass),
1876 .class_init = pc_machine_class_init,
1877 .interfaces = (InterfaceInfo[]) {
1878 { TYPE_HOTPLUG_HANDLER },
1879 { }
1880 },
1881 };
1882
1883 static void pc_machine_register_types(void)
1884 {
1885 type_register_static(&pc_machine_info);
1886 }
1887
1888 type_init(pc_machine_register_types)
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