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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "qapi/error.h"
80 #include "qapi/qapi-visit-common.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/mem/memory-device.h"
89 #include "sysemu/replay.h"
90 #include "qapi/qmp/qerror.h"
91 #include "config-devices.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95
96 GlobalProperty pc_compat_4_2[] = {
97 { "mch", "smbase-smram", "off" },
98 };
99 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
100
101 GlobalProperty pc_compat_4_1[] = {};
102 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
103
104 GlobalProperty pc_compat_4_0[] = {};
105 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
106
107 GlobalProperty pc_compat_3_1[] = {
108 { "intel-iommu", "dma-drain", "off" },
109 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
110 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
111 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
112 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
113 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
114 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
115 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
116 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
117 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
119 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
120 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
121 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
122 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
123 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
124 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
125 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
126 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
128 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
129 };
130 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
131
132 GlobalProperty pc_compat_3_0[] = {
133 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
134 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
135 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
136 };
137 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
138
139 GlobalProperty pc_compat_2_12[] = {
140 { TYPE_X86_CPU, "legacy-cache", "on" },
141 { TYPE_X86_CPU, "topoext", "off" },
142 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
143 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
144 };
145 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
146
147 GlobalProperty pc_compat_2_11[] = {
148 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
149 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
150 };
151 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
152
153 GlobalProperty pc_compat_2_10[] = {
154 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
155 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
156 { "q35-pcihost", "x-pci-hole64-fix", "off" },
157 };
158 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
159
160 GlobalProperty pc_compat_2_9[] = {
161 { "mch", "extended-tseg-mbytes", "0" },
162 };
163 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
164
165 GlobalProperty pc_compat_2_8[] = {
166 { TYPE_X86_CPU, "tcg-cpuid", "off" },
167 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
168 { "ICH9-LPC", "x-smi-broadcast", "off" },
169 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
170 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
171 };
172 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
173
174 GlobalProperty pc_compat_2_7[] = {
175 { TYPE_X86_CPU, "l3-cache", "off" },
176 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
177 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
178 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
179 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
180 { "isa-pcspk", "migrate", "off" },
181 };
182 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
183
184 GlobalProperty pc_compat_2_6[] = {
185 { TYPE_X86_CPU, "cpuid-0xb", "off" },
186 { "vmxnet3", "romfile", "" },
187 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
188 { "apic-common", "legacy-instance-id", "on", }
189 };
190 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
191
192 GlobalProperty pc_compat_2_5[] = {};
193 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
194
195 GlobalProperty pc_compat_2_4[] = {
196 PC_CPU_MODEL_IDS("2.4.0")
197 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
198 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
199 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
200 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
201 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
202 { TYPE_X86_CPU, "check", "off" },
203 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
204 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
205 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
206 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
207 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
208 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
209 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
210 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
211 };
212 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
213
214 GlobalProperty pc_compat_2_3[] = {
215 PC_CPU_MODEL_IDS("2.3.0")
216 { TYPE_X86_CPU, "arat", "off" },
217 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
218 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
219 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
220 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
221 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
222 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
223 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
224 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
225 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
226 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
227 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
228 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
229 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
236 };
237 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
238
239 GlobalProperty pc_compat_2_2[] = {
240 PC_CPU_MODEL_IDS("2.2.0")
241 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
242 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
243 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
244 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
245 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
246 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
247 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
256 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
257 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
258 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
259 };
260 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
261
262 GlobalProperty pc_compat_2_1[] = {
263 PC_CPU_MODEL_IDS("2.1.0")
264 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
265 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
266 };
267 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
268
269 GlobalProperty pc_compat_2_0[] = {
270 PC_CPU_MODEL_IDS("2.0.0")
271 { "virtio-scsi-pci", "any_layout", "off" },
272 { "PIIX4_PM", "memory-hotplug-support", "off" },
273 { "apic", "version", "0x11" },
274 { "nec-usb-xhci", "superspeed-ports-first", "off" },
275 { "nec-usb-xhci", "force-pcie-endcap", "on" },
276 { "pci-serial", "prog_if", "0" },
277 { "pci-serial-2x", "prog_if", "0" },
278 { "pci-serial-4x", "prog_if", "0" },
279 { "virtio-net-pci", "guest_announce", "off" },
280 { "ICH9-LPC", "memory-hotplug-support", "off" },
281 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
282 { "ioh3420", COMPAT_PROP_PCP, "off" },
283 };
284 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
285
286 GlobalProperty pc_compat_1_7[] = {
287 PC_CPU_MODEL_IDS("1.7.0")
288 { TYPE_USB_DEVICE, "msos-desc", "no" },
289 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
290 { "hpet", HPET_INTCAP, "4" },
291 };
292 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
293
294 GlobalProperty pc_compat_1_6[] = {
295 PC_CPU_MODEL_IDS("1.6.0")
296 { "e1000", "mitigation", "off" },
297 { "qemu64-" TYPE_X86_CPU, "model", "2" },
298 { "qemu32-" TYPE_X86_CPU, "model", "3" },
299 { "i440FX-pcihost", "short_root_bus", "1" },
300 { "q35-pcihost", "short_root_bus", "1" },
301 };
302 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
303
304 GlobalProperty pc_compat_1_5[] = {
305 PC_CPU_MODEL_IDS("1.5.0")
306 { "Conroe-" TYPE_X86_CPU, "model", "2" },
307 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
308 { "Penryn-" TYPE_X86_CPU, "model", "2" },
309 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
310 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
311 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
312 { "virtio-net-pci", "any_layout", "off" },
313 { TYPE_X86_CPU, "pmu", "on" },
314 { "i440FX-pcihost", "short_root_bus", "0" },
315 { "q35-pcihost", "short_root_bus", "0" },
316 };
317 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
318
319 GlobalProperty pc_compat_1_4[] = {
320 PC_CPU_MODEL_IDS("1.4.0")
321 { "scsi-hd", "discard_granularity", "0" },
322 { "scsi-cd", "discard_granularity", "0" },
323 { "scsi-disk", "discard_granularity", "0" },
324 { "ide-hd", "discard_granularity", "0" },
325 { "ide-cd", "discard_granularity", "0" },
326 { "ide-drive", "discard_granularity", "0" },
327 { "virtio-blk-pci", "discard_granularity", "0" },
328 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
329 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
330 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
331 { "e1000", "romfile", "pxe-e1000.rom" },
332 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
333 { "pcnet", "romfile", "pxe-pcnet.rom" },
334 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
335 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
336 { "486-" TYPE_X86_CPU, "model", "0" },
337 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
338 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
339 };
340 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
341
342 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
343 {
344 GSIState *s;
345
346 s = g_new0(GSIState, 1);
347 if (kvm_ioapic_in_kernel()) {
348 kvm_pc_setup_irq_routing(pci_enabled);
349 }
350 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
351
352 return s;
353 }
354
355 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
356 unsigned size)
357 {
358 }
359
360 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
361 {
362 return 0xffffffffffffffffULL;
363 }
364
365 /* MSDOS compatibility mode FPU exception support */
366 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
367 unsigned size)
368 {
369 if (tcg_enabled()) {
370 cpu_set_ignne();
371 }
372 }
373
374 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
375 {
376 return 0xffffffffffffffffULL;
377 }
378
379 /* PC cmos mappings */
380
381 #define REG_EQUIPMENT_BYTE 0x14
382
383 int cmos_get_fd_drive_type(FloppyDriveType fd0)
384 {
385 int val;
386
387 switch (fd0) {
388 case FLOPPY_DRIVE_TYPE_144:
389 /* 1.44 Mb 3"5 drive */
390 val = 4;
391 break;
392 case FLOPPY_DRIVE_TYPE_288:
393 /* 2.88 Mb 3"5 drive */
394 val = 5;
395 break;
396 case FLOPPY_DRIVE_TYPE_120:
397 /* 1.2 Mb 5"5 drive */
398 val = 2;
399 break;
400 case FLOPPY_DRIVE_TYPE_NONE:
401 default:
402 val = 0;
403 break;
404 }
405 return val;
406 }
407
408 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
409 int16_t cylinders, int8_t heads, int8_t sectors)
410 {
411 rtc_set_memory(s, type_ofs, 47);
412 rtc_set_memory(s, info_ofs, cylinders);
413 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
414 rtc_set_memory(s, info_ofs + 2, heads);
415 rtc_set_memory(s, info_ofs + 3, 0xff);
416 rtc_set_memory(s, info_ofs + 4, 0xff);
417 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
418 rtc_set_memory(s, info_ofs + 6, cylinders);
419 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
420 rtc_set_memory(s, info_ofs + 8, sectors);
421 }
422
423 /* convert boot_device letter to something recognizable by the bios */
424 static int boot_device2nibble(char boot_device)
425 {
426 switch(boot_device) {
427 case 'a':
428 case 'b':
429 return 0x01; /* floppy boot */
430 case 'c':
431 return 0x02; /* hard drive boot */
432 case 'd':
433 return 0x03; /* CD-ROM boot */
434 case 'n':
435 return 0x04; /* Network boot */
436 }
437 return 0;
438 }
439
440 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
441 {
442 #define PC_MAX_BOOT_DEVICES 3
443 int nbds, bds[3] = { 0, };
444 int i;
445
446 nbds = strlen(boot_device);
447 if (nbds > PC_MAX_BOOT_DEVICES) {
448 error_setg(errp, "Too many boot devices for PC");
449 return;
450 }
451 for (i = 0; i < nbds; i++) {
452 bds[i] = boot_device2nibble(boot_device[i]);
453 if (bds[i] == 0) {
454 error_setg(errp, "Invalid boot device for PC: '%c'",
455 boot_device[i]);
456 return;
457 }
458 }
459 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
460 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
461 }
462
463 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
464 {
465 set_boot_dev(opaque, boot_device, errp);
466 }
467
468 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
469 {
470 int val, nb, i;
471 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
472 FLOPPY_DRIVE_TYPE_NONE };
473
474 /* floppy type */
475 if (floppy) {
476 for (i = 0; i < 2; i++) {
477 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
478 }
479 }
480 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
481 cmos_get_fd_drive_type(fd_type[1]);
482 rtc_set_memory(rtc_state, 0x10, val);
483
484 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
485 nb = 0;
486 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
487 nb++;
488 }
489 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
490 nb++;
491 }
492 switch (nb) {
493 case 0:
494 break;
495 case 1:
496 val |= 0x01; /* 1 drive, ready for boot */
497 break;
498 case 2:
499 val |= 0x41; /* 2 drives, ready for boot */
500 break;
501 }
502 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
503 }
504
505 typedef struct pc_cmos_init_late_arg {
506 ISADevice *rtc_state;
507 BusState *idebus[2];
508 } pc_cmos_init_late_arg;
509
510 typedef struct check_fdc_state {
511 ISADevice *floppy;
512 bool multiple;
513 } CheckFdcState;
514
515 static int check_fdc(Object *obj, void *opaque)
516 {
517 CheckFdcState *state = opaque;
518 Object *fdc;
519 uint32_t iobase;
520 Error *local_err = NULL;
521
522 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
523 if (!fdc) {
524 return 0;
525 }
526
527 iobase = object_property_get_uint(obj, "iobase", &local_err);
528 if (local_err || iobase != 0x3f0) {
529 error_free(local_err);
530 return 0;
531 }
532
533 if (state->floppy) {
534 state->multiple = true;
535 } else {
536 state->floppy = ISA_DEVICE(obj);
537 }
538 return 0;
539 }
540
541 static const char * const fdc_container_path[] = {
542 "/unattached", "/peripheral", "/peripheral-anon"
543 };
544
545 /*
546 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
547 * and ACPI objects.
548 */
549 ISADevice *pc_find_fdc0(void)
550 {
551 int i;
552 Object *container;
553 CheckFdcState state = { 0 };
554
555 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
556 container = container_get(qdev_get_machine(), fdc_container_path[i]);
557 object_child_foreach(container, check_fdc, &state);
558 }
559
560 if (state.multiple) {
561 warn_report("multiple floppy disk controllers with "
562 "iobase=0x3f0 have been found");
563 error_printf("the one being picked for CMOS setup might not reflect "
564 "your intent");
565 }
566
567 return state.floppy;
568 }
569
570 static void pc_cmos_init_late(void *opaque)
571 {
572 pc_cmos_init_late_arg *arg = opaque;
573 ISADevice *s = arg->rtc_state;
574 int16_t cylinders;
575 int8_t heads, sectors;
576 int val;
577 int i, trans;
578
579 val = 0;
580 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
581 &cylinders, &heads, &sectors) >= 0) {
582 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
583 val |= 0xf0;
584 }
585 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
586 &cylinders, &heads, &sectors) >= 0) {
587 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
588 val |= 0x0f;
589 }
590 rtc_set_memory(s, 0x12, val);
591
592 val = 0;
593 for (i = 0; i < 4; i++) {
594 /* NOTE: ide_get_geometry() returns the physical
595 geometry. It is always such that: 1 <= sects <= 63, 1
596 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
597 geometry can be different if a translation is done. */
598 if (arg->idebus[i / 2] &&
599 ide_get_geometry(arg->idebus[i / 2], i % 2,
600 &cylinders, &heads, &sectors) >= 0) {
601 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
602 assert((trans & ~3) == 0);
603 val |= trans << (i * 2);
604 }
605 }
606 rtc_set_memory(s, 0x39, val);
607
608 pc_cmos_init_floppy(s, pc_find_fdc0());
609
610 qemu_unregister_reset(pc_cmos_init_late, opaque);
611 }
612
613 void pc_cmos_init(PCMachineState *pcms,
614 BusState *idebus0, BusState *idebus1,
615 ISADevice *s)
616 {
617 int val;
618 static pc_cmos_init_late_arg arg;
619 X86MachineState *x86ms = X86_MACHINE(pcms);
620
621 /* various important CMOS locations needed by PC/Bochs bios */
622
623 /* memory size */
624 /* base memory (first MiB) */
625 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
626 rtc_set_memory(s, 0x15, val);
627 rtc_set_memory(s, 0x16, val >> 8);
628 /* extended memory (next 64MiB) */
629 if (x86ms->below_4g_mem_size > 1 * MiB) {
630 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
631 } else {
632 val = 0;
633 }
634 if (val > 65535)
635 val = 65535;
636 rtc_set_memory(s, 0x17, val);
637 rtc_set_memory(s, 0x18, val >> 8);
638 rtc_set_memory(s, 0x30, val);
639 rtc_set_memory(s, 0x31, val >> 8);
640 /* memory between 16MiB and 4GiB */
641 if (x86ms->below_4g_mem_size > 16 * MiB) {
642 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
643 } else {
644 val = 0;
645 }
646 if (val > 65535)
647 val = 65535;
648 rtc_set_memory(s, 0x34, val);
649 rtc_set_memory(s, 0x35, val >> 8);
650 /* memory above 4GiB */
651 val = x86ms->above_4g_mem_size / 65536;
652 rtc_set_memory(s, 0x5b, val);
653 rtc_set_memory(s, 0x5c, val >> 8);
654 rtc_set_memory(s, 0x5d, val >> 16);
655
656 object_property_add_link(OBJECT(pcms), "rtc_state",
657 TYPE_ISA_DEVICE,
658 (Object **)&x86ms->rtc,
659 object_property_allow_set_link,
660 OBJ_PROP_LINK_STRONG, &error_abort);
661 object_property_set_link(OBJECT(pcms), OBJECT(s),
662 "rtc_state", &error_abort);
663
664 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
665
666 val = 0;
667 val |= 0x02; /* FPU is there */
668 val |= 0x04; /* PS/2 mouse installed */
669 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
670
671 /* hard drives and FDC */
672 arg.rtc_state = s;
673 arg.idebus[0] = idebus0;
674 arg.idebus[1] = idebus1;
675 qemu_register_reset(pc_cmos_init_late, &arg);
676 }
677
678 static void handle_a20_line_change(void *opaque, int irq, int level)
679 {
680 X86CPU *cpu = opaque;
681
682 /* XXX: send to all CPUs ? */
683 /* XXX: add logic to handle multiple A20 line sources */
684 x86_cpu_set_a20(cpu, level);
685 }
686
687 #define NE2000_NB_MAX 6
688
689 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
690 0x280, 0x380 };
691 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
692
693 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
694 {
695 static int nb_ne2k = 0;
696
697 if (nb_ne2k == NE2000_NB_MAX)
698 return;
699 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
700 ne2000_irq[nb_ne2k], nd);
701 nb_ne2k++;
702 }
703
704 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
705 {
706 X86CPU *cpu = opaque;
707
708 if (level) {
709 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
710 }
711 }
712
713 /*
714 * This function is very similar to smp_parse()
715 * in hw/core/machine.c but includes CPU die support.
716 */
717 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
718 {
719 X86MachineState *x86ms = X86_MACHINE(ms);
720
721 if (opts) {
722 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
723 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
724 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
725 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
726 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
727
728 /* compute missing values, prefer sockets over cores over threads */
729 if (cpus == 0 || sockets == 0) {
730 cores = cores > 0 ? cores : 1;
731 threads = threads > 0 ? threads : 1;
732 if (cpus == 0) {
733 sockets = sockets > 0 ? sockets : 1;
734 cpus = cores * threads * dies * sockets;
735 } else {
736 ms->smp.max_cpus =
737 qemu_opt_get_number(opts, "maxcpus", cpus);
738 sockets = ms->smp.max_cpus / (cores * threads * dies);
739 }
740 } else if (cores == 0) {
741 threads = threads > 0 ? threads : 1;
742 cores = cpus / (sockets * dies * threads);
743 cores = cores > 0 ? cores : 1;
744 } else if (threads == 0) {
745 threads = cpus / (cores * dies * sockets);
746 threads = threads > 0 ? threads : 1;
747 } else if (sockets * dies * cores * threads < cpus) {
748 error_report("cpu topology: "
749 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
750 "smp_cpus (%u)",
751 sockets, dies, cores, threads, cpus);
752 exit(1);
753 }
754
755 ms->smp.max_cpus =
756 qemu_opt_get_number(opts, "maxcpus", cpus);
757
758 if (ms->smp.max_cpus < cpus) {
759 error_report("maxcpus must be equal to or greater than smp");
760 exit(1);
761 }
762
763 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
764 error_report("cpu topology: "
765 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
766 "maxcpus (%u)",
767 sockets, dies, cores, threads,
768 ms->smp.max_cpus);
769 exit(1);
770 }
771
772 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
773 warn_report("Invalid CPU topology deprecated: "
774 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
775 "!= maxcpus (%u)",
776 sockets, dies, cores, threads,
777 ms->smp.max_cpus);
778 }
779
780 ms->smp.cpus = cpus;
781 ms->smp.cores = cores;
782 ms->smp.threads = threads;
783 x86ms->smp_dies = dies;
784 }
785
786 if (ms->smp.cpus > 1) {
787 Error *blocker = NULL;
788 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
789 replay_add_blocker(blocker);
790 }
791 }
792
793 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
794 {
795 X86MachineState *x86ms = X86_MACHINE(ms);
796 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
797 Error *local_err = NULL;
798
799 if (id < 0) {
800 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
801 return;
802 }
803
804 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
805 error_setg(errp, "Unable to add CPU: %" PRIi64
806 ", resulting APIC ID (%" PRIi64 ") is too large",
807 id, apic_id);
808 return;
809 }
810
811
812 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
813 if (local_err) {
814 error_propagate(errp, local_err);
815 return;
816 }
817 }
818
819 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
820 {
821 if (cpus_count > 0xff) {
822 /* If the number of CPUs can't be represented in 8 bits, the
823 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
824 * to make old BIOSes fail more predictably.
825 */
826 rtc_set_memory(rtc, 0x5f, 0);
827 } else {
828 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
829 }
830 }
831
832 static
833 void pc_machine_done(Notifier *notifier, void *data)
834 {
835 PCMachineState *pcms = container_of(notifier,
836 PCMachineState, machine_done);
837 X86MachineState *x86ms = X86_MACHINE(pcms);
838 PCIBus *bus = pcms->bus;
839
840 /* set the number of CPUs */
841 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
842
843 if (bus) {
844 int extra_hosts = 0;
845
846 QLIST_FOREACH(bus, &bus->child, sibling) {
847 /* look for expander root buses */
848 if (pci_bus_is_root(bus)) {
849 extra_hosts++;
850 }
851 }
852 if (extra_hosts && x86ms->fw_cfg) {
853 uint64_t *val = g_malloc(sizeof(*val));
854 *val = cpu_to_le64(extra_hosts);
855 fw_cfg_add_file(x86ms->fw_cfg,
856 "etc/extra-pci-roots", val, sizeof(*val));
857 }
858 }
859
860 acpi_setup();
861 if (x86ms->fw_cfg) {
862 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
863 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
864 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
865 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
866 }
867
868 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
869 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
870
871 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
872 iommu->intr_eim != ON_OFF_AUTO_ON) {
873 error_report("current -smp configuration requires "
874 "Extended Interrupt Mode enabled. "
875 "You can add an IOMMU using: "
876 "-device intel-iommu,intremap=on,eim=on");
877 exit(EXIT_FAILURE);
878 }
879 }
880 }
881
882 void pc_guest_info_init(PCMachineState *pcms)
883 {
884 int i;
885 MachineState *ms = MACHINE(pcms);
886 X86MachineState *x86ms = X86_MACHINE(pcms);
887
888 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
889 pcms->numa_nodes = ms->numa_state->num_nodes;
890 pcms->node_mem = g_malloc0(pcms->numa_nodes *
891 sizeof *pcms->node_mem);
892 for (i = 0; i < ms->numa_state->num_nodes; i++) {
893 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
894 }
895
896 pcms->machine_done.notify = pc_machine_done;
897 qemu_add_machine_init_done_notifier(&pcms->machine_done);
898 }
899
900 /* setup pci memory address space mapping into system address space */
901 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
902 MemoryRegion *pci_address_space)
903 {
904 /* Set to lower priority than RAM */
905 memory_region_add_subregion_overlap(system_memory, 0x0,
906 pci_address_space, -1);
907 }
908
909 void xen_load_linux(PCMachineState *pcms)
910 {
911 int i;
912 FWCfgState *fw_cfg;
913 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
914 X86MachineState *x86ms = X86_MACHINE(pcms);
915
916 assert(MACHINE(pcms)->kernel_filename != NULL);
917
918 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
919 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
920 rom_set_fw(fw_cfg);
921
922 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
923 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
924 for (i = 0; i < nb_option_roms; i++) {
925 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
926 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
927 !strcmp(option_rom[i].name, "pvh.bin") ||
928 !strcmp(option_rom[i].name, "multiboot.bin"));
929 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
930 }
931 x86ms->fw_cfg = fw_cfg;
932 }
933
934 void pc_memory_init(PCMachineState *pcms,
935 MemoryRegion *system_memory,
936 MemoryRegion *rom_memory,
937 MemoryRegion **ram_memory)
938 {
939 int linux_boot, i;
940 MemoryRegion *ram, *option_rom_mr;
941 MemoryRegion *ram_below_4g, *ram_above_4g;
942 FWCfgState *fw_cfg;
943 MachineState *machine = MACHINE(pcms);
944 MachineClass *mc = MACHINE_GET_CLASS(machine);
945 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
946 X86MachineState *x86ms = X86_MACHINE(pcms);
947
948 assert(machine->ram_size == x86ms->below_4g_mem_size +
949 x86ms->above_4g_mem_size);
950
951 linux_boot = (machine->kernel_filename != NULL);
952
953 /* Allocate RAM. We allocate it as a single memory region and use
954 * aliases to address portions of it, mostly for backwards compatibility
955 * with older qemus that used qemu_ram_alloc().
956 */
957 ram = g_malloc(sizeof(*ram));
958 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
959 machine->ram_size);
960 *ram_memory = ram;
961 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
962 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
963 0, x86ms->below_4g_mem_size);
964 memory_region_add_subregion(system_memory, 0, ram_below_4g);
965 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
966 if (x86ms->above_4g_mem_size > 0) {
967 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
968 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
969 x86ms->below_4g_mem_size,
970 x86ms->above_4g_mem_size);
971 memory_region_add_subregion(system_memory, 0x100000000ULL,
972 ram_above_4g);
973 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
974 }
975
976 if (!pcmc->has_reserved_memory &&
977 (machine->ram_slots ||
978 (machine->maxram_size > machine->ram_size))) {
979
980 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
981 mc->name);
982 exit(EXIT_FAILURE);
983 }
984
985 /* always allocate the device memory information */
986 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
987
988 /* initialize device memory address space */
989 if (pcmc->has_reserved_memory &&
990 (machine->ram_size < machine->maxram_size)) {
991 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
992
993 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
994 error_report("unsupported amount of memory slots: %"PRIu64,
995 machine->ram_slots);
996 exit(EXIT_FAILURE);
997 }
998
999 if (QEMU_ALIGN_UP(machine->maxram_size,
1000 TARGET_PAGE_SIZE) != machine->maxram_size) {
1001 error_report("maximum memory size must by aligned to multiple of "
1002 "%d bytes", TARGET_PAGE_SIZE);
1003 exit(EXIT_FAILURE);
1004 }
1005
1006 machine->device_memory->base =
1007 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1008
1009 if (pcmc->enforce_aligned_dimm) {
1010 /* size device region assuming 1G page max alignment per slot */
1011 device_mem_size += (1 * GiB) * machine->ram_slots;
1012 }
1013
1014 if ((machine->device_memory->base + device_mem_size) <
1015 device_mem_size) {
1016 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1017 machine->maxram_size);
1018 exit(EXIT_FAILURE);
1019 }
1020
1021 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1022 "device-memory", device_mem_size);
1023 memory_region_add_subregion(system_memory, machine->device_memory->base,
1024 &machine->device_memory->mr);
1025 }
1026
1027 /* Initialize PC system firmware */
1028 pc_system_firmware_init(pcms, rom_memory);
1029
1030 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1031 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1032 &error_fatal);
1033 if (pcmc->pci_enabled) {
1034 memory_region_set_readonly(option_rom_mr, true);
1035 }
1036 memory_region_add_subregion_overlap(rom_memory,
1037 PC_ROM_MIN_VGA,
1038 option_rom_mr,
1039 1);
1040
1041 fw_cfg = fw_cfg_arch_create(machine,
1042 x86ms->boot_cpus, x86ms->apic_id_limit);
1043
1044 rom_set_fw(fw_cfg);
1045
1046 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1047 uint64_t *val = g_malloc(sizeof(*val));
1048 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1049 uint64_t res_mem_end = machine->device_memory->base;
1050
1051 if (!pcmc->broken_reserved_end) {
1052 res_mem_end += memory_region_size(&machine->device_memory->mr);
1053 }
1054 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1055 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1056 }
1057
1058 if (linux_boot) {
1059 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1060 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1061 }
1062
1063 for (i = 0; i < nb_option_roms; i++) {
1064 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1065 }
1066 x86ms->fw_cfg = fw_cfg;
1067
1068 /* Init default IOAPIC address space */
1069 x86ms->ioapic_as = &address_space_memory;
1070
1071 /* Init ACPI memory hotplug IO base address */
1072 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1073 }
1074
1075 /*
1076 * The 64bit pci hole starts after "above 4G RAM" and
1077 * potentially the space reserved for memory hotplug.
1078 */
1079 uint64_t pc_pci_hole64_start(void)
1080 {
1081 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1082 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1083 MachineState *ms = MACHINE(pcms);
1084 X86MachineState *x86ms = X86_MACHINE(pcms);
1085 uint64_t hole64_start = 0;
1086
1087 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1088 hole64_start = ms->device_memory->base;
1089 if (!pcmc->broken_reserved_end) {
1090 hole64_start += memory_region_size(&ms->device_memory->mr);
1091 }
1092 } else {
1093 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1094 }
1095
1096 return ROUND_UP(hole64_start, 1 * GiB);
1097 }
1098
1099 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1100 {
1101 DeviceState *dev = NULL;
1102
1103 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1104 if (pci_bus) {
1105 PCIDevice *pcidev = pci_vga_init(pci_bus);
1106 dev = pcidev ? &pcidev->qdev : NULL;
1107 } else if (isa_bus) {
1108 ISADevice *isadev = isa_vga_init(isa_bus);
1109 dev = isadev ? DEVICE(isadev) : NULL;
1110 }
1111 rom_reset_order_override();
1112 return dev;
1113 }
1114
1115 static const MemoryRegionOps ioport80_io_ops = {
1116 .write = ioport80_write,
1117 .read = ioport80_read,
1118 .endianness = DEVICE_NATIVE_ENDIAN,
1119 .impl = {
1120 .min_access_size = 1,
1121 .max_access_size = 1,
1122 },
1123 };
1124
1125 static const MemoryRegionOps ioportF0_io_ops = {
1126 .write = ioportF0_write,
1127 .read = ioportF0_read,
1128 .endianness = DEVICE_NATIVE_ENDIAN,
1129 .impl = {
1130 .min_access_size = 1,
1131 .max_access_size = 1,
1132 },
1133 };
1134
1135 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1136 {
1137 int i;
1138 DriveInfo *fd[MAX_FD];
1139 qemu_irq *a20_line;
1140 ISADevice *i8042, *port92, *vmmouse;
1141
1142 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1143 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1144
1145 for (i = 0; i < MAX_FD; i++) {
1146 fd[i] = drive_get(IF_FLOPPY, 0, i);
1147 create_fdctrl |= !!fd[i];
1148 }
1149 if (create_fdctrl) {
1150 fdctrl_init_isa(isa_bus, fd);
1151 }
1152
1153 i8042 = isa_create_simple(isa_bus, "i8042");
1154 if (!no_vmport) {
1155 vmport_init(isa_bus);
1156 vmmouse = isa_try_create(isa_bus, "vmmouse");
1157 } else {
1158 vmmouse = NULL;
1159 }
1160 if (vmmouse) {
1161 object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
1162 "i8042", &error_abort);
1163 qdev_init_nofail(DEVICE(vmmouse));
1164 }
1165 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1166
1167 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1168 i8042_setup_a20_line(i8042, a20_line[0]);
1169 qdev_connect_gpio_out_named(DEVICE(port92),
1170 PORT92_A20_LINE, 0, a20_line[1]);
1171 g_free(a20_line);
1172 }
1173
1174 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1175 ISADevice **rtc_state,
1176 bool create_fdctrl,
1177 bool no_vmport,
1178 bool has_pit,
1179 uint32_t hpet_irqs)
1180 {
1181 int i;
1182 DeviceState *hpet = NULL;
1183 int pit_isa_irq = 0;
1184 qemu_irq pit_alt_irq = NULL;
1185 qemu_irq rtc_irq = NULL;
1186 ISADevice *pit = NULL;
1187 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1188 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1189
1190 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1191 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1192
1193 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1194 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1195
1196 /*
1197 * Check if an HPET shall be created.
1198 *
1199 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1200 * when the HPET wants to take over. Thus we have to disable the latter.
1201 */
1202 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1203 hpet = qdev_try_create(NULL, TYPE_HPET);
1204 if (hpet) {
1205 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1206 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1207 * IRQ8 and IRQ2.
1208 */
1209 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1210 HPET_INTCAP, NULL);
1211 if (!compat) {
1212 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1213 }
1214 qdev_init_nofail(hpet);
1215 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1216
1217 for (i = 0; i < GSI_NUM_PINS; i++) {
1218 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1219 }
1220 pit_isa_irq = -1;
1221 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1222 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1223 }
1224 }
1225 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1226
1227 qemu_register_boot_set(pc_boot_set, *rtc_state);
1228
1229 if (!xen_enabled() && has_pit) {
1230 if (kvm_pit_in_kernel()) {
1231 pit = kvm_pit_init(isa_bus, 0x40);
1232 } else {
1233 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1234 }
1235 if (hpet) {
1236 /* connect PIT to output control line of the HPET */
1237 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1238 }
1239 pcspk_init(isa_bus, pit);
1240 }
1241
1242 i8257_dma_init(isa_bus, 0);
1243
1244 /* Super I/O */
1245 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1246 }
1247
1248 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1249 {
1250 int i;
1251
1252 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1253 for (i = 0; i < nb_nics; i++) {
1254 NICInfo *nd = &nd_table[i];
1255 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1256
1257 if (g_str_equal(model, "ne2k_isa")) {
1258 pc_init_ne2k_isa(isa_bus, nd);
1259 } else {
1260 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1261 }
1262 }
1263 rom_reset_order_override();
1264 }
1265
1266 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1267 {
1268 qemu_irq *i8259;
1269
1270 if (kvm_pic_in_kernel()) {
1271 i8259 = kvm_i8259_init(isa_bus);
1272 } else if (xen_enabled()) {
1273 i8259 = xen_interrupt_controller_init();
1274 } else {
1275 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1276 }
1277
1278 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1279 i8259_irqs[i] = i8259[i];
1280 }
1281
1282 g_free(i8259);
1283 }
1284
1285 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1286 Error **errp)
1287 {
1288 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1289 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1290 const MachineState *ms = MACHINE(hotplug_dev);
1291 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1292 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1293 Error *local_err = NULL;
1294
1295 /*
1296 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1297 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1298 * addition to cover this case.
1299 */
1300 if (!pcms->acpi_dev || !acpi_enabled) {
1301 error_setg(errp,
1302 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1303 return;
1304 }
1305
1306 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1307 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1308 return;
1309 }
1310
1311 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1312 if (local_err) {
1313 error_propagate(errp, local_err);
1314 return;
1315 }
1316
1317 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1318 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1319 }
1320
1321 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1322 DeviceState *dev, Error **errp)
1323 {
1324 Error *local_err = NULL;
1325 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1326 MachineState *ms = MACHINE(hotplug_dev);
1327 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1328
1329 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1330 if (local_err) {
1331 goto out;
1332 }
1333
1334 if (is_nvdimm) {
1335 nvdimm_plug(ms->nvdimms_state);
1336 }
1337
1338 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1339 out:
1340 error_propagate(errp, local_err);
1341 }
1342
1343 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1344 DeviceState *dev, Error **errp)
1345 {
1346 Error *local_err = NULL;
1347 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1348
1349 /*
1350 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1351 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1352 * addition to cover this case.
1353 */
1354 if (!pcms->acpi_dev || !acpi_enabled) {
1355 error_setg(&local_err,
1356 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1357 goto out;
1358 }
1359
1360 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1361 error_setg(&local_err,
1362 "nvdimm device hot unplug is not supported yet.");
1363 goto out;
1364 }
1365
1366 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1367 &local_err);
1368 out:
1369 error_propagate(errp, local_err);
1370 }
1371
1372 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1373 DeviceState *dev, Error **errp)
1374 {
1375 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1376 Error *local_err = NULL;
1377
1378 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1379 if (local_err) {
1380 goto out;
1381 }
1382
1383 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1384 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1385 out:
1386 error_propagate(errp, local_err);
1387 }
1388
1389 static int pc_apic_cmp(const void *a, const void *b)
1390 {
1391 CPUArchId *apic_a = (CPUArchId *)a;
1392 CPUArchId *apic_b = (CPUArchId *)b;
1393
1394 return apic_a->arch_id - apic_b->arch_id;
1395 }
1396
1397 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1398 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1399 * entry corresponding to CPU's apic_id returns NULL.
1400 */
1401 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1402 {
1403 CPUArchId apic_id, *found_cpu;
1404
1405 apic_id.arch_id = id;
1406 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1407 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1408 pc_apic_cmp);
1409 if (found_cpu && idx) {
1410 *idx = found_cpu - ms->possible_cpus->cpus;
1411 }
1412 return found_cpu;
1413 }
1414
1415 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1416 DeviceState *dev, Error **errp)
1417 {
1418 CPUArchId *found_cpu;
1419 Error *local_err = NULL;
1420 X86CPU *cpu = X86_CPU(dev);
1421 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1422 X86MachineState *x86ms = X86_MACHINE(pcms);
1423
1424 if (pcms->acpi_dev) {
1425 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1426 if (local_err) {
1427 goto out;
1428 }
1429 }
1430
1431 /* increment the number of CPUs */
1432 x86ms->boot_cpus++;
1433 if (x86ms->rtc) {
1434 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1435 }
1436 if (x86ms->fw_cfg) {
1437 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1438 }
1439
1440 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1441 found_cpu->cpu = OBJECT(dev);
1442 out:
1443 error_propagate(errp, local_err);
1444 }
1445 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1446 DeviceState *dev, Error **errp)
1447 {
1448 int idx = -1;
1449 Error *local_err = NULL;
1450 X86CPU *cpu = X86_CPU(dev);
1451 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1452
1453 if (!pcms->acpi_dev) {
1454 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1455 goto out;
1456 }
1457
1458 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1459 assert(idx != -1);
1460 if (idx == 0) {
1461 error_setg(&local_err, "Boot CPU is unpluggable");
1462 goto out;
1463 }
1464
1465 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1466 &local_err);
1467 if (local_err) {
1468 goto out;
1469 }
1470
1471 out:
1472 error_propagate(errp, local_err);
1473
1474 }
1475
1476 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1477 DeviceState *dev, Error **errp)
1478 {
1479 CPUArchId *found_cpu;
1480 Error *local_err = NULL;
1481 X86CPU *cpu = X86_CPU(dev);
1482 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1483 X86MachineState *x86ms = X86_MACHINE(pcms);
1484
1485 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1486 if (local_err) {
1487 goto out;
1488 }
1489
1490 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1491 found_cpu->cpu = NULL;
1492 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1493
1494 /* decrement the number of CPUs */
1495 x86ms->boot_cpus--;
1496 /* Update the number of CPUs in CMOS */
1497 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1498 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1499 out:
1500 error_propagate(errp, local_err);
1501 }
1502
1503 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1504 DeviceState *dev, Error **errp)
1505 {
1506 int idx;
1507 CPUState *cs;
1508 CPUArchId *cpu_slot;
1509 X86CPUTopoInfo topo;
1510 X86CPU *cpu = X86_CPU(dev);
1511 CPUX86State *env = &cpu->env;
1512 MachineState *ms = MACHINE(hotplug_dev);
1513 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1514 X86MachineState *x86ms = X86_MACHINE(pcms);
1515 unsigned int smp_cores = ms->smp.cores;
1516 unsigned int smp_threads = ms->smp.threads;
1517
1518 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1519 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1520 ms->cpu_type);
1521 return;
1522 }
1523
1524 env->nr_dies = x86ms->smp_dies;
1525
1526 /*
1527 * If APIC ID is not set,
1528 * set it based on socket/die/core/thread properties.
1529 */
1530 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1531 int max_socket = (ms->smp.max_cpus - 1) /
1532 smp_threads / smp_cores / x86ms->smp_dies;
1533
1534 /*
1535 * die-id was optional in QEMU 4.0 and older, so keep it optional
1536 * if there's only one die per socket.
1537 */
1538 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1539 cpu->die_id = 0;
1540 }
1541
1542 if (cpu->socket_id < 0) {
1543 error_setg(errp, "CPU socket-id is not set");
1544 return;
1545 } else if (cpu->socket_id > max_socket) {
1546 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1547 cpu->socket_id, max_socket);
1548 return;
1549 }
1550 if (cpu->die_id < 0) {
1551 error_setg(errp, "CPU die-id is not set");
1552 return;
1553 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1554 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1555 cpu->die_id, x86ms->smp_dies - 1);
1556 return;
1557 }
1558 if (cpu->core_id < 0) {
1559 error_setg(errp, "CPU core-id is not set");
1560 return;
1561 } else if (cpu->core_id > (smp_cores - 1)) {
1562 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1563 cpu->core_id, smp_cores - 1);
1564 return;
1565 }
1566 if (cpu->thread_id < 0) {
1567 error_setg(errp, "CPU thread-id is not set");
1568 return;
1569 } else if (cpu->thread_id > (smp_threads - 1)) {
1570 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1571 cpu->thread_id, smp_threads - 1);
1572 return;
1573 }
1574
1575 topo.pkg_id = cpu->socket_id;
1576 topo.die_id = cpu->die_id;
1577 topo.core_id = cpu->core_id;
1578 topo.smt_id = cpu->thread_id;
1579 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1580 smp_threads, &topo);
1581 }
1582
1583 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1584 if (!cpu_slot) {
1585 MachineState *ms = MACHINE(pcms);
1586
1587 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1588 smp_cores, smp_threads, &topo);
1589 error_setg(errp,
1590 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1591 " APIC ID %" PRIu32 ", valid index range 0:%d",
1592 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1593 cpu->apic_id, ms->possible_cpus->len - 1);
1594 return;
1595 }
1596
1597 if (cpu_slot->cpu) {
1598 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1599 idx, cpu->apic_id);
1600 return;
1601 }
1602
1603 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1604 * so that machine_query_hotpluggable_cpus would show correct values
1605 */
1606 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1607 * once -smp refactoring is complete and there will be CPU private
1608 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1609 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1610 smp_cores, smp_threads, &topo);
1611 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1612 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1613 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1614 return;
1615 }
1616 cpu->socket_id = topo.pkg_id;
1617
1618 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1619 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1620 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1621 return;
1622 }
1623 cpu->die_id = topo.die_id;
1624
1625 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1626 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1627 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1628 return;
1629 }
1630 cpu->core_id = topo.core_id;
1631
1632 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1633 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1634 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1635 return;
1636 }
1637 cpu->thread_id = topo.smt_id;
1638
1639 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1640 !kvm_hv_vpindex_settable()) {
1641 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1642 return;
1643 }
1644
1645 cs = CPU(cpu);
1646 cs->cpu_index = idx;
1647
1648 numa_cpu_pre_plug(cpu_slot, dev, errp);
1649 }
1650
1651 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1652 DeviceState *dev, Error **errp)
1653 {
1654 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1655 Error *local_err = NULL;
1656
1657 if (!hotplug_dev2) {
1658 /*
1659 * Without a bus hotplug handler, we cannot control the plug/unplug
1660 * order. This should never be the case on x86, however better add
1661 * a safety net.
1662 */
1663 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1664 return;
1665 }
1666 /*
1667 * First, see if we can plug this memory device at all. If that
1668 * succeeds, branch of to the actual hotplug handler.
1669 */
1670 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1671 &local_err);
1672 if (!local_err) {
1673 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1674 }
1675 error_propagate(errp, local_err);
1676 }
1677
1678 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1679 DeviceState *dev, Error **errp)
1680 {
1681 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1682 Error *local_err = NULL;
1683
1684 /*
1685 * Plug the memory device first and then branch off to the actual
1686 * hotplug handler. If that one fails, we can easily undo the memory
1687 * device bits.
1688 */
1689 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1690 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1691 if (local_err) {
1692 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1693 }
1694 error_propagate(errp, local_err);
1695 }
1696
1697 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1698 DeviceState *dev, Error **errp)
1699 {
1700 /* We don't support virtio pmem hot unplug */
1701 error_setg(errp, "virtio pmem device unplug not supported.");
1702 }
1703
1704 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1705 DeviceState *dev, Error **errp)
1706 {
1707 /* We don't support virtio pmem hot unplug */
1708 }
1709
1710 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1711 DeviceState *dev, Error **errp)
1712 {
1713 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1714 pc_memory_pre_plug(hotplug_dev, dev, errp);
1715 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1716 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1717 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1718 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1719 }
1720 }
1721
1722 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1723 DeviceState *dev, Error **errp)
1724 {
1725 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1726 pc_memory_plug(hotplug_dev, dev, errp);
1727 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1728 pc_cpu_plug(hotplug_dev, dev, errp);
1729 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1730 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1731 }
1732 }
1733
1734 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1735 DeviceState *dev, Error **errp)
1736 {
1737 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1738 pc_memory_unplug_request(hotplug_dev, dev, errp);
1739 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1740 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1741 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1742 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1743 } else {
1744 error_setg(errp, "acpi: device unplug request for not supported device"
1745 " type: %s", object_get_typename(OBJECT(dev)));
1746 }
1747 }
1748
1749 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1750 DeviceState *dev, Error **errp)
1751 {
1752 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1753 pc_memory_unplug(hotplug_dev, dev, errp);
1754 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1755 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1756 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1757 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1758 } else {
1759 error_setg(errp, "acpi: device unplug for not supported device"
1760 " type: %s", object_get_typename(OBJECT(dev)));
1761 }
1762 }
1763
1764 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1765 DeviceState *dev)
1766 {
1767 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1768 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1769 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1770 return HOTPLUG_HANDLER(machine);
1771 }
1772
1773 return NULL;
1774 }
1775
1776 static void
1777 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1778 const char *name, void *opaque,
1779 Error **errp)
1780 {
1781 MachineState *ms = MACHINE(obj);
1782 int64_t value = 0;
1783
1784 if (ms->device_memory) {
1785 value = memory_region_size(&ms->device_memory->mr);
1786 }
1787
1788 visit_type_int(v, name, &value, errp);
1789 }
1790
1791 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1792 void *opaque, Error **errp)
1793 {
1794 PCMachineState *pcms = PC_MACHINE(obj);
1795 OnOffAuto vmport = pcms->vmport;
1796
1797 visit_type_OnOffAuto(v, name, &vmport, errp);
1798 }
1799
1800 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1801 void *opaque, Error **errp)
1802 {
1803 PCMachineState *pcms = PC_MACHINE(obj);
1804
1805 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1806 }
1807
1808 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1809 {
1810 PCMachineState *pcms = PC_MACHINE(obj);
1811
1812 return pcms->smbus_enabled;
1813 }
1814
1815 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1816 {
1817 PCMachineState *pcms = PC_MACHINE(obj);
1818
1819 pcms->smbus_enabled = value;
1820 }
1821
1822 static bool pc_machine_get_sata(Object *obj, Error **errp)
1823 {
1824 PCMachineState *pcms = PC_MACHINE(obj);
1825
1826 return pcms->sata_enabled;
1827 }
1828
1829 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1830 {
1831 PCMachineState *pcms = PC_MACHINE(obj);
1832
1833 pcms->sata_enabled = value;
1834 }
1835
1836 static bool pc_machine_get_pit(Object *obj, Error **errp)
1837 {
1838 PCMachineState *pcms = PC_MACHINE(obj);
1839
1840 return pcms->pit_enabled;
1841 }
1842
1843 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1844 {
1845 PCMachineState *pcms = PC_MACHINE(obj);
1846
1847 pcms->pit_enabled = value;
1848 }
1849
1850 static void pc_machine_initfn(Object *obj)
1851 {
1852 PCMachineState *pcms = PC_MACHINE(obj);
1853
1854 #ifdef CONFIG_VMPORT
1855 pcms->vmport = ON_OFF_AUTO_AUTO;
1856 #else
1857 pcms->vmport = ON_OFF_AUTO_OFF;
1858 #endif /* CONFIG_VMPORT */
1859 /* acpi build is enabled by default if machine supports it */
1860 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1861 pcms->smbus_enabled = true;
1862 pcms->sata_enabled = true;
1863 pcms->pit_enabled = true;
1864
1865 pc_system_flash_create(pcms);
1866 }
1867
1868 static void pc_machine_reset(MachineState *machine)
1869 {
1870 CPUState *cs;
1871 X86CPU *cpu;
1872
1873 qemu_devices_reset();
1874
1875 /* Reset APIC after devices have been reset to cancel
1876 * any changes that qemu_devices_reset() might have done.
1877 */
1878 CPU_FOREACH(cs) {
1879 cpu = X86_CPU(cs);
1880
1881 if (cpu->apic_state) {
1882 device_reset(cpu->apic_state);
1883 }
1884 }
1885 }
1886
1887 static void pc_machine_wakeup(MachineState *machine)
1888 {
1889 cpu_synchronize_all_states();
1890 pc_machine_reset(machine);
1891 cpu_synchronize_all_post_reset();
1892 }
1893
1894 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1895 {
1896 X86IOMMUState *iommu = x86_iommu_get_default();
1897 IntelIOMMUState *intel_iommu;
1898
1899 if (iommu &&
1900 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1901 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1902 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1903 if (!intel_iommu->caching_mode) {
1904 error_setg(errp, "Device assignment is not allowed without "
1905 "enabling caching-mode=on for Intel IOMMU.");
1906 return false;
1907 }
1908 }
1909
1910 return true;
1911 }
1912
1913 static void pc_machine_class_init(ObjectClass *oc, void *data)
1914 {
1915 MachineClass *mc = MACHINE_CLASS(oc);
1916 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1917 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1918
1919 pcmc->pci_enabled = true;
1920 pcmc->has_acpi_build = true;
1921 pcmc->rsdp_in_ram = true;
1922 pcmc->smbios_defaults = true;
1923 pcmc->smbios_uuid_encoded = true;
1924 pcmc->gigabyte_align = true;
1925 pcmc->has_reserved_memory = true;
1926 pcmc->kvmclock_enabled = true;
1927 pcmc->enforce_aligned_dimm = true;
1928 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1929 * to be used at the moment, 32K should be enough for a while. */
1930 pcmc->acpi_data_size = 0x20000 + 0x8000;
1931 pcmc->linuxboot_dma_enabled = true;
1932 pcmc->pvh_enabled = true;
1933 assert(!mc->get_hotplug_handler);
1934 mc->get_hotplug_handler = pc_get_hotplug_handler;
1935 mc->hotplug_allowed = pc_hotplug_allowed;
1936 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1937 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1938 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1939 mc->auto_enable_numa_with_memhp = true;
1940 mc->has_hotpluggable_cpus = true;
1941 mc->default_boot_order = "cad";
1942 mc->hot_add_cpu = pc_hot_add_cpu;
1943 mc->smp_parse = pc_smp_parse;
1944 mc->block_default_type = IF_IDE;
1945 mc->max_cpus = 255;
1946 mc->reset = pc_machine_reset;
1947 mc->wakeup = pc_machine_wakeup;
1948 hc->pre_plug = pc_machine_device_pre_plug_cb;
1949 hc->plug = pc_machine_device_plug_cb;
1950 hc->unplug_request = pc_machine_device_unplug_request_cb;
1951 hc->unplug = pc_machine_device_unplug_cb;
1952 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1953 mc->nvdimm_supported = true;
1954 mc->numa_mem_supported = true;
1955
1956 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1957 pc_machine_get_device_memory_region_size, NULL,
1958 NULL, NULL, &error_abort);
1959
1960 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1961 pc_machine_get_vmport, pc_machine_set_vmport,
1962 NULL, NULL, &error_abort);
1963 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1964 "Enable vmport (pc & q35)", &error_abort);
1965
1966 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1967 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
1968
1969 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1970 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
1971
1972 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1973 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
1974 }
1975
1976 static const TypeInfo pc_machine_info = {
1977 .name = TYPE_PC_MACHINE,
1978 .parent = TYPE_X86_MACHINE,
1979 .abstract = true,
1980 .instance_size = sizeof(PCMachineState),
1981 .instance_init = pc_machine_initfn,
1982 .class_size = sizeof(PCMachineClass),
1983 .class_init = pc_machine_class_init,
1984 .interfaces = (InterfaceInfo[]) {
1985 { TYPE_HOTPLUG_HANDLER },
1986 { }
1987 },
1988 };
1989
1990 static void pc_machine_register_types(void)
1991 {
1992 type_register_static(&pc_machine_info);
1993 }
1994
1995 type_init(pc_machine_register_types)
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