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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/dma/i8257.h"
48 #include "hw/timer/i8254.h"
49 #include "hw/input/i8042.h"
50 #include "hw/irq.h"
51 #include "hw/audio/pcspk.h"
52 #include "hw/pci/msi.h"
53 #include "hw/sysbus.h"
54 #include "sysemu/sysemu.h"
55 #include "sysemu/tcg.h"
56 #include "sysemu/numa.h"
57 #include "sysemu/kvm.h"
58 #include "sysemu/qtest.h"
59 #include "sysemu/reset.h"
60 #include "sysemu/runstate.h"
61 #include "kvm_i386.h"
62 #include "hw/xen/xen.h"
63 #include "hw/xen/start_info.h"
64 #include "ui/qemu-spice.h"
65 #include "exec/memory.h"
66 #include "exec/address-spaces.h"
67 #include "sysemu/arch_init.h"
68 #include "qemu/bitmap.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
71 #include "qemu/option.h"
72 #include "qemu/cutils.h"
73 #include "hw/acpi/acpi.h"
74 #include "hw/acpi/cpu_hotplug.h"
75 #include "hw/boards.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "qapi/error.h"
79 #include "qapi/qapi-visit-common.h"
80 #include "qapi/visitor.h"
81 #include "hw/core/cpu.h"
82 #include "hw/usb.h"
83 #include "hw/i386/intel_iommu.h"
84 #include "hw/net/ne2000-isa.h"
85 #include "standard-headers/asm-x86/bootparam.h"
86 #include "hw/virtio/virtio-pmem-pci.h"
87 #include "hw/mem/memory-device.h"
88 #include "sysemu/replay.h"
89 #include "qapi/qmp/qerror.h"
90 #include "config-devices.h"
91 #include "e820_memory_layout.h"
92 #include "fw_cfg.h"
93
94 /* debug PC/ISA interrupts */
95 //#define DEBUG_IRQ
96
97 #ifdef DEBUG_IRQ
98 #define DPRINTF(fmt, ...) \
99 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
100 #else
101 #define DPRINTF(fmt, ...)
102 #endif
103
104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
105
106 GlobalProperty pc_compat_4_1[] = {};
107 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
108
109 GlobalProperty pc_compat_4_0[] = {};
110 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
111
112 GlobalProperty pc_compat_3_1[] = {
113 { "intel-iommu", "dma-drain", "off" },
114 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
115 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
117 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
119 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
120 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
121 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
123 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
125 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
126 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
133 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
134 };
135 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
136
137 GlobalProperty pc_compat_3_0[] = {
138 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
139 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
140 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
141 };
142 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
143
144 GlobalProperty pc_compat_2_12[] = {
145 { TYPE_X86_CPU, "legacy-cache", "on" },
146 { TYPE_X86_CPU, "topoext", "off" },
147 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
148 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 };
150 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
151
152 GlobalProperty pc_compat_2_11[] = {
153 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
154 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
155 };
156 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
157
158 GlobalProperty pc_compat_2_10[] = {
159 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
160 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
161 { "q35-pcihost", "x-pci-hole64-fix", "off" },
162 };
163 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
164
165 GlobalProperty pc_compat_2_9[] = {
166 { "mch", "extended-tseg-mbytes", "0" },
167 };
168 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
169
170 GlobalProperty pc_compat_2_8[] = {
171 { TYPE_X86_CPU, "tcg-cpuid", "off" },
172 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
173 { "ICH9-LPC", "x-smi-broadcast", "off" },
174 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
175 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
176 };
177 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
178
179 GlobalProperty pc_compat_2_7[] = {
180 { TYPE_X86_CPU, "l3-cache", "off" },
181 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
182 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
185 { "isa-pcspk", "migrate", "off" },
186 };
187 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
188
189 GlobalProperty pc_compat_2_6[] = {
190 { TYPE_X86_CPU, "cpuid-0xb", "off" },
191 { "vmxnet3", "romfile", "" },
192 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
193 { "apic-common", "legacy-instance-id", "on", }
194 };
195 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
196
197 GlobalProperty pc_compat_2_5[] = {};
198 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
199
200 GlobalProperty pc_compat_2_4[] = {
201 PC_CPU_MODEL_IDS("2.4.0")
202 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
203 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
204 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
206 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
207 { TYPE_X86_CPU, "check", "off" },
208 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
209 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
211 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
213 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
216 };
217 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
218
219 GlobalProperty pc_compat_2_3[] = {
220 PC_CPU_MODEL_IDS("2.3.0")
221 { TYPE_X86_CPU, "arat", "off" },
222 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
223 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
224 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
225 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
226 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
227 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
241 };
242 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
243
244 GlobalProperty pc_compat_2_2[] = {
245 PC_CPU_MODEL_IDS("2.2.0")
246 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
247 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
252 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
262 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
264 };
265 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
266
267 GlobalProperty pc_compat_2_1[] = {
268 PC_CPU_MODEL_IDS("2.1.0")
269 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
270 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
271 };
272 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
273
274 GlobalProperty pc_compat_2_0[] = {
275 PC_CPU_MODEL_IDS("2.0.0")
276 { "virtio-scsi-pci", "any_layout", "off" },
277 { "PIIX4_PM", "memory-hotplug-support", "off" },
278 { "apic", "version", "0x11" },
279 { "nec-usb-xhci", "superspeed-ports-first", "off" },
280 { "nec-usb-xhci", "force-pcie-endcap", "on" },
281 { "pci-serial", "prog_if", "0" },
282 { "pci-serial-2x", "prog_if", "0" },
283 { "pci-serial-4x", "prog_if", "0" },
284 { "virtio-net-pci", "guest_announce", "off" },
285 { "ICH9-LPC", "memory-hotplug-support", "off" },
286 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
287 { "ioh3420", COMPAT_PROP_PCP, "off" },
288 };
289 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
290
291 GlobalProperty pc_compat_1_7[] = {
292 PC_CPU_MODEL_IDS("1.7.0")
293 { TYPE_USB_DEVICE, "msos-desc", "no" },
294 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
295 { "hpet", HPET_INTCAP, "4" },
296 };
297 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
298
299 GlobalProperty pc_compat_1_6[] = {
300 PC_CPU_MODEL_IDS("1.6.0")
301 { "e1000", "mitigation", "off" },
302 { "qemu64-" TYPE_X86_CPU, "model", "2" },
303 { "qemu32-" TYPE_X86_CPU, "model", "3" },
304 { "i440FX-pcihost", "short_root_bus", "1" },
305 { "q35-pcihost", "short_root_bus", "1" },
306 };
307 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
308
309 GlobalProperty pc_compat_1_5[] = {
310 PC_CPU_MODEL_IDS("1.5.0")
311 { "Conroe-" TYPE_X86_CPU, "model", "2" },
312 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
313 { "Penryn-" TYPE_X86_CPU, "model", "2" },
314 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
315 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
317 { "virtio-net-pci", "any_layout", "off" },
318 { TYPE_X86_CPU, "pmu", "on" },
319 { "i440FX-pcihost", "short_root_bus", "0" },
320 { "q35-pcihost", "short_root_bus", "0" },
321 };
322 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
323
324 GlobalProperty pc_compat_1_4[] = {
325 PC_CPU_MODEL_IDS("1.4.0")
326 { "scsi-hd", "discard_granularity", "0" },
327 { "scsi-cd", "discard_granularity", "0" },
328 { "scsi-disk", "discard_granularity", "0" },
329 { "ide-hd", "discard_granularity", "0" },
330 { "ide-cd", "discard_granularity", "0" },
331 { "ide-drive", "discard_granularity", "0" },
332 { "virtio-blk-pci", "discard_granularity", "0" },
333 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
334 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
335 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
336 { "e1000", "romfile", "pxe-e1000.rom" },
337 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
338 { "pcnet", "romfile", "pxe-pcnet.rom" },
339 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
340 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
341 { "486-" TYPE_X86_CPU, "model", "0" },
342 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
343 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
344 };
345 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
346
347 void gsi_handler(void *opaque, int n, int level)
348 {
349 GSIState *s = opaque;
350
351 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
352 if (n < ISA_NUM_IRQS) {
353 qemu_set_irq(s->i8259_irq[n], level);
354 }
355 qemu_set_irq(s->ioapic_irq[n], level);
356 }
357
358 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
359 {
360 GSIState *s;
361
362 s = g_new0(GSIState, 1);
363 if (kvm_ioapic_in_kernel()) {
364 kvm_pc_setup_irq_routing(pci_enabled);
365 *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
366 } else {
367 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
368 }
369
370 return s;
371 }
372
373 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
374 unsigned size)
375 {
376 }
377
378 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
379 {
380 return 0xffffffffffffffffULL;
381 }
382
383 /* MSDOS compatibility mode FPU exception support */
384 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
385 unsigned size)
386 {
387 if (tcg_enabled()) {
388 cpu_set_ignne();
389 }
390 }
391
392 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
393 {
394 return 0xffffffffffffffffULL;
395 }
396
397 /* TSC handling */
398 uint64_t cpu_get_tsc(CPUX86State *env)
399 {
400 return cpu_get_ticks();
401 }
402
403 /* IRQ handling */
404 int cpu_get_pic_interrupt(CPUX86State *env)
405 {
406 X86CPU *cpu = env_archcpu(env);
407 int intno;
408
409 if (!kvm_irqchip_in_kernel()) {
410 intno = apic_get_interrupt(cpu->apic_state);
411 if (intno >= 0) {
412 return intno;
413 }
414 /* read the irq from the PIC */
415 if (!apic_accept_pic_intr(cpu->apic_state)) {
416 return -1;
417 }
418 }
419
420 intno = pic_read_irq(isa_pic);
421 return intno;
422 }
423
424 static void pic_irq_request(void *opaque, int irq, int level)
425 {
426 CPUState *cs = first_cpu;
427 X86CPU *cpu = X86_CPU(cs);
428
429 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
430 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
431 CPU_FOREACH(cs) {
432 cpu = X86_CPU(cs);
433 if (apic_accept_pic_intr(cpu->apic_state)) {
434 apic_deliver_pic_intr(cpu->apic_state, level);
435 }
436 }
437 } else {
438 if (level) {
439 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
440 } else {
441 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
442 }
443 }
444 }
445
446 /* PC cmos mappings */
447
448 #define REG_EQUIPMENT_BYTE 0x14
449
450 int cmos_get_fd_drive_type(FloppyDriveType fd0)
451 {
452 int val;
453
454 switch (fd0) {
455 case FLOPPY_DRIVE_TYPE_144:
456 /* 1.44 Mb 3"5 drive */
457 val = 4;
458 break;
459 case FLOPPY_DRIVE_TYPE_288:
460 /* 2.88 Mb 3"5 drive */
461 val = 5;
462 break;
463 case FLOPPY_DRIVE_TYPE_120:
464 /* 1.2 Mb 5"5 drive */
465 val = 2;
466 break;
467 case FLOPPY_DRIVE_TYPE_NONE:
468 default:
469 val = 0;
470 break;
471 }
472 return val;
473 }
474
475 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
476 int16_t cylinders, int8_t heads, int8_t sectors)
477 {
478 rtc_set_memory(s, type_ofs, 47);
479 rtc_set_memory(s, info_ofs, cylinders);
480 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
481 rtc_set_memory(s, info_ofs + 2, heads);
482 rtc_set_memory(s, info_ofs + 3, 0xff);
483 rtc_set_memory(s, info_ofs + 4, 0xff);
484 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
485 rtc_set_memory(s, info_ofs + 6, cylinders);
486 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
487 rtc_set_memory(s, info_ofs + 8, sectors);
488 }
489
490 /* convert boot_device letter to something recognizable by the bios */
491 static int boot_device2nibble(char boot_device)
492 {
493 switch(boot_device) {
494 case 'a':
495 case 'b':
496 return 0x01; /* floppy boot */
497 case 'c':
498 return 0x02; /* hard drive boot */
499 case 'd':
500 return 0x03; /* CD-ROM boot */
501 case 'n':
502 return 0x04; /* Network boot */
503 }
504 return 0;
505 }
506
507 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
508 {
509 #define PC_MAX_BOOT_DEVICES 3
510 int nbds, bds[3] = { 0, };
511 int i;
512
513 nbds = strlen(boot_device);
514 if (nbds > PC_MAX_BOOT_DEVICES) {
515 error_setg(errp, "Too many boot devices for PC");
516 return;
517 }
518 for (i = 0; i < nbds; i++) {
519 bds[i] = boot_device2nibble(boot_device[i]);
520 if (bds[i] == 0) {
521 error_setg(errp, "Invalid boot device for PC: '%c'",
522 boot_device[i]);
523 return;
524 }
525 }
526 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
527 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
528 }
529
530 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
531 {
532 set_boot_dev(opaque, boot_device, errp);
533 }
534
535 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
536 {
537 int val, nb, i;
538 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
539 FLOPPY_DRIVE_TYPE_NONE };
540
541 /* floppy type */
542 if (floppy) {
543 for (i = 0; i < 2; i++) {
544 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
545 }
546 }
547 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
548 cmos_get_fd_drive_type(fd_type[1]);
549 rtc_set_memory(rtc_state, 0x10, val);
550
551 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
552 nb = 0;
553 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
554 nb++;
555 }
556 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
557 nb++;
558 }
559 switch (nb) {
560 case 0:
561 break;
562 case 1:
563 val |= 0x01; /* 1 drive, ready for boot */
564 break;
565 case 2:
566 val |= 0x41; /* 2 drives, ready for boot */
567 break;
568 }
569 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
570 }
571
572 typedef struct pc_cmos_init_late_arg {
573 ISADevice *rtc_state;
574 BusState *idebus[2];
575 } pc_cmos_init_late_arg;
576
577 typedef struct check_fdc_state {
578 ISADevice *floppy;
579 bool multiple;
580 } CheckFdcState;
581
582 static int check_fdc(Object *obj, void *opaque)
583 {
584 CheckFdcState *state = opaque;
585 Object *fdc;
586 uint32_t iobase;
587 Error *local_err = NULL;
588
589 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
590 if (!fdc) {
591 return 0;
592 }
593
594 iobase = object_property_get_uint(obj, "iobase", &local_err);
595 if (local_err || iobase != 0x3f0) {
596 error_free(local_err);
597 return 0;
598 }
599
600 if (state->floppy) {
601 state->multiple = true;
602 } else {
603 state->floppy = ISA_DEVICE(obj);
604 }
605 return 0;
606 }
607
608 static const char * const fdc_container_path[] = {
609 "/unattached", "/peripheral", "/peripheral-anon"
610 };
611
612 /*
613 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
614 * and ACPI objects.
615 */
616 ISADevice *pc_find_fdc0(void)
617 {
618 int i;
619 Object *container;
620 CheckFdcState state = { 0 };
621
622 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
623 container = container_get(qdev_get_machine(), fdc_container_path[i]);
624 object_child_foreach(container, check_fdc, &state);
625 }
626
627 if (state.multiple) {
628 warn_report("multiple floppy disk controllers with "
629 "iobase=0x3f0 have been found");
630 error_printf("the one being picked for CMOS setup might not reflect "
631 "your intent");
632 }
633
634 return state.floppy;
635 }
636
637 static void pc_cmos_init_late(void *opaque)
638 {
639 pc_cmos_init_late_arg *arg = opaque;
640 ISADevice *s = arg->rtc_state;
641 int16_t cylinders;
642 int8_t heads, sectors;
643 int val;
644 int i, trans;
645
646 val = 0;
647 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
648 &cylinders, &heads, &sectors) >= 0) {
649 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
650 val |= 0xf0;
651 }
652 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
653 &cylinders, &heads, &sectors) >= 0) {
654 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
655 val |= 0x0f;
656 }
657 rtc_set_memory(s, 0x12, val);
658
659 val = 0;
660 for (i = 0; i < 4; i++) {
661 /* NOTE: ide_get_geometry() returns the physical
662 geometry. It is always such that: 1 <= sects <= 63, 1
663 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
664 geometry can be different if a translation is done. */
665 if (arg->idebus[i / 2] &&
666 ide_get_geometry(arg->idebus[i / 2], i % 2,
667 &cylinders, &heads, &sectors) >= 0) {
668 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
669 assert((trans & ~3) == 0);
670 val |= trans << (i * 2);
671 }
672 }
673 rtc_set_memory(s, 0x39, val);
674
675 pc_cmos_init_floppy(s, pc_find_fdc0());
676
677 qemu_unregister_reset(pc_cmos_init_late, opaque);
678 }
679
680 void pc_cmos_init(PCMachineState *pcms,
681 BusState *idebus0, BusState *idebus1,
682 ISADevice *s)
683 {
684 int val;
685 static pc_cmos_init_late_arg arg;
686 X86MachineState *x86ms = X86_MACHINE(pcms);
687
688 /* various important CMOS locations needed by PC/Bochs bios */
689
690 /* memory size */
691 /* base memory (first MiB) */
692 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
693 rtc_set_memory(s, 0x15, val);
694 rtc_set_memory(s, 0x16, val >> 8);
695 /* extended memory (next 64MiB) */
696 if (x86ms->below_4g_mem_size > 1 * MiB) {
697 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
698 } else {
699 val = 0;
700 }
701 if (val > 65535)
702 val = 65535;
703 rtc_set_memory(s, 0x17, val);
704 rtc_set_memory(s, 0x18, val >> 8);
705 rtc_set_memory(s, 0x30, val);
706 rtc_set_memory(s, 0x31, val >> 8);
707 /* memory between 16MiB and 4GiB */
708 if (x86ms->below_4g_mem_size > 16 * MiB) {
709 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
710 } else {
711 val = 0;
712 }
713 if (val > 65535)
714 val = 65535;
715 rtc_set_memory(s, 0x34, val);
716 rtc_set_memory(s, 0x35, val >> 8);
717 /* memory above 4GiB */
718 val = x86ms->above_4g_mem_size / 65536;
719 rtc_set_memory(s, 0x5b, val);
720 rtc_set_memory(s, 0x5c, val >> 8);
721 rtc_set_memory(s, 0x5d, val >> 16);
722
723 object_property_add_link(OBJECT(pcms), "rtc_state",
724 TYPE_ISA_DEVICE,
725 (Object **)&x86ms->rtc,
726 object_property_allow_set_link,
727 OBJ_PROP_LINK_STRONG, &error_abort);
728 object_property_set_link(OBJECT(pcms), OBJECT(s),
729 "rtc_state", &error_abort);
730
731 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
732
733 val = 0;
734 val |= 0x02; /* FPU is there */
735 val |= 0x04; /* PS/2 mouse installed */
736 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
737
738 /* hard drives and FDC */
739 arg.rtc_state = s;
740 arg.idebus[0] = idebus0;
741 arg.idebus[1] = idebus1;
742 qemu_register_reset(pc_cmos_init_late, &arg);
743 }
744
745 #define TYPE_PORT92 "port92"
746 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
747
748 /* port 92 stuff: could be split off */
749 typedef struct Port92State {
750 ISADevice parent_obj;
751
752 MemoryRegion io;
753 uint8_t outport;
754 qemu_irq a20_out;
755 } Port92State;
756
757 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
758 unsigned size)
759 {
760 Port92State *s = opaque;
761 int oldval = s->outport;
762
763 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
764 s->outport = val;
765 qemu_set_irq(s->a20_out, (val >> 1) & 1);
766 if ((val & 1) && !(oldval & 1)) {
767 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
768 }
769 }
770
771 static uint64_t port92_read(void *opaque, hwaddr addr,
772 unsigned size)
773 {
774 Port92State *s = opaque;
775 uint32_t ret;
776
777 ret = s->outport;
778 DPRINTF("port92: read 0x%02x\n", ret);
779 return ret;
780 }
781
782 static void port92_init(ISADevice *dev, qemu_irq a20_out)
783 {
784 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
785 }
786
787 static const VMStateDescription vmstate_port92_isa = {
788 .name = "port92",
789 .version_id = 1,
790 .minimum_version_id = 1,
791 .fields = (VMStateField[]) {
792 VMSTATE_UINT8(outport, Port92State),
793 VMSTATE_END_OF_LIST()
794 }
795 };
796
797 static void port92_reset(DeviceState *d)
798 {
799 Port92State *s = PORT92(d);
800
801 s->outport &= ~1;
802 }
803
804 static const MemoryRegionOps port92_ops = {
805 .read = port92_read,
806 .write = port92_write,
807 .impl = {
808 .min_access_size = 1,
809 .max_access_size = 1,
810 },
811 .endianness = DEVICE_LITTLE_ENDIAN,
812 };
813
814 static void port92_initfn(Object *obj)
815 {
816 Port92State *s = PORT92(obj);
817
818 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
819
820 s->outport = 0;
821
822 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
823 }
824
825 static void port92_realizefn(DeviceState *dev, Error **errp)
826 {
827 ISADevice *isadev = ISA_DEVICE(dev);
828 Port92State *s = PORT92(dev);
829
830 isa_register_ioport(isadev, &s->io, 0x92);
831 }
832
833 static void port92_class_initfn(ObjectClass *klass, void *data)
834 {
835 DeviceClass *dc = DEVICE_CLASS(klass);
836
837 dc->realize = port92_realizefn;
838 dc->reset = port92_reset;
839 dc->vmsd = &vmstate_port92_isa;
840 /*
841 * Reason: unlike ordinary ISA devices, this one needs additional
842 * wiring: its A20 output line needs to be wired up by
843 * port92_init().
844 */
845 dc->user_creatable = false;
846 }
847
848 static const TypeInfo port92_info = {
849 .name = TYPE_PORT92,
850 .parent = TYPE_ISA_DEVICE,
851 .instance_size = sizeof(Port92State),
852 .instance_init = port92_initfn,
853 .class_init = port92_class_initfn,
854 };
855
856 static void port92_register_types(void)
857 {
858 type_register_static(&port92_info);
859 }
860
861 type_init(port92_register_types)
862
863 static void handle_a20_line_change(void *opaque, int irq, int level)
864 {
865 X86CPU *cpu = opaque;
866
867 /* XXX: send to all CPUs ? */
868 /* XXX: add logic to handle multiple A20 line sources */
869 x86_cpu_set_a20(cpu, level);
870 }
871
872 #define NE2000_NB_MAX 6
873
874 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
875 0x280, 0x380 };
876 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
877
878 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
879 {
880 static int nb_ne2k = 0;
881
882 if (nb_ne2k == NE2000_NB_MAX)
883 return;
884 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
885 ne2000_irq[nb_ne2k], nd);
886 nb_ne2k++;
887 }
888
889 DeviceState *cpu_get_current_apic(void)
890 {
891 if (current_cpu) {
892 X86CPU *cpu = X86_CPU(current_cpu);
893 return cpu->apic_state;
894 } else {
895 return NULL;
896 }
897 }
898
899 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
900 {
901 X86CPU *cpu = opaque;
902
903 if (level) {
904 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
905 }
906 }
907
908 /*
909 * This function is very similar to smp_parse()
910 * in hw/core/machine.c but includes CPU die support.
911 */
912 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
913 {
914 X86MachineState *x86ms = X86_MACHINE(ms);
915
916 if (opts) {
917 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
918 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
919 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
920 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
921 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
922
923 /* compute missing values, prefer sockets over cores over threads */
924 if (cpus == 0 || sockets == 0) {
925 cores = cores > 0 ? cores : 1;
926 threads = threads > 0 ? threads : 1;
927 if (cpus == 0) {
928 sockets = sockets > 0 ? sockets : 1;
929 cpus = cores * threads * dies * sockets;
930 } else {
931 ms->smp.max_cpus =
932 qemu_opt_get_number(opts, "maxcpus", cpus);
933 sockets = ms->smp.max_cpus / (cores * threads * dies);
934 }
935 } else if (cores == 0) {
936 threads = threads > 0 ? threads : 1;
937 cores = cpus / (sockets * dies * threads);
938 cores = cores > 0 ? cores : 1;
939 } else if (threads == 0) {
940 threads = cpus / (cores * dies * sockets);
941 threads = threads > 0 ? threads : 1;
942 } else if (sockets * dies * cores * threads < cpus) {
943 error_report("cpu topology: "
944 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
945 "smp_cpus (%u)",
946 sockets, dies, cores, threads, cpus);
947 exit(1);
948 }
949
950 ms->smp.max_cpus =
951 qemu_opt_get_number(opts, "maxcpus", cpus);
952
953 if (ms->smp.max_cpus < cpus) {
954 error_report("maxcpus must be equal to or greater than smp");
955 exit(1);
956 }
957
958 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
959 error_report("cpu topology: "
960 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
961 "maxcpus (%u)",
962 sockets, dies, cores, threads,
963 ms->smp.max_cpus);
964 exit(1);
965 }
966
967 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
968 warn_report("Invalid CPU topology deprecated: "
969 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
970 "!= maxcpus (%u)",
971 sockets, dies, cores, threads,
972 ms->smp.max_cpus);
973 }
974
975 ms->smp.cpus = cpus;
976 ms->smp.cores = cores;
977 ms->smp.threads = threads;
978 x86ms->smp_dies = dies;
979 }
980
981 if (ms->smp.cpus > 1) {
982 Error *blocker = NULL;
983 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
984 replay_add_blocker(blocker);
985 }
986 }
987
988 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
989 {
990 X86MachineState *x86ms = X86_MACHINE(ms);
991 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
992 Error *local_err = NULL;
993
994 if (id < 0) {
995 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
996 return;
997 }
998
999 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1000 error_setg(errp, "Unable to add CPU: %" PRIi64
1001 ", resulting APIC ID (%" PRIi64 ") is too large",
1002 id, apic_id);
1003 return;
1004 }
1005
1006
1007 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
1008 if (local_err) {
1009 error_propagate(errp, local_err);
1010 return;
1011 }
1012 }
1013
1014 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1015 {
1016 if (cpus_count > 0xff) {
1017 /* If the number of CPUs can't be represented in 8 bits, the
1018 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1019 * to make old BIOSes fail more predictably.
1020 */
1021 rtc_set_memory(rtc, 0x5f, 0);
1022 } else {
1023 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1024 }
1025 }
1026
1027 static
1028 void pc_machine_done(Notifier *notifier, void *data)
1029 {
1030 PCMachineState *pcms = container_of(notifier,
1031 PCMachineState, machine_done);
1032 X86MachineState *x86ms = X86_MACHINE(pcms);
1033 PCIBus *bus = pcms->bus;
1034
1035 /* set the number of CPUs */
1036 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1037
1038 if (bus) {
1039 int extra_hosts = 0;
1040
1041 QLIST_FOREACH(bus, &bus->child, sibling) {
1042 /* look for expander root buses */
1043 if (pci_bus_is_root(bus)) {
1044 extra_hosts++;
1045 }
1046 }
1047 if (extra_hosts && x86ms->fw_cfg) {
1048 uint64_t *val = g_malloc(sizeof(*val));
1049 *val = cpu_to_le64(extra_hosts);
1050 fw_cfg_add_file(x86ms->fw_cfg,
1051 "etc/extra-pci-roots", val, sizeof(*val));
1052 }
1053 }
1054
1055 acpi_setup();
1056 if (x86ms->fw_cfg) {
1057 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
1058 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
1059 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1060 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1061 }
1062
1063 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
1064 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1065
1066 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1067 iommu->intr_eim != ON_OFF_AUTO_ON) {
1068 error_report("current -smp configuration requires "
1069 "Extended Interrupt Mode enabled. "
1070 "You can add an IOMMU using: "
1071 "-device intel-iommu,intremap=on,eim=on");
1072 exit(EXIT_FAILURE);
1073 }
1074 }
1075 }
1076
1077 void pc_guest_info_init(PCMachineState *pcms)
1078 {
1079 int i;
1080 MachineState *ms = MACHINE(pcms);
1081 X86MachineState *x86ms = X86_MACHINE(pcms);
1082
1083 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
1084 pcms->numa_nodes = ms->numa_state->num_nodes;
1085 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1086 sizeof *pcms->node_mem);
1087 for (i = 0; i < ms->numa_state->num_nodes; i++) {
1088 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
1089 }
1090
1091 pcms->machine_done.notify = pc_machine_done;
1092 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1093 }
1094
1095 /* setup pci memory address space mapping into system address space */
1096 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1097 MemoryRegion *pci_address_space)
1098 {
1099 /* Set to lower priority than RAM */
1100 memory_region_add_subregion_overlap(system_memory, 0x0,
1101 pci_address_space, -1);
1102 }
1103
1104 void xen_load_linux(PCMachineState *pcms)
1105 {
1106 int i;
1107 FWCfgState *fw_cfg;
1108 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1109 X86MachineState *x86ms = X86_MACHINE(pcms);
1110
1111 assert(MACHINE(pcms)->kernel_filename != NULL);
1112
1113 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1114 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1115 rom_set_fw(fw_cfg);
1116
1117 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1118 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1119 for (i = 0; i < nb_option_roms; i++) {
1120 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1121 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1122 !strcmp(option_rom[i].name, "pvh.bin") ||
1123 !strcmp(option_rom[i].name, "multiboot.bin"));
1124 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1125 }
1126 x86ms->fw_cfg = fw_cfg;
1127 }
1128
1129 void pc_memory_init(PCMachineState *pcms,
1130 MemoryRegion *system_memory,
1131 MemoryRegion *rom_memory,
1132 MemoryRegion **ram_memory)
1133 {
1134 int linux_boot, i;
1135 MemoryRegion *ram, *option_rom_mr;
1136 MemoryRegion *ram_below_4g, *ram_above_4g;
1137 FWCfgState *fw_cfg;
1138 MachineState *machine = MACHINE(pcms);
1139 MachineClass *mc = MACHINE_GET_CLASS(machine);
1140 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1141 X86MachineState *x86ms = X86_MACHINE(pcms);
1142
1143 assert(machine->ram_size == x86ms->below_4g_mem_size +
1144 x86ms->above_4g_mem_size);
1145
1146 linux_boot = (machine->kernel_filename != NULL);
1147
1148 /* Allocate RAM. We allocate it as a single memory region and use
1149 * aliases to address portions of it, mostly for backwards compatibility
1150 * with older qemus that used qemu_ram_alloc().
1151 */
1152 ram = g_malloc(sizeof(*ram));
1153 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1154 machine->ram_size);
1155 *ram_memory = ram;
1156 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1157 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1158 0, x86ms->below_4g_mem_size);
1159 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1160 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1161 if (x86ms->above_4g_mem_size > 0) {
1162 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1163 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1164 x86ms->below_4g_mem_size,
1165 x86ms->above_4g_mem_size);
1166 memory_region_add_subregion(system_memory, 0x100000000ULL,
1167 ram_above_4g);
1168 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
1169 }
1170
1171 if (!pcmc->has_reserved_memory &&
1172 (machine->ram_slots ||
1173 (machine->maxram_size > machine->ram_size))) {
1174
1175 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1176 mc->name);
1177 exit(EXIT_FAILURE);
1178 }
1179
1180 /* always allocate the device memory information */
1181 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1182
1183 /* initialize device memory address space */
1184 if (pcmc->has_reserved_memory &&
1185 (machine->ram_size < machine->maxram_size)) {
1186 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1187
1188 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1189 error_report("unsupported amount of memory slots: %"PRIu64,
1190 machine->ram_slots);
1191 exit(EXIT_FAILURE);
1192 }
1193
1194 if (QEMU_ALIGN_UP(machine->maxram_size,
1195 TARGET_PAGE_SIZE) != machine->maxram_size) {
1196 error_report("maximum memory size must by aligned to multiple of "
1197 "%d bytes", TARGET_PAGE_SIZE);
1198 exit(EXIT_FAILURE);
1199 }
1200
1201 machine->device_memory->base =
1202 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1203
1204 if (pcmc->enforce_aligned_dimm) {
1205 /* size device region assuming 1G page max alignment per slot */
1206 device_mem_size += (1 * GiB) * machine->ram_slots;
1207 }
1208
1209 if ((machine->device_memory->base + device_mem_size) <
1210 device_mem_size) {
1211 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1212 machine->maxram_size);
1213 exit(EXIT_FAILURE);
1214 }
1215
1216 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1217 "device-memory", device_mem_size);
1218 memory_region_add_subregion(system_memory, machine->device_memory->base,
1219 &machine->device_memory->mr);
1220 }
1221
1222 /* Initialize PC system firmware */
1223 pc_system_firmware_init(pcms, rom_memory);
1224
1225 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1226 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1227 &error_fatal);
1228 if (pcmc->pci_enabled) {
1229 memory_region_set_readonly(option_rom_mr, true);
1230 }
1231 memory_region_add_subregion_overlap(rom_memory,
1232 PC_ROM_MIN_VGA,
1233 option_rom_mr,
1234 1);
1235
1236 fw_cfg = fw_cfg_arch_create(machine,
1237 x86ms->boot_cpus, x86ms->apic_id_limit);
1238
1239 rom_set_fw(fw_cfg);
1240
1241 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1242 uint64_t *val = g_malloc(sizeof(*val));
1243 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1244 uint64_t res_mem_end = machine->device_memory->base;
1245
1246 if (!pcmc->broken_reserved_end) {
1247 res_mem_end += memory_region_size(&machine->device_memory->mr);
1248 }
1249 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1250 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1251 }
1252
1253 if (linux_boot) {
1254 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1255 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1256 }
1257
1258 for (i = 0; i < nb_option_roms; i++) {
1259 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1260 }
1261 x86ms->fw_cfg = fw_cfg;
1262
1263 /* Init default IOAPIC address space */
1264 x86ms->ioapic_as = &address_space_memory;
1265
1266 /* Init ACPI memory hotplug IO base address */
1267 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1268 }
1269
1270 /*
1271 * The 64bit pci hole starts after "above 4G RAM" and
1272 * potentially the space reserved for memory hotplug.
1273 */
1274 uint64_t pc_pci_hole64_start(void)
1275 {
1276 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1277 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1278 MachineState *ms = MACHINE(pcms);
1279 X86MachineState *x86ms = X86_MACHINE(pcms);
1280 uint64_t hole64_start = 0;
1281
1282 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1283 hole64_start = ms->device_memory->base;
1284 if (!pcmc->broken_reserved_end) {
1285 hole64_start += memory_region_size(&ms->device_memory->mr);
1286 }
1287 } else {
1288 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1289 }
1290
1291 return ROUND_UP(hole64_start, 1 * GiB);
1292 }
1293
1294 qemu_irq pc_allocate_cpu_irq(void)
1295 {
1296 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1297 }
1298
1299 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1300 {
1301 DeviceState *dev = NULL;
1302
1303 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1304 if (pci_bus) {
1305 PCIDevice *pcidev = pci_vga_init(pci_bus);
1306 dev = pcidev ? &pcidev->qdev : NULL;
1307 } else if (isa_bus) {
1308 ISADevice *isadev = isa_vga_init(isa_bus);
1309 dev = isadev ? DEVICE(isadev) : NULL;
1310 }
1311 rom_reset_order_override();
1312 return dev;
1313 }
1314
1315 static const MemoryRegionOps ioport80_io_ops = {
1316 .write = ioport80_write,
1317 .read = ioport80_read,
1318 .endianness = DEVICE_NATIVE_ENDIAN,
1319 .impl = {
1320 .min_access_size = 1,
1321 .max_access_size = 1,
1322 },
1323 };
1324
1325 static const MemoryRegionOps ioportF0_io_ops = {
1326 .write = ioportF0_write,
1327 .read = ioportF0_read,
1328 .endianness = DEVICE_NATIVE_ENDIAN,
1329 .impl = {
1330 .min_access_size = 1,
1331 .max_access_size = 1,
1332 },
1333 };
1334
1335 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1336 {
1337 int i;
1338 DriveInfo *fd[MAX_FD];
1339 qemu_irq *a20_line;
1340 ISADevice *i8042, *port92, *vmmouse;
1341
1342 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1343 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1344
1345 for (i = 0; i < MAX_FD; i++) {
1346 fd[i] = drive_get(IF_FLOPPY, 0, i);
1347 create_fdctrl |= !!fd[i];
1348 }
1349 if (create_fdctrl) {
1350 fdctrl_init_isa(isa_bus, fd);
1351 }
1352
1353 i8042 = isa_create_simple(isa_bus, "i8042");
1354 if (!no_vmport) {
1355 vmport_init(isa_bus);
1356 vmmouse = isa_try_create(isa_bus, "vmmouse");
1357 } else {
1358 vmmouse = NULL;
1359 }
1360 if (vmmouse) {
1361 DeviceState *dev = DEVICE(vmmouse);
1362 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1363 qdev_init_nofail(dev);
1364 }
1365 port92 = isa_create_simple(isa_bus, "port92");
1366
1367 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1368 i8042_setup_a20_line(i8042, a20_line[0]);
1369 port92_init(port92, a20_line[1]);
1370 g_free(a20_line);
1371 }
1372
1373 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1374 ISADevice **rtc_state,
1375 bool create_fdctrl,
1376 bool no_vmport,
1377 bool has_pit,
1378 uint32_t hpet_irqs)
1379 {
1380 int i;
1381 DeviceState *hpet = NULL;
1382 int pit_isa_irq = 0;
1383 qemu_irq pit_alt_irq = NULL;
1384 qemu_irq rtc_irq = NULL;
1385 ISADevice *pit = NULL;
1386 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1387 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1388
1389 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1390 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1391
1392 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1393 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1394
1395 /*
1396 * Check if an HPET shall be created.
1397 *
1398 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1399 * when the HPET wants to take over. Thus we have to disable the latter.
1400 */
1401 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1402 /* In order to set property, here not using sysbus_try_create_simple */
1403 hpet = qdev_try_create(NULL, TYPE_HPET);
1404 if (hpet) {
1405 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1406 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1407 * IRQ8 and IRQ2.
1408 */
1409 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1410 HPET_INTCAP, NULL);
1411 if (!compat) {
1412 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1413 }
1414 qdev_init_nofail(hpet);
1415 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1416
1417 for (i = 0; i < GSI_NUM_PINS; i++) {
1418 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1419 }
1420 pit_isa_irq = -1;
1421 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1422 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1423 }
1424 }
1425 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1426
1427 qemu_register_boot_set(pc_boot_set, *rtc_state);
1428
1429 if (!xen_enabled() && has_pit) {
1430 if (kvm_pit_in_kernel()) {
1431 pit = kvm_pit_init(isa_bus, 0x40);
1432 } else {
1433 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1434 }
1435 if (hpet) {
1436 /* connect PIT to output control line of the HPET */
1437 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1438 }
1439 pcspk_init(isa_bus, pit);
1440 }
1441
1442 i8257_dma_init(isa_bus, 0);
1443
1444 /* Super I/O */
1445 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1446 }
1447
1448 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1449 {
1450 int i;
1451
1452 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1453 for (i = 0; i < nb_nics; i++) {
1454 NICInfo *nd = &nd_table[i];
1455 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1456
1457 if (g_str_equal(model, "ne2k_isa")) {
1458 pc_init_ne2k_isa(isa_bus, nd);
1459 } else {
1460 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1461 }
1462 }
1463 rom_reset_order_override();
1464 }
1465
1466 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1467 {
1468 qemu_irq *i8259;
1469
1470 if (kvm_pic_in_kernel()) {
1471 i8259 = kvm_i8259_init(isa_bus);
1472 } else if (xen_enabled()) {
1473 i8259 = xen_interrupt_controller_init();
1474 } else {
1475 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
1476 }
1477
1478 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1479 i8259_irqs[i] = i8259[i];
1480 }
1481
1482 g_free(i8259);
1483 }
1484
1485 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1486 {
1487 DeviceState *dev;
1488 SysBusDevice *d;
1489 unsigned int i;
1490
1491 if (kvm_ioapic_in_kernel()) {
1492 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
1493 } else {
1494 dev = qdev_create(NULL, TYPE_IOAPIC);
1495 }
1496 if (parent_name) {
1497 object_property_add_child(object_resolve_path(parent_name, NULL),
1498 "ioapic", OBJECT(dev), NULL);
1499 }
1500 qdev_init_nofail(dev);
1501 d = SYS_BUS_DEVICE(dev);
1502 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1503
1504 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1505 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1506 }
1507 }
1508
1509 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1510 Error **errp)
1511 {
1512 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1513 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1514 const MachineState *ms = MACHINE(hotplug_dev);
1515 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1516 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1517 Error *local_err = NULL;
1518
1519 /*
1520 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1521 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1522 * addition to cover this case.
1523 */
1524 if (!pcms->acpi_dev || !acpi_enabled) {
1525 error_setg(errp,
1526 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1527 return;
1528 }
1529
1530 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1531 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1532 return;
1533 }
1534
1535 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1536 if (local_err) {
1537 error_propagate(errp, local_err);
1538 return;
1539 }
1540
1541 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1542 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1543 }
1544
1545 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1546 DeviceState *dev, Error **errp)
1547 {
1548 Error *local_err = NULL;
1549 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1550 MachineState *ms = MACHINE(hotplug_dev);
1551 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1552
1553 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1554 if (local_err) {
1555 goto out;
1556 }
1557
1558 if (is_nvdimm) {
1559 nvdimm_plug(ms->nvdimms_state);
1560 }
1561
1562 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1563 out:
1564 error_propagate(errp, local_err);
1565 }
1566
1567 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1568 DeviceState *dev, Error **errp)
1569 {
1570 Error *local_err = NULL;
1571 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1572
1573 /*
1574 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1575 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1576 * addition to cover this case.
1577 */
1578 if (!pcms->acpi_dev || !acpi_enabled) {
1579 error_setg(&local_err,
1580 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1581 goto out;
1582 }
1583
1584 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1585 error_setg(&local_err,
1586 "nvdimm device hot unplug is not supported yet.");
1587 goto out;
1588 }
1589
1590 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1591 &local_err);
1592 out:
1593 error_propagate(errp, local_err);
1594 }
1595
1596 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1597 DeviceState *dev, Error **errp)
1598 {
1599 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1600 Error *local_err = NULL;
1601
1602 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1603 if (local_err) {
1604 goto out;
1605 }
1606
1607 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1608 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1609 out:
1610 error_propagate(errp, local_err);
1611 }
1612
1613 static int pc_apic_cmp(const void *a, const void *b)
1614 {
1615 CPUArchId *apic_a = (CPUArchId *)a;
1616 CPUArchId *apic_b = (CPUArchId *)b;
1617
1618 return apic_a->arch_id - apic_b->arch_id;
1619 }
1620
1621 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1622 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1623 * entry corresponding to CPU's apic_id returns NULL.
1624 */
1625 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1626 {
1627 CPUArchId apic_id, *found_cpu;
1628
1629 apic_id.arch_id = id;
1630 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1631 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1632 pc_apic_cmp);
1633 if (found_cpu && idx) {
1634 *idx = found_cpu - ms->possible_cpus->cpus;
1635 }
1636 return found_cpu;
1637 }
1638
1639 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1640 DeviceState *dev, Error **errp)
1641 {
1642 CPUArchId *found_cpu;
1643 Error *local_err = NULL;
1644 X86CPU *cpu = X86_CPU(dev);
1645 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1646 X86MachineState *x86ms = X86_MACHINE(pcms);
1647
1648 if (pcms->acpi_dev) {
1649 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1650 if (local_err) {
1651 goto out;
1652 }
1653 }
1654
1655 /* increment the number of CPUs */
1656 x86ms->boot_cpus++;
1657 if (x86ms->rtc) {
1658 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1659 }
1660 if (x86ms->fw_cfg) {
1661 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1662 }
1663
1664 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1665 found_cpu->cpu = OBJECT(dev);
1666 out:
1667 error_propagate(errp, local_err);
1668 }
1669 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1670 DeviceState *dev, Error **errp)
1671 {
1672 int idx = -1;
1673 Error *local_err = NULL;
1674 X86CPU *cpu = X86_CPU(dev);
1675 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1676
1677 if (!pcms->acpi_dev) {
1678 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1679 goto out;
1680 }
1681
1682 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1683 assert(idx != -1);
1684 if (idx == 0) {
1685 error_setg(&local_err, "Boot CPU is unpluggable");
1686 goto out;
1687 }
1688
1689 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1690 &local_err);
1691 if (local_err) {
1692 goto out;
1693 }
1694
1695 out:
1696 error_propagate(errp, local_err);
1697
1698 }
1699
1700 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1701 DeviceState *dev, Error **errp)
1702 {
1703 CPUArchId *found_cpu;
1704 Error *local_err = NULL;
1705 X86CPU *cpu = X86_CPU(dev);
1706 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1707 X86MachineState *x86ms = X86_MACHINE(pcms);
1708
1709 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1710 if (local_err) {
1711 goto out;
1712 }
1713
1714 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1715 found_cpu->cpu = NULL;
1716 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1717
1718 /* decrement the number of CPUs */
1719 x86ms->boot_cpus--;
1720 /* Update the number of CPUs in CMOS */
1721 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1722 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1723 out:
1724 error_propagate(errp, local_err);
1725 }
1726
1727 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1728 DeviceState *dev, Error **errp)
1729 {
1730 int idx;
1731 CPUState *cs;
1732 CPUArchId *cpu_slot;
1733 X86CPUTopoInfo topo;
1734 X86CPU *cpu = X86_CPU(dev);
1735 CPUX86State *env = &cpu->env;
1736 MachineState *ms = MACHINE(hotplug_dev);
1737 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1738 X86MachineState *x86ms = X86_MACHINE(pcms);
1739 unsigned int smp_cores = ms->smp.cores;
1740 unsigned int smp_threads = ms->smp.threads;
1741
1742 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1743 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1744 ms->cpu_type);
1745 return;
1746 }
1747
1748 env->nr_dies = x86ms->smp_dies;
1749
1750 /*
1751 * If APIC ID is not set,
1752 * set it based on socket/die/core/thread properties.
1753 */
1754 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1755 int max_socket = (ms->smp.max_cpus - 1) /
1756 smp_threads / smp_cores / x86ms->smp_dies;
1757
1758 /*
1759 * die-id was optional in QEMU 4.0 and older, so keep it optional
1760 * if there's only one die per socket.
1761 */
1762 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1763 cpu->die_id = 0;
1764 }
1765
1766 if (cpu->socket_id < 0) {
1767 error_setg(errp, "CPU socket-id is not set");
1768 return;
1769 } else if (cpu->socket_id > max_socket) {
1770 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1771 cpu->socket_id, max_socket);
1772 return;
1773 }
1774 if (cpu->die_id < 0) {
1775 error_setg(errp, "CPU die-id is not set");
1776 return;
1777 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1778 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1779 cpu->die_id, x86ms->smp_dies - 1);
1780 return;
1781 }
1782 if (cpu->core_id < 0) {
1783 error_setg(errp, "CPU core-id is not set");
1784 return;
1785 } else if (cpu->core_id > (smp_cores - 1)) {
1786 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1787 cpu->core_id, smp_cores - 1);
1788 return;
1789 }
1790 if (cpu->thread_id < 0) {
1791 error_setg(errp, "CPU thread-id is not set");
1792 return;
1793 } else if (cpu->thread_id > (smp_threads - 1)) {
1794 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1795 cpu->thread_id, smp_threads - 1);
1796 return;
1797 }
1798
1799 topo.pkg_id = cpu->socket_id;
1800 topo.die_id = cpu->die_id;
1801 topo.core_id = cpu->core_id;
1802 topo.smt_id = cpu->thread_id;
1803 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1804 smp_threads, &topo);
1805 }
1806
1807 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1808 if (!cpu_slot) {
1809 MachineState *ms = MACHINE(pcms);
1810
1811 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1812 smp_cores, smp_threads, &topo);
1813 error_setg(errp,
1814 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1815 " APIC ID %" PRIu32 ", valid index range 0:%d",
1816 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1817 cpu->apic_id, ms->possible_cpus->len - 1);
1818 return;
1819 }
1820
1821 if (cpu_slot->cpu) {
1822 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1823 idx, cpu->apic_id);
1824 return;
1825 }
1826
1827 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1828 * so that machine_query_hotpluggable_cpus would show correct values
1829 */
1830 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1831 * once -smp refactoring is complete and there will be CPU private
1832 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1833 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1834 smp_cores, smp_threads, &topo);
1835 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1836 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1837 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1838 return;
1839 }
1840 cpu->socket_id = topo.pkg_id;
1841
1842 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1843 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1844 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1845 return;
1846 }
1847 cpu->die_id = topo.die_id;
1848
1849 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1850 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1851 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1852 return;
1853 }
1854 cpu->core_id = topo.core_id;
1855
1856 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1857 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1858 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1859 return;
1860 }
1861 cpu->thread_id = topo.smt_id;
1862
1863 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1864 !kvm_hv_vpindex_settable()) {
1865 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1866 return;
1867 }
1868
1869 cs = CPU(cpu);
1870 cs->cpu_index = idx;
1871
1872 numa_cpu_pre_plug(cpu_slot, dev, errp);
1873 }
1874
1875 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1876 DeviceState *dev, Error **errp)
1877 {
1878 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1879 Error *local_err = NULL;
1880
1881 if (!hotplug_dev2) {
1882 /*
1883 * Without a bus hotplug handler, we cannot control the plug/unplug
1884 * order. This should never be the case on x86, however better add
1885 * a safety net.
1886 */
1887 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1888 return;
1889 }
1890 /*
1891 * First, see if we can plug this memory device at all. If that
1892 * succeeds, branch of to the actual hotplug handler.
1893 */
1894 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1895 &local_err);
1896 if (!local_err) {
1897 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1898 }
1899 error_propagate(errp, local_err);
1900 }
1901
1902 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1903 DeviceState *dev, Error **errp)
1904 {
1905 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1906 Error *local_err = NULL;
1907
1908 /*
1909 * Plug the memory device first and then branch off to the actual
1910 * hotplug handler. If that one fails, we can easily undo the memory
1911 * device bits.
1912 */
1913 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1914 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1915 if (local_err) {
1916 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1917 }
1918 error_propagate(errp, local_err);
1919 }
1920
1921 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1922 DeviceState *dev, Error **errp)
1923 {
1924 /* We don't support virtio pmem hot unplug */
1925 error_setg(errp, "virtio pmem device unplug not supported.");
1926 }
1927
1928 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1929 DeviceState *dev, Error **errp)
1930 {
1931 /* We don't support virtio pmem hot unplug */
1932 }
1933
1934 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1935 DeviceState *dev, Error **errp)
1936 {
1937 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1938 pc_memory_pre_plug(hotplug_dev, dev, errp);
1939 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1940 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1941 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1942 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1943 }
1944 }
1945
1946 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1947 DeviceState *dev, Error **errp)
1948 {
1949 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1950 pc_memory_plug(hotplug_dev, dev, errp);
1951 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1952 pc_cpu_plug(hotplug_dev, dev, errp);
1953 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1954 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1955 }
1956 }
1957
1958 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1959 DeviceState *dev, Error **errp)
1960 {
1961 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1962 pc_memory_unplug_request(hotplug_dev, dev, errp);
1963 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1964 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1965 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1966 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1967 } else {
1968 error_setg(errp, "acpi: device unplug request for not supported device"
1969 " type: %s", object_get_typename(OBJECT(dev)));
1970 }
1971 }
1972
1973 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1974 DeviceState *dev, Error **errp)
1975 {
1976 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1977 pc_memory_unplug(hotplug_dev, dev, errp);
1978 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1979 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1980 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1981 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1982 } else {
1983 error_setg(errp, "acpi: device unplug for not supported device"
1984 " type: %s", object_get_typename(OBJECT(dev)));
1985 }
1986 }
1987
1988 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1989 DeviceState *dev)
1990 {
1991 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1992 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1993 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1994 return HOTPLUG_HANDLER(machine);
1995 }
1996
1997 return NULL;
1998 }
1999
2000 static void
2001 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2002 const char *name, void *opaque,
2003 Error **errp)
2004 {
2005 MachineState *ms = MACHINE(obj);
2006 int64_t value = 0;
2007
2008 if (ms->device_memory) {
2009 value = memory_region_size(&ms->device_memory->mr);
2010 }
2011
2012 visit_type_int(v, name, &value, errp);
2013 }
2014
2015 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2016 void *opaque, Error **errp)
2017 {
2018 PCMachineState *pcms = PC_MACHINE(obj);
2019 OnOffAuto vmport = pcms->vmport;
2020
2021 visit_type_OnOffAuto(v, name, &vmport, errp);
2022 }
2023
2024 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2025 void *opaque, Error **errp)
2026 {
2027 PCMachineState *pcms = PC_MACHINE(obj);
2028
2029 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2030 }
2031
2032 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2033 {
2034 bool smm_available = false;
2035
2036 if (pcms->smm == ON_OFF_AUTO_OFF) {
2037 return false;
2038 }
2039
2040 if (tcg_enabled() || qtest_enabled()) {
2041 smm_available = true;
2042 } else if (kvm_enabled()) {
2043 smm_available = kvm_has_smm();
2044 }
2045
2046 if (smm_available) {
2047 return true;
2048 }
2049
2050 if (pcms->smm == ON_OFF_AUTO_ON) {
2051 error_report("System Management Mode not supported by this hypervisor.");
2052 exit(1);
2053 }
2054 return false;
2055 }
2056
2057 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2058 void *opaque, Error **errp)
2059 {
2060 PCMachineState *pcms = PC_MACHINE(obj);
2061 OnOffAuto smm = pcms->smm;
2062
2063 visit_type_OnOffAuto(v, name, &smm, errp);
2064 }
2065
2066 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2067 void *opaque, Error **errp)
2068 {
2069 PCMachineState *pcms = PC_MACHINE(obj);
2070
2071 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2072 }
2073
2074 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2075 {
2076 PCMachineState *pcms = PC_MACHINE(obj);
2077
2078 return pcms->smbus_enabled;
2079 }
2080
2081 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2082 {
2083 PCMachineState *pcms = PC_MACHINE(obj);
2084
2085 pcms->smbus_enabled = value;
2086 }
2087
2088 static bool pc_machine_get_sata(Object *obj, Error **errp)
2089 {
2090 PCMachineState *pcms = PC_MACHINE(obj);
2091
2092 return pcms->sata_enabled;
2093 }
2094
2095 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2096 {
2097 PCMachineState *pcms = PC_MACHINE(obj);
2098
2099 pcms->sata_enabled = value;
2100 }
2101
2102 static bool pc_machine_get_pit(Object *obj, Error **errp)
2103 {
2104 PCMachineState *pcms = PC_MACHINE(obj);
2105
2106 return pcms->pit_enabled;
2107 }
2108
2109 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2110 {
2111 PCMachineState *pcms = PC_MACHINE(obj);
2112
2113 pcms->pit_enabled = value;
2114 }
2115
2116 static void pc_machine_initfn(Object *obj)
2117 {
2118 PCMachineState *pcms = PC_MACHINE(obj);
2119
2120 pcms->smm = ON_OFF_AUTO_AUTO;
2121 #ifdef CONFIG_VMPORT
2122 pcms->vmport = ON_OFF_AUTO_AUTO;
2123 #else
2124 pcms->vmport = ON_OFF_AUTO_OFF;
2125 #endif /* CONFIG_VMPORT */
2126 /* acpi build is enabled by default if machine supports it */
2127 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2128 pcms->smbus_enabled = true;
2129 pcms->sata_enabled = true;
2130 pcms->pit_enabled = true;
2131
2132 pc_system_flash_create(pcms);
2133 }
2134
2135 static void pc_machine_reset(MachineState *machine)
2136 {
2137 CPUState *cs;
2138 X86CPU *cpu;
2139
2140 qemu_devices_reset();
2141
2142 /* Reset APIC after devices have been reset to cancel
2143 * any changes that qemu_devices_reset() might have done.
2144 */
2145 CPU_FOREACH(cs) {
2146 cpu = X86_CPU(cs);
2147
2148 if (cpu->apic_state) {
2149 device_reset(cpu->apic_state);
2150 }
2151 }
2152 }
2153
2154 static void pc_machine_wakeup(MachineState *machine)
2155 {
2156 cpu_synchronize_all_states();
2157 pc_machine_reset(machine);
2158 cpu_synchronize_all_post_reset();
2159 }
2160
2161 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
2162 {
2163 X86IOMMUState *iommu = x86_iommu_get_default();
2164 IntelIOMMUState *intel_iommu;
2165
2166 if (iommu &&
2167 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
2168 object_dynamic_cast((Object *)dev, "vfio-pci")) {
2169 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2170 if (!intel_iommu->caching_mode) {
2171 error_setg(errp, "Device assignment is not allowed without "
2172 "enabling caching-mode=on for Intel IOMMU.");
2173 return false;
2174 }
2175 }
2176
2177 return true;
2178 }
2179
2180 static void pc_machine_class_init(ObjectClass *oc, void *data)
2181 {
2182 MachineClass *mc = MACHINE_CLASS(oc);
2183 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2184 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2185
2186 pcmc->pci_enabled = true;
2187 pcmc->has_acpi_build = true;
2188 pcmc->rsdp_in_ram = true;
2189 pcmc->smbios_defaults = true;
2190 pcmc->smbios_uuid_encoded = true;
2191 pcmc->gigabyte_align = true;
2192 pcmc->has_reserved_memory = true;
2193 pcmc->kvmclock_enabled = true;
2194 pcmc->enforce_aligned_dimm = true;
2195 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2196 * to be used at the moment, 32K should be enough for a while. */
2197 pcmc->acpi_data_size = 0x20000 + 0x8000;
2198 pcmc->save_tsc_khz = true;
2199 pcmc->linuxboot_dma_enabled = true;
2200 pcmc->pvh_enabled = true;
2201 assert(!mc->get_hotplug_handler);
2202 mc->get_hotplug_handler = pc_get_hotplug_handler;
2203 mc->hotplug_allowed = pc_hotplug_allowed;
2204 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
2205 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
2206 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
2207 mc->auto_enable_numa_with_memhp = true;
2208 mc->has_hotpluggable_cpus = true;
2209 mc->default_boot_order = "cad";
2210 mc->hot_add_cpu = pc_hot_add_cpu;
2211 mc->smp_parse = pc_smp_parse;
2212 mc->block_default_type = IF_IDE;
2213 mc->max_cpus = 255;
2214 mc->reset = pc_machine_reset;
2215 mc->wakeup = pc_machine_wakeup;
2216 hc->pre_plug = pc_machine_device_pre_plug_cb;
2217 hc->plug = pc_machine_device_plug_cb;
2218 hc->unplug_request = pc_machine_device_unplug_request_cb;
2219 hc->unplug = pc_machine_device_unplug_cb;
2220 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2221 mc->nvdimm_supported = true;
2222 mc->numa_mem_supported = true;
2223
2224 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2225 pc_machine_get_device_memory_region_size, NULL,
2226 NULL, NULL, &error_abort);
2227
2228 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2229 pc_machine_get_smm, pc_machine_set_smm,
2230 NULL, NULL, &error_abort);
2231 object_class_property_set_description(oc, PC_MACHINE_SMM,
2232 "Enable SMM (pc & q35)", &error_abort);
2233
2234 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2235 pc_machine_get_vmport, pc_machine_set_vmport,
2236 NULL, NULL, &error_abort);
2237 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2238 "Enable vmport (pc & q35)", &error_abort);
2239
2240 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2241 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2242
2243 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2244 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2245
2246 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2247 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2248 }
2249
2250 static const TypeInfo pc_machine_info = {
2251 .name = TYPE_PC_MACHINE,
2252 .parent = TYPE_X86_MACHINE,
2253 .abstract = true,
2254 .instance_size = sizeof(PCMachineState),
2255 .instance_init = pc_machine_initfn,
2256 .class_size = sizeof(PCMachineClass),
2257 .class_init = pc_machine_class_init,
2258 .interfaces = (InterfaceInfo[]) {
2259 { TYPE_HOTPLUG_HANDLER },
2260 { }
2261 },
2262 };
2263
2264 static void pc_machine_register_types(void)
2265 {
2266 type_register_static(&pc_machine_info);
2267 }
2268
2269 type_init(pc_machine_register_types)
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