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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into...
[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "qapi/error.h"
80 #include "qapi/qapi-visit-common.h"
81 #include "qapi/visitor.h"
82 #include "hw/core/cpu.h"
83 #include "hw/usb.h"
84 #include "hw/i386/intel_iommu.h"
85 #include "hw/net/ne2000-isa.h"
86 #include "standard-headers/asm-x86/bootparam.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/mem/memory-device.h"
89 #include "sysemu/replay.h"
90 #include "qapi/qmp/qerror.h"
91 #include "config-devices.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95
96 GlobalProperty pc_compat_4_2[] = {};
97 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
98
99 GlobalProperty pc_compat_4_1[] = {};
100 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
101
102 GlobalProperty pc_compat_4_0[] = {};
103 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
104
105 GlobalProperty pc_compat_3_1[] = {
106 { "intel-iommu", "dma-drain", "off" },
107 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
108 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
109 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
110 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
111 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
112 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
113 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
114 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
115 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
116 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
117 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
119 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
120 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
121 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
122 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
123 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
124 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
125 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
126 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
127 };
128 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
129
130 GlobalProperty pc_compat_3_0[] = {
131 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
132 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
133 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
134 };
135 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
136
137 GlobalProperty pc_compat_2_12[] = {
138 { TYPE_X86_CPU, "legacy-cache", "on" },
139 { TYPE_X86_CPU, "topoext", "off" },
140 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
141 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
142 };
143 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
144
145 GlobalProperty pc_compat_2_11[] = {
146 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
147 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
148 };
149 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
150
151 GlobalProperty pc_compat_2_10[] = {
152 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
153 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
154 { "q35-pcihost", "x-pci-hole64-fix", "off" },
155 };
156 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
157
158 GlobalProperty pc_compat_2_9[] = {
159 { "mch", "extended-tseg-mbytes", "0" },
160 };
161 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
162
163 GlobalProperty pc_compat_2_8[] = {
164 { TYPE_X86_CPU, "tcg-cpuid", "off" },
165 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
166 { "ICH9-LPC", "x-smi-broadcast", "off" },
167 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
168 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
169 };
170 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
171
172 GlobalProperty pc_compat_2_7[] = {
173 { TYPE_X86_CPU, "l3-cache", "off" },
174 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
175 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
176 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
177 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
178 { "isa-pcspk", "migrate", "off" },
179 };
180 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
181
182 GlobalProperty pc_compat_2_6[] = {
183 { TYPE_X86_CPU, "cpuid-0xb", "off" },
184 { "vmxnet3", "romfile", "" },
185 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
186 { "apic-common", "legacy-instance-id", "on", }
187 };
188 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
189
190 GlobalProperty pc_compat_2_5[] = {};
191 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
192
193 GlobalProperty pc_compat_2_4[] = {
194 PC_CPU_MODEL_IDS("2.4.0")
195 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
196 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
197 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
198 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
199 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
200 { TYPE_X86_CPU, "check", "off" },
201 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
202 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
203 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
204 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
205 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
206 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
207 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
208 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
209 };
210 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
211
212 GlobalProperty pc_compat_2_3[] = {
213 PC_CPU_MODEL_IDS("2.3.0")
214 { TYPE_X86_CPU, "arat", "off" },
215 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
216 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
217 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
218 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
219 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
220 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
221 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
222 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
223 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
224 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
225 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
226 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
227 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
228 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
229 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
234 };
235 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
236
237 GlobalProperty pc_compat_2_2[] = {
238 PC_CPU_MODEL_IDS("2.2.0")
239 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
240 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
241 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
242 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
243 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
244 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
245 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
246 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
247 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
256 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
257 };
258 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
259
260 GlobalProperty pc_compat_2_1[] = {
261 PC_CPU_MODEL_IDS("2.1.0")
262 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
263 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
264 };
265 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
266
267 GlobalProperty pc_compat_2_0[] = {
268 PC_CPU_MODEL_IDS("2.0.0")
269 { "virtio-scsi-pci", "any_layout", "off" },
270 { "PIIX4_PM", "memory-hotplug-support", "off" },
271 { "apic", "version", "0x11" },
272 { "nec-usb-xhci", "superspeed-ports-first", "off" },
273 { "nec-usb-xhci", "force-pcie-endcap", "on" },
274 { "pci-serial", "prog_if", "0" },
275 { "pci-serial-2x", "prog_if", "0" },
276 { "pci-serial-4x", "prog_if", "0" },
277 { "virtio-net-pci", "guest_announce", "off" },
278 { "ICH9-LPC", "memory-hotplug-support", "off" },
279 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
280 { "ioh3420", COMPAT_PROP_PCP, "off" },
281 };
282 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
283
284 GlobalProperty pc_compat_1_7[] = {
285 PC_CPU_MODEL_IDS("1.7.0")
286 { TYPE_USB_DEVICE, "msos-desc", "no" },
287 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
288 { "hpet", HPET_INTCAP, "4" },
289 };
290 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
291
292 GlobalProperty pc_compat_1_6[] = {
293 PC_CPU_MODEL_IDS("1.6.0")
294 { "e1000", "mitigation", "off" },
295 { "qemu64-" TYPE_X86_CPU, "model", "2" },
296 { "qemu32-" TYPE_X86_CPU, "model", "3" },
297 { "i440FX-pcihost", "short_root_bus", "1" },
298 { "q35-pcihost", "short_root_bus", "1" },
299 };
300 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
301
302 GlobalProperty pc_compat_1_5[] = {
303 PC_CPU_MODEL_IDS("1.5.0")
304 { "Conroe-" TYPE_X86_CPU, "model", "2" },
305 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
306 { "Penryn-" TYPE_X86_CPU, "model", "2" },
307 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
308 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
309 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
310 { "virtio-net-pci", "any_layout", "off" },
311 { TYPE_X86_CPU, "pmu", "on" },
312 { "i440FX-pcihost", "short_root_bus", "0" },
313 { "q35-pcihost", "short_root_bus", "0" },
314 };
315 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
316
317 GlobalProperty pc_compat_1_4[] = {
318 PC_CPU_MODEL_IDS("1.4.0")
319 { "scsi-hd", "discard_granularity", "0" },
320 { "scsi-cd", "discard_granularity", "0" },
321 { "scsi-disk", "discard_granularity", "0" },
322 { "ide-hd", "discard_granularity", "0" },
323 { "ide-cd", "discard_granularity", "0" },
324 { "ide-drive", "discard_granularity", "0" },
325 { "virtio-blk-pci", "discard_granularity", "0" },
326 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
327 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
328 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
329 { "e1000", "romfile", "pxe-e1000.rom" },
330 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
331 { "pcnet", "romfile", "pxe-pcnet.rom" },
332 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
333 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
334 { "486-" TYPE_X86_CPU, "model", "0" },
335 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
336 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
337 };
338 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
339
340 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
341 {
342 GSIState *s;
343
344 s = g_new0(GSIState, 1);
345 if (kvm_ioapic_in_kernel()) {
346 kvm_pc_setup_irq_routing(pci_enabled);
347 }
348 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
349
350 return s;
351 }
352
353 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
354 unsigned size)
355 {
356 }
357
358 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
359 {
360 return 0xffffffffffffffffULL;
361 }
362
363 /* MSDOS compatibility mode FPU exception support */
364 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
365 unsigned size)
366 {
367 if (tcg_enabled()) {
368 cpu_set_ignne();
369 }
370 }
371
372 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
373 {
374 return 0xffffffffffffffffULL;
375 }
376
377 /* PC cmos mappings */
378
379 #define REG_EQUIPMENT_BYTE 0x14
380
381 int cmos_get_fd_drive_type(FloppyDriveType fd0)
382 {
383 int val;
384
385 switch (fd0) {
386 case FLOPPY_DRIVE_TYPE_144:
387 /* 1.44 Mb 3"5 drive */
388 val = 4;
389 break;
390 case FLOPPY_DRIVE_TYPE_288:
391 /* 2.88 Mb 3"5 drive */
392 val = 5;
393 break;
394 case FLOPPY_DRIVE_TYPE_120:
395 /* 1.2 Mb 5"5 drive */
396 val = 2;
397 break;
398 case FLOPPY_DRIVE_TYPE_NONE:
399 default:
400 val = 0;
401 break;
402 }
403 return val;
404 }
405
406 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
407 int16_t cylinders, int8_t heads, int8_t sectors)
408 {
409 rtc_set_memory(s, type_ofs, 47);
410 rtc_set_memory(s, info_ofs, cylinders);
411 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
412 rtc_set_memory(s, info_ofs + 2, heads);
413 rtc_set_memory(s, info_ofs + 3, 0xff);
414 rtc_set_memory(s, info_ofs + 4, 0xff);
415 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
416 rtc_set_memory(s, info_ofs + 6, cylinders);
417 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
418 rtc_set_memory(s, info_ofs + 8, sectors);
419 }
420
421 /* convert boot_device letter to something recognizable by the bios */
422 static int boot_device2nibble(char boot_device)
423 {
424 switch(boot_device) {
425 case 'a':
426 case 'b':
427 return 0x01; /* floppy boot */
428 case 'c':
429 return 0x02; /* hard drive boot */
430 case 'd':
431 return 0x03; /* CD-ROM boot */
432 case 'n':
433 return 0x04; /* Network boot */
434 }
435 return 0;
436 }
437
438 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
439 {
440 #define PC_MAX_BOOT_DEVICES 3
441 int nbds, bds[3] = { 0, };
442 int i;
443
444 nbds = strlen(boot_device);
445 if (nbds > PC_MAX_BOOT_DEVICES) {
446 error_setg(errp, "Too many boot devices for PC");
447 return;
448 }
449 for (i = 0; i < nbds; i++) {
450 bds[i] = boot_device2nibble(boot_device[i]);
451 if (bds[i] == 0) {
452 error_setg(errp, "Invalid boot device for PC: '%c'",
453 boot_device[i]);
454 return;
455 }
456 }
457 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
458 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
459 }
460
461 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
462 {
463 set_boot_dev(opaque, boot_device, errp);
464 }
465
466 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
467 {
468 int val, nb, i;
469 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
470 FLOPPY_DRIVE_TYPE_NONE };
471
472 /* floppy type */
473 if (floppy) {
474 for (i = 0; i < 2; i++) {
475 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
476 }
477 }
478 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
479 cmos_get_fd_drive_type(fd_type[1]);
480 rtc_set_memory(rtc_state, 0x10, val);
481
482 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
483 nb = 0;
484 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
485 nb++;
486 }
487 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
488 nb++;
489 }
490 switch (nb) {
491 case 0:
492 break;
493 case 1:
494 val |= 0x01; /* 1 drive, ready for boot */
495 break;
496 case 2:
497 val |= 0x41; /* 2 drives, ready for boot */
498 break;
499 }
500 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
501 }
502
503 typedef struct pc_cmos_init_late_arg {
504 ISADevice *rtc_state;
505 BusState *idebus[2];
506 } pc_cmos_init_late_arg;
507
508 typedef struct check_fdc_state {
509 ISADevice *floppy;
510 bool multiple;
511 } CheckFdcState;
512
513 static int check_fdc(Object *obj, void *opaque)
514 {
515 CheckFdcState *state = opaque;
516 Object *fdc;
517 uint32_t iobase;
518 Error *local_err = NULL;
519
520 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
521 if (!fdc) {
522 return 0;
523 }
524
525 iobase = object_property_get_uint(obj, "iobase", &local_err);
526 if (local_err || iobase != 0x3f0) {
527 error_free(local_err);
528 return 0;
529 }
530
531 if (state->floppy) {
532 state->multiple = true;
533 } else {
534 state->floppy = ISA_DEVICE(obj);
535 }
536 return 0;
537 }
538
539 static const char * const fdc_container_path[] = {
540 "/unattached", "/peripheral", "/peripheral-anon"
541 };
542
543 /*
544 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
545 * and ACPI objects.
546 */
547 ISADevice *pc_find_fdc0(void)
548 {
549 int i;
550 Object *container;
551 CheckFdcState state = { 0 };
552
553 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
554 container = container_get(qdev_get_machine(), fdc_container_path[i]);
555 object_child_foreach(container, check_fdc, &state);
556 }
557
558 if (state.multiple) {
559 warn_report("multiple floppy disk controllers with "
560 "iobase=0x3f0 have been found");
561 error_printf("the one being picked for CMOS setup might not reflect "
562 "your intent");
563 }
564
565 return state.floppy;
566 }
567
568 static void pc_cmos_init_late(void *opaque)
569 {
570 pc_cmos_init_late_arg *arg = opaque;
571 ISADevice *s = arg->rtc_state;
572 int16_t cylinders;
573 int8_t heads, sectors;
574 int val;
575 int i, trans;
576
577 val = 0;
578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
579 &cylinders, &heads, &sectors) >= 0) {
580 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
581 val |= 0xf0;
582 }
583 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
584 &cylinders, &heads, &sectors) >= 0) {
585 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
586 val |= 0x0f;
587 }
588 rtc_set_memory(s, 0x12, val);
589
590 val = 0;
591 for (i = 0; i < 4; i++) {
592 /* NOTE: ide_get_geometry() returns the physical
593 geometry. It is always such that: 1 <= sects <= 63, 1
594 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
595 geometry can be different if a translation is done. */
596 if (arg->idebus[i / 2] &&
597 ide_get_geometry(arg->idebus[i / 2], i % 2,
598 &cylinders, &heads, &sectors) >= 0) {
599 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
600 assert((trans & ~3) == 0);
601 val |= trans << (i * 2);
602 }
603 }
604 rtc_set_memory(s, 0x39, val);
605
606 pc_cmos_init_floppy(s, pc_find_fdc0());
607
608 qemu_unregister_reset(pc_cmos_init_late, opaque);
609 }
610
611 void pc_cmos_init(PCMachineState *pcms,
612 BusState *idebus0, BusState *idebus1,
613 ISADevice *s)
614 {
615 int val;
616 static pc_cmos_init_late_arg arg;
617 X86MachineState *x86ms = X86_MACHINE(pcms);
618
619 /* various important CMOS locations needed by PC/Bochs bios */
620
621 /* memory size */
622 /* base memory (first MiB) */
623 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
624 rtc_set_memory(s, 0x15, val);
625 rtc_set_memory(s, 0x16, val >> 8);
626 /* extended memory (next 64MiB) */
627 if (x86ms->below_4g_mem_size > 1 * MiB) {
628 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
629 } else {
630 val = 0;
631 }
632 if (val > 65535)
633 val = 65535;
634 rtc_set_memory(s, 0x17, val);
635 rtc_set_memory(s, 0x18, val >> 8);
636 rtc_set_memory(s, 0x30, val);
637 rtc_set_memory(s, 0x31, val >> 8);
638 /* memory between 16MiB and 4GiB */
639 if (x86ms->below_4g_mem_size > 16 * MiB) {
640 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
641 } else {
642 val = 0;
643 }
644 if (val > 65535)
645 val = 65535;
646 rtc_set_memory(s, 0x34, val);
647 rtc_set_memory(s, 0x35, val >> 8);
648 /* memory above 4GiB */
649 val = x86ms->above_4g_mem_size / 65536;
650 rtc_set_memory(s, 0x5b, val);
651 rtc_set_memory(s, 0x5c, val >> 8);
652 rtc_set_memory(s, 0x5d, val >> 16);
653
654 object_property_add_link(OBJECT(pcms), "rtc_state",
655 TYPE_ISA_DEVICE,
656 (Object **)&x86ms->rtc,
657 object_property_allow_set_link,
658 OBJ_PROP_LINK_STRONG, &error_abort);
659 object_property_set_link(OBJECT(pcms), OBJECT(s),
660 "rtc_state", &error_abort);
661
662 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
663
664 val = 0;
665 val |= 0x02; /* FPU is there */
666 val |= 0x04; /* PS/2 mouse installed */
667 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
668
669 /* hard drives and FDC */
670 arg.rtc_state = s;
671 arg.idebus[0] = idebus0;
672 arg.idebus[1] = idebus1;
673 qemu_register_reset(pc_cmos_init_late, &arg);
674 }
675
676 static void handle_a20_line_change(void *opaque, int irq, int level)
677 {
678 X86CPU *cpu = opaque;
679
680 /* XXX: send to all CPUs ? */
681 /* XXX: add logic to handle multiple A20 line sources */
682 x86_cpu_set_a20(cpu, level);
683 }
684
685 #define NE2000_NB_MAX 6
686
687 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
688 0x280, 0x380 };
689 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
690
691 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
692 {
693 static int nb_ne2k = 0;
694
695 if (nb_ne2k == NE2000_NB_MAX)
696 return;
697 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
698 ne2000_irq[nb_ne2k], nd);
699 nb_ne2k++;
700 }
701
702 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
703 {
704 X86CPU *cpu = opaque;
705
706 if (level) {
707 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
708 }
709 }
710
711 /*
712 * This function is very similar to smp_parse()
713 * in hw/core/machine.c but includes CPU die support.
714 */
715 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
716 {
717 X86MachineState *x86ms = X86_MACHINE(ms);
718
719 if (opts) {
720 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
721 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
722 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
723 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
724 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
725
726 /* compute missing values, prefer sockets over cores over threads */
727 if (cpus == 0 || sockets == 0) {
728 cores = cores > 0 ? cores : 1;
729 threads = threads > 0 ? threads : 1;
730 if (cpus == 0) {
731 sockets = sockets > 0 ? sockets : 1;
732 cpus = cores * threads * dies * sockets;
733 } else {
734 ms->smp.max_cpus =
735 qemu_opt_get_number(opts, "maxcpus", cpus);
736 sockets = ms->smp.max_cpus / (cores * threads * dies);
737 }
738 } else if (cores == 0) {
739 threads = threads > 0 ? threads : 1;
740 cores = cpus / (sockets * dies * threads);
741 cores = cores > 0 ? cores : 1;
742 } else if (threads == 0) {
743 threads = cpus / (cores * dies * sockets);
744 threads = threads > 0 ? threads : 1;
745 } else if (sockets * dies * cores * threads < cpus) {
746 error_report("cpu topology: "
747 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
748 "smp_cpus (%u)",
749 sockets, dies, cores, threads, cpus);
750 exit(1);
751 }
752
753 ms->smp.max_cpus =
754 qemu_opt_get_number(opts, "maxcpus", cpus);
755
756 if (ms->smp.max_cpus < cpus) {
757 error_report("maxcpus must be equal to or greater than smp");
758 exit(1);
759 }
760
761 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
762 error_report("cpu topology: "
763 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
764 "maxcpus (%u)",
765 sockets, dies, cores, threads,
766 ms->smp.max_cpus);
767 exit(1);
768 }
769
770 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
771 warn_report("Invalid CPU topology deprecated: "
772 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
773 "!= maxcpus (%u)",
774 sockets, dies, cores, threads,
775 ms->smp.max_cpus);
776 }
777
778 ms->smp.cpus = cpus;
779 ms->smp.cores = cores;
780 ms->smp.threads = threads;
781 x86ms->smp_dies = dies;
782 }
783
784 if (ms->smp.cpus > 1) {
785 Error *blocker = NULL;
786 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
787 replay_add_blocker(blocker);
788 }
789 }
790
791 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
792 {
793 X86MachineState *x86ms = X86_MACHINE(ms);
794 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
795 Error *local_err = NULL;
796
797 if (id < 0) {
798 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
799 return;
800 }
801
802 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
803 error_setg(errp, "Unable to add CPU: %" PRIi64
804 ", resulting APIC ID (%" PRIi64 ") is too large",
805 id, apic_id);
806 return;
807 }
808
809
810 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
811 if (local_err) {
812 error_propagate(errp, local_err);
813 return;
814 }
815 }
816
817 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
818 {
819 if (cpus_count > 0xff) {
820 /* If the number of CPUs can't be represented in 8 bits, the
821 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
822 * to make old BIOSes fail more predictably.
823 */
824 rtc_set_memory(rtc, 0x5f, 0);
825 } else {
826 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
827 }
828 }
829
830 static
831 void pc_machine_done(Notifier *notifier, void *data)
832 {
833 PCMachineState *pcms = container_of(notifier,
834 PCMachineState, machine_done);
835 X86MachineState *x86ms = X86_MACHINE(pcms);
836 PCIBus *bus = pcms->bus;
837
838 /* set the number of CPUs */
839 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
840
841 if (bus) {
842 int extra_hosts = 0;
843
844 QLIST_FOREACH(bus, &bus->child, sibling) {
845 /* look for expander root buses */
846 if (pci_bus_is_root(bus)) {
847 extra_hosts++;
848 }
849 }
850 if (extra_hosts && x86ms->fw_cfg) {
851 uint64_t *val = g_malloc(sizeof(*val));
852 *val = cpu_to_le64(extra_hosts);
853 fw_cfg_add_file(x86ms->fw_cfg,
854 "etc/extra-pci-roots", val, sizeof(*val));
855 }
856 }
857
858 acpi_setup();
859 if (x86ms->fw_cfg) {
860 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
861 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
862 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
863 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
864 }
865
866 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
867 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
868
869 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
870 iommu->intr_eim != ON_OFF_AUTO_ON) {
871 error_report("current -smp configuration requires "
872 "Extended Interrupt Mode enabled. "
873 "You can add an IOMMU using: "
874 "-device intel-iommu,intremap=on,eim=on");
875 exit(EXIT_FAILURE);
876 }
877 }
878 }
879
880 void pc_guest_info_init(PCMachineState *pcms)
881 {
882 int i;
883 MachineState *ms = MACHINE(pcms);
884 X86MachineState *x86ms = X86_MACHINE(pcms);
885
886 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
887 pcms->numa_nodes = ms->numa_state->num_nodes;
888 pcms->node_mem = g_malloc0(pcms->numa_nodes *
889 sizeof *pcms->node_mem);
890 for (i = 0; i < ms->numa_state->num_nodes; i++) {
891 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
892 }
893
894 pcms->machine_done.notify = pc_machine_done;
895 qemu_add_machine_init_done_notifier(&pcms->machine_done);
896 }
897
898 /* setup pci memory address space mapping into system address space */
899 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
900 MemoryRegion *pci_address_space)
901 {
902 /* Set to lower priority than RAM */
903 memory_region_add_subregion_overlap(system_memory, 0x0,
904 pci_address_space, -1);
905 }
906
907 void xen_load_linux(PCMachineState *pcms)
908 {
909 int i;
910 FWCfgState *fw_cfg;
911 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
912 X86MachineState *x86ms = X86_MACHINE(pcms);
913
914 assert(MACHINE(pcms)->kernel_filename != NULL);
915
916 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
917 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
918 rom_set_fw(fw_cfg);
919
920 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
921 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
922 for (i = 0; i < nb_option_roms; i++) {
923 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
924 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
925 !strcmp(option_rom[i].name, "pvh.bin") ||
926 !strcmp(option_rom[i].name, "multiboot.bin"));
927 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
928 }
929 x86ms->fw_cfg = fw_cfg;
930 }
931
932 void pc_memory_init(PCMachineState *pcms,
933 MemoryRegion *system_memory,
934 MemoryRegion *rom_memory,
935 MemoryRegion **ram_memory)
936 {
937 int linux_boot, i;
938 MemoryRegion *ram, *option_rom_mr;
939 MemoryRegion *ram_below_4g, *ram_above_4g;
940 FWCfgState *fw_cfg;
941 MachineState *machine = MACHINE(pcms);
942 MachineClass *mc = MACHINE_GET_CLASS(machine);
943 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
944 X86MachineState *x86ms = X86_MACHINE(pcms);
945
946 assert(machine->ram_size == x86ms->below_4g_mem_size +
947 x86ms->above_4g_mem_size);
948
949 linux_boot = (machine->kernel_filename != NULL);
950
951 /* Allocate RAM. We allocate it as a single memory region and use
952 * aliases to address portions of it, mostly for backwards compatibility
953 * with older qemus that used qemu_ram_alloc().
954 */
955 ram = g_malloc(sizeof(*ram));
956 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
957 machine->ram_size);
958 *ram_memory = ram;
959 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
960 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
961 0, x86ms->below_4g_mem_size);
962 memory_region_add_subregion(system_memory, 0, ram_below_4g);
963 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
964 if (x86ms->above_4g_mem_size > 0) {
965 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
966 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
967 x86ms->below_4g_mem_size,
968 x86ms->above_4g_mem_size);
969 memory_region_add_subregion(system_memory, 0x100000000ULL,
970 ram_above_4g);
971 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
972 }
973
974 if (!pcmc->has_reserved_memory &&
975 (machine->ram_slots ||
976 (machine->maxram_size > machine->ram_size))) {
977
978 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
979 mc->name);
980 exit(EXIT_FAILURE);
981 }
982
983 /* always allocate the device memory information */
984 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
985
986 /* initialize device memory address space */
987 if (pcmc->has_reserved_memory &&
988 (machine->ram_size < machine->maxram_size)) {
989 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
990
991 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
992 error_report("unsupported amount of memory slots: %"PRIu64,
993 machine->ram_slots);
994 exit(EXIT_FAILURE);
995 }
996
997 if (QEMU_ALIGN_UP(machine->maxram_size,
998 TARGET_PAGE_SIZE) != machine->maxram_size) {
999 error_report("maximum memory size must by aligned to multiple of "
1000 "%d bytes", TARGET_PAGE_SIZE);
1001 exit(EXIT_FAILURE);
1002 }
1003
1004 machine->device_memory->base =
1005 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1006
1007 if (pcmc->enforce_aligned_dimm) {
1008 /* size device region assuming 1G page max alignment per slot */
1009 device_mem_size += (1 * GiB) * machine->ram_slots;
1010 }
1011
1012 if ((machine->device_memory->base + device_mem_size) <
1013 device_mem_size) {
1014 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1015 machine->maxram_size);
1016 exit(EXIT_FAILURE);
1017 }
1018
1019 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1020 "device-memory", device_mem_size);
1021 memory_region_add_subregion(system_memory, machine->device_memory->base,
1022 &machine->device_memory->mr);
1023 }
1024
1025 /* Initialize PC system firmware */
1026 pc_system_firmware_init(pcms, rom_memory);
1027
1028 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1029 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1030 &error_fatal);
1031 if (pcmc->pci_enabled) {
1032 memory_region_set_readonly(option_rom_mr, true);
1033 }
1034 memory_region_add_subregion_overlap(rom_memory,
1035 PC_ROM_MIN_VGA,
1036 option_rom_mr,
1037 1);
1038
1039 fw_cfg = fw_cfg_arch_create(machine,
1040 x86ms->boot_cpus, x86ms->apic_id_limit);
1041
1042 rom_set_fw(fw_cfg);
1043
1044 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1045 uint64_t *val = g_malloc(sizeof(*val));
1046 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1047 uint64_t res_mem_end = machine->device_memory->base;
1048
1049 if (!pcmc->broken_reserved_end) {
1050 res_mem_end += memory_region_size(&machine->device_memory->mr);
1051 }
1052 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1053 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1054 }
1055
1056 if (linux_boot) {
1057 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1058 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1059 }
1060
1061 for (i = 0; i < nb_option_roms; i++) {
1062 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1063 }
1064 x86ms->fw_cfg = fw_cfg;
1065
1066 /* Init default IOAPIC address space */
1067 x86ms->ioapic_as = &address_space_memory;
1068
1069 /* Init ACPI memory hotplug IO base address */
1070 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1071 }
1072
1073 /*
1074 * The 64bit pci hole starts after "above 4G RAM" and
1075 * potentially the space reserved for memory hotplug.
1076 */
1077 uint64_t pc_pci_hole64_start(void)
1078 {
1079 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1080 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1081 MachineState *ms = MACHINE(pcms);
1082 X86MachineState *x86ms = X86_MACHINE(pcms);
1083 uint64_t hole64_start = 0;
1084
1085 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1086 hole64_start = ms->device_memory->base;
1087 if (!pcmc->broken_reserved_end) {
1088 hole64_start += memory_region_size(&ms->device_memory->mr);
1089 }
1090 } else {
1091 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1092 }
1093
1094 return ROUND_UP(hole64_start, 1 * GiB);
1095 }
1096
1097 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1098 {
1099 DeviceState *dev = NULL;
1100
1101 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1102 if (pci_bus) {
1103 PCIDevice *pcidev = pci_vga_init(pci_bus);
1104 dev = pcidev ? &pcidev->qdev : NULL;
1105 } else if (isa_bus) {
1106 ISADevice *isadev = isa_vga_init(isa_bus);
1107 dev = isadev ? DEVICE(isadev) : NULL;
1108 }
1109 rom_reset_order_override();
1110 return dev;
1111 }
1112
1113 static const MemoryRegionOps ioport80_io_ops = {
1114 .write = ioport80_write,
1115 .read = ioport80_read,
1116 .endianness = DEVICE_NATIVE_ENDIAN,
1117 .impl = {
1118 .min_access_size = 1,
1119 .max_access_size = 1,
1120 },
1121 };
1122
1123 static const MemoryRegionOps ioportF0_io_ops = {
1124 .write = ioportF0_write,
1125 .read = ioportF0_read,
1126 .endianness = DEVICE_NATIVE_ENDIAN,
1127 .impl = {
1128 .min_access_size = 1,
1129 .max_access_size = 1,
1130 },
1131 };
1132
1133 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1134 {
1135 int i;
1136 DriveInfo *fd[MAX_FD];
1137 qemu_irq *a20_line;
1138 ISADevice *i8042, *port92, *vmmouse;
1139
1140 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1141 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1142
1143 for (i = 0; i < MAX_FD; i++) {
1144 fd[i] = drive_get(IF_FLOPPY, 0, i);
1145 create_fdctrl |= !!fd[i];
1146 }
1147 if (create_fdctrl) {
1148 fdctrl_init_isa(isa_bus, fd);
1149 }
1150
1151 i8042 = isa_create_simple(isa_bus, "i8042");
1152 if (!no_vmport) {
1153 vmport_init(isa_bus);
1154 vmmouse = isa_try_create(isa_bus, "vmmouse");
1155 } else {
1156 vmmouse = NULL;
1157 }
1158 if (vmmouse) {
1159 DeviceState *dev = DEVICE(vmmouse);
1160 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1161 qdev_init_nofail(dev);
1162 }
1163 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1164
1165 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1166 i8042_setup_a20_line(i8042, a20_line[0]);
1167 qdev_connect_gpio_out_named(DEVICE(port92),
1168 PORT92_A20_LINE, 0, a20_line[1]);
1169 g_free(a20_line);
1170 }
1171
1172 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1173 ISADevice **rtc_state,
1174 bool create_fdctrl,
1175 bool no_vmport,
1176 bool has_pit,
1177 uint32_t hpet_irqs)
1178 {
1179 int i;
1180 DeviceState *hpet = NULL;
1181 int pit_isa_irq = 0;
1182 qemu_irq pit_alt_irq = NULL;
1183 qemu_irq rtc_irq = NULL;
1184 ISADevice *pit = NULL;
1185 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1186 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1187
1188 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1189 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1190
1191 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1192 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1193
1194 /*
1195 * Check if an HPET shall be created.
1196 *
1197 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1198 * when the HPET wants to take over. Thus we have to disable the latter.
1199 */
1200 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1201 /* In order to set property, here not using sysbus_try_create_simple */
1202 hpet = qdev_try_create(NULL, TYPE_HPET);
1203 if (hpet) {
1204 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1205 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1206 * IRQ8 and IRQ2.
1207 */
1208 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1209 HPET_INTCAP, NULL);
1210 if (!compat) {
1211 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1212 }
1213 qdev_init_nofail(hpet);
1214 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1215
1216 for (i = 0; i < GSI_NUM_PINS; i++) {
1217 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1218 }
1219 pit_isa_irq = -1;
1220 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1221 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1222 }
1223 }
1224 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1225
1226 qemu_register_boot_set(pc_boot_set, *rtc_state);
1227
1228 if (!xen_enabled() && has_pit) {
1229 if (kvm_pit_in_kernel()) {
1230 pit = kvm_pit_init(isa_bus, 0x40);
1231 } else {
1232 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1233 }
1234 if (hpet) {
1235 /* connect PIT to output control line of the HPET */
1236 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1237 }
1238 pcspk_init(isa_bus, pit);
1239 }
1240
1241 i8257_dma_init(isa_bus, 0);
1242
1243 /* Super I/O */
1244 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1245 }
1246
1247 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1248 {
1249 int i;
1250
1251 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1252 for (i = 0; i < nb_nics; i++) {
1253 NICInfo *nd = &nd_table[i];
1254 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1255
1256 if (g_str_equal(model, "ne2k_isa")) {
1257 pc_init_ne2k_isa(isa_bus, nd);
1258 } else {
1259 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1260 }
1261 }
1262 rom_reset_order_override();
1263 }
1264
1265 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1266 {
1267 qemu_irq *i8259;
1268
1269 if (kvm_pic_in_kernel()) {
1270 i8259 = kvm_i8259_init(isa_bus);
1271 } else if (xen_enabled()) {
1272 i8259 = xen_interrupt_controller_init();
1273 } else {
1274 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1275 }
1276
1277 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1278 i8259_irqs[i] = i8259[i];
1279 }
1280
1281 g_free(i8259);
1282 }
1283
1284 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1285 Error **errp)
1286 {
1287 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1288 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1289 const MachineState *ms = MACHINE(hotplug_dev);
1290 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1291 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1292 Error *local_err = NULL;
1293
1294 /*
1295 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1296 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1297 * addition to cover this case.
1298 */
1299 if (!pcms->acpi_dev || !acpi_enabled) {
1300 error_setg(errp,
1301 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1302 return;
1303 }
1304
1305 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1306 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1307 return;
1308 }
1309
1310 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1311 if (local_err) {
1312 error_propagate(errp, local_err);
1313 return;
1314 }
1315
1316 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1317 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1318 }
1319
1320 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1321 DeviceState *dev, Error **errp)
1322 {
1323 Error *local_err = NULL;
1324 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1325 MachineState *ms = MACHINE(hotplug_dev);
1326 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1327
1328 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1329 if (local_err) {
1330 goto out;
1331 }
1332
1333 if (is_nvdimm) {
1334 nvdimm_plug(ms->nvdimms_state);
1335 }
1336
1337 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1338 out:
1339 error_propagate(errp, local_err);
1340 }
1341
1342 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1343 DeviceState *dev, Error **errp)
1344 {
1345 Error *local_err = NULL;
1346 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1347
1348 /*
1349 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1350 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1351 * addition to cover this case.
1352 */
1353 if (!pcms->acpi_dev || !acpi_enabled) {
1354 error_setg(&local_err,
1355 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1356 goto out;
1357 }
1358
1359 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1360 error_setg(&local_err,
1361 "nvdimm device hot unplug is not supported yet.");
1362 goto out;
1363 }
1364
1365 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1366 &local_err);
1367 out:
1368 error_propagate(errp, local_err);
1369 }
1370
1371 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1372 DeviceState *dev, Error **errp)
1373 {
1374 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1375 Error *local_err = NULL;
1376
1377 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1378 if (local_err) {
1379 goto out;
1380 }
1381
1382 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1383 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1384 out:
1385 error_propagate(errp, local_err);
1386 }
1387
1388 static int pc_apic_cmp(const void *a, const void *b)
1389 {
1390 CPUArchId *apic_a = (CPUArchId *)a;
1391 CPUArchId *apic_b = (CPUArchId *)b;
1392
1393 return apic_a->arch_id - apic_b->arch_id;
1394 }
1395
1396 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1397 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1398 * entry corresponding to CPU's apic_id returns NULL.
1399 */
1400 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1401 {
1402 CPUArchId apic_id, *found_cpu;
1403
1404 apic_id.arch_id = id;
1405 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1406 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1407 pc_apic_cmp);
1408 if (found_cpu && idx) {
1409 *idx = found_cpu - ms->possible_cpus->cpus;
1410 }
1411 return found_cpu;
1412 }
1413
1414 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1415 DeviceState *dev, Error **errp)
1416 {
1417 CPUArchId *found_cpu;
1418 Error *local_err = NULL;
1419 X86CPU *cpu = X86_CPU(dev);
1420 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1421 X86MachineState *x86ms = X86_MACHINE(pcms);
1422
1423 if (pcms->acpi_dev) {
1424 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1425 if (local_err) {
1426 goto out;
1427 }
1428 }
1429
1430 /* increment the number of CPUs */
1431 x86ms->boot_cpus++;
1432 if (x86ms->rtc) {
1433 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1434 }
1435 if (x86ms->fw_cfg) {
1436 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1437 }
1438
1439 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1440 found_cpu->cpu = OBJECT(dev);
1441 out:
1442 error_propagate(errp, local_err);
1443 }
1444 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1445 DeviceState *dev, Error **errp)
1446 {
1447 int idx = -1;
1448 Error *local_err = NULL;
1449 X86CPU *cpu = X86_CPU(dev);
1450 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1451
1452 if (!pcms->acpi_dev) {
1453 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1454 goto out;
1455 }
1456
1457 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1458 assert(idx != -1);
1459 if (idx == 0) {
1460 error_setg(&local_err, "Boot CPU is unpluggable");
1461 goto out;
1462 }
1463
1464 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1465 &local_err);
1466 if (local_err) {
1467 goto out;
1468 }
1469
1470 out:
1471 error_propagate(errp, local_err);
1472
1473 }
1474
1475 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1476 DeviceState *dev, Error **errp)
1477 {
1478 CPUArchId *found_cpu;
1479 Error *local_err = NULL;
1480 X86CPU *cpu = X86_CPU(dev);
1481 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1482 X86MachineState *x86ms = X86_MACHINE(pcms);
1483
1484 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1485 if (local_err) {
1486 goto out;
1487 }
1488
1489 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1490 found_cpu->cpu = NULL;
1491 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1492
1493 /* decrement the number of CPUs */
1494 x86ms->boot_cpus--;
1495 /* Update the number of CPUs in CMOS */
1496 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1497 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1498 out:
1499 error_propagate(errp, local_err);
1500 }
1501
1502 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1503 DeviceState *dev, Error **errp)
1504 {
1505 int idx;
1506 CPUState *cs;
1507 CPUArchId *cpu_slot;
1508 X86CPUTopoInfo topo;
1509 X86CPU *cpu = X86_CPU(dev);
1510 CPUX86State *env = &cpu->env;
1511 MachineState *ms = MACHINE(hotplug_dev);
1512 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1513 X86MachineState *x86ms = X86_MACHINE(pcms);
1514 unsigned int smp_cores = ms->smp.cores;
1515 unsigned int smp_threads = ms->smp.threads;
1516
1517 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1518 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1519 ms->cpu_type);
1520 return;
1521 }
1522
1523 env->nr_dies = x86ms->smp_dies;
1524
1525 /*
1526 * If APIC ID is not set,
1527 * set it based on socket/die/core/thread properties.
1528 */
1529 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1530 int max_socket = (ms->smp.max_cpus - 1) /
1531 smp_threads / smp_cores / x86ms->smp_dies;
1532
1533 /*
1534 * die-id was optional in QEMU 4.0 and older, so keep it optional
1535 * if there's only one die per socket.
1536 */
1537 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1538 cpu->die_id = 0;
1539 }
1540
1541 if (cpu->socket_id < 0) {
1542 error_setg(errp, "CPU socket-id is not set");
1543 return;
1544 } else if (cpu->socket_id > max_socket) {
1545 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1546 cpu->socket_id, max_socket);
1547 return;
1548 }
1549 if (cpu->die_id < 0) {
1550 error_setg(errp, "CPU die-id is not set");
1551 return;
1552 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1553 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1554 cpu->die_id, x86ms->smp_dies - 1);
1555 return;
1556 }
1557 if (cpu->core_id < 0) {
1558 error_setg(errp, "CPU core-id is not set");
1559 return;
1560 } else if (cpu->core_id > (smp_cores - 1)) {
1561 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1562 cpu->core_id, smp_cores - 1);
1563 return;
1564 }
1565 if (cpu->thread_id < 0) {
1566 error_setg(errp, "CPU thread-id is not set");
1567 return;
1568 } else if (cpu->thread_id > (smp_threads - 1)) {
1569 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1570 cpu->thread_id, smp_threads - 1);
1571 return;
1572 }
1573
1574 topo.pkg_id = cpu->socket_id;
1575 topo.die_id = cpu->die_id;
1576 topo.core_id = cpu->core_id;
1577 topo.smt_id = cpu->thread_id;
1578 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
1579 smp_threads, &topo);
1580 }
1581
1582 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1583 if (!cpu_slot) {
1584 MachineState *ms = MACHINE(pcms);
1585
1586 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1587 smp_cores, smp_threads, &topo);
1588 error_setg(errp,
1589 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1590 " APIC ID %" PRIu32 ", valid index range 0:%d",
1591 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
1592 cpu->apic_id, ms->possible_cpus->len - 1);
1593 return;
1594 }
1595
1596 if (cpu_slot->cpu) {
1597 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1598 idx, cpu->apic_id);
1599 return;
1600 }
1601
1602 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1603 * so that machine_query_hotpluggable_cpus would show correct values
1604 */
1605 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1606 * once -smp refactoring is complete and there will be CPU private
1607 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1608 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
1609 smp_cores, smp_threads, &topo);
1610 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1611 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1612 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1613 return;
1614 }
1615 cpu->socket_id = topo.pkg_id;
1616
1617 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
1618 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1619 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
1620 return;
1621 }
1622 cpu->die_id = topo.die_id;
1623
1624 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1625 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1626 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1627 return;
1628 }
1629 cpu->core_id = topo.core_id;
1630
1631 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1632 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1633 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1634 return;
1635 }
1636 cpu->thread_id = topo.smt_id;
1637
1638 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1639 !kvm_hv_vpindex_settable()) {
1640 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1641 return;
1642 }
1643
1644 cs = CPU(cpu);
1645 cs->cpu_index = idx;
1646
1647 numa_cpu_pre_plug(cpu_slot, dev, errp);
1648 }
1649
1650 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1651 DeviceState *dev, Error **errp)
1652 {
1653 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1654 Error *local_err = NULL;
1655
1656 if (!hotplug_dev2) {
1657 /*
1658 * Without a bus hotplug handler, we cannot control the plug/unplug
1659 * order. This should never be the case on x86, however better add
1660 * a safety net.
1661 */
1662 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1663 return;
1664 }
1665 /*
1666 * First, see if we can plug this memory device at all. If that
1667 * succeeds, branch of to the actual hotplug handler.
1668 */
1669 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1670 &local_err);
1671 if (!local_err) {
1672 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1673 }
1674 error_propagate(errp, local_err);
1675 }
1676
1677 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1678 DeviceState *dev, Error **errp)
1679 {
1680 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1681 Error *local_err = NULL;
1682
1683 /*
1684 * Plug the memory device first and then branch off to the actual
1685 * hotplug handler. If that one fails, we can easily undo the memory
1686 * device bits.
1687 */
1688 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1689 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1690 if (local_err) {
1691 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1692 }
1693 error_propagate(errp, local_err);
1694 }
1695
1696 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1697 DeviceState *dev, Error **errp)
1698 {
1699 /* We don't support virtio pmem hot unplug */
1700 error_setg(errp, "virtio pmem device unplug not supported.");
1701 }
1702
1703 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1704 DeviceState *dev, Error **errp)
1705 {
1706 /* We don't support virtio pmem hot unplug */
1707 }
1708
1709 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1710 DeviceState *dev, Error **errp)
1711 {
1712 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1713 pc_memory_pre_plug(hotplug_dev, dev, errp);
1714 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1715 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1716 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1717 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1718 }
1719 }
1720
1721 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1722 DeviceState *dev, Error **errp)
1723 {
1724 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1725 pc_memory_plug(hotplug_dev, dev, errp);
1726 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1727 pc_cpu_plug(hotplug_dev, dev, errp);
1728 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1729 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1730 }
1731 }
1732
1733 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1734 DeviceState *dev, Error **errp)
1735 {
1736 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1737 pc_memory_unplug_request(hotplug_dev, dev, errp);
1738 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1739 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1740 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1741 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1742 } else {
1743 error_setg(errp, "acpi: device unplug request for not supported device"
1744 " type: %s", object_get_typename(OBJECT(dev)));
1745 }
1746 }
1747
1748 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1749 DeviceState *dev, Error **errp)
1750 {
1751 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1752 pc_memory_unplug(hotplug_dev, dev, errp);
1753 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1754 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1755 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1756 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1757 } else {
1758 error_setg(errp, "acpi: device unplug for not supported device"
1759 " type: %s", object_get_typename(OBJECT(dev)));
1760 }
1761 }
1762
1763 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1764 DeviceState *dev)
1765 {
1766 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1767 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1768 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1769 return HOTPLUG_HANDLER(machine);
1770 }
1771
1772 return NULL;
1773 }
1774
1775 static void
1776 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1777 const char *name, void *opaque,
1778 Error **errp)
1779 {
1780 MachineState *ms = MACHINE(obj);
1781 int64_t value = 0;
1782
1783 if (ms->device_memory) {
1784 value = memory_region_size(&ms->device_memory->mr);
1785 }
1786
1787 visit_type_int(v, name, &value, errp);
1788 }
1789
1790 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1791 void *opaque, Error **errp)
1792 {
1793 PCMachineState *pcms = PC_MACHINE(obj);
1794 OnOffAuto vmport = pcms->vmport;
1795
1796 visit_type_OnOffAuto(v, name, &vmport, errp);
1797 }
1798
1799 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1800 void *opaque, Error **errp)
1801 {
1802 PCMachineState *pcms = PC_MACHINE(obj);
1803
1804 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1805 }
1806
1807 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1808 {
1809 PCMachineState *pcms = PC_MACHINE(obj);
1810
1811 return pcms->smbus_enabled;
1812 }
1813
1814 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1815 {
1816 PCMachineState *pcms = PC_MACHINE(obj);
1817
1818 pcms->smbus_enabled = value;
1819 }
1820
1821 static bool pc_machine_get_sata(Object *obj, Error **errp)
1822 {
1823 PCMachineState *pcms = PC_MACHINE(obj);
1824
1825 return pcms->sata_enabled;
1826 }
1827
1828 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1829 {
1830 PCMachineState *pcms = PC_MACHINE(obj);
1831
1832 pcms->sata_enabled = value;
1833 }
1834
1835 static bool pc_machine_get_pit(Object *obj, Error **errp)
1836 {
1837 PCMachineState *pcms = PC_MACHINE(obj);
1838
1839 return pcms->pit_enabled;
1840 }
1841
1842 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1843 {
1844 PCMachineState *pcms = PC_MACHINE(obj);
1845
1846 pcms->pit_enabled = value;
1847 }
1848
1849 static void pc_machine_initfn(Object *obj)
1850 {
1851 PCMachineState *pcms = PC_MACHINE(obj);
1852
1853 #ifdef CONFIG_VMPORT
1854 pcms->vmport = ON_OFF_AUTO_AUTO;
1855 #else
1856 pcms->vmport = ON_OFF_AUTO_OFF;
1857 #endif /* CONFIG_VMPORT */
1858 /* acpi build is enabled by default if machine supports it */
1859 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1860 pcms->smbus_enabled = true;
1861 pcms->sata_enabled = true;
1862 pcms->pit_enabled = true;
1863
1864 pc_system_flash_create(pcms);
1865 }
1866
1867 static void pc_machine_reset(MachineState *machine)
1868 {
1869 CPUState *cs;
1870 X86CPU *cpu;
1871
1872 qemu_devices_reset();
1873
1874 /* Reset APIC after devices have been reset to cancel
1875 * any changes that qemu_devices_reset() might have done.
1876 */
1877 CPU_FOREACH(cs) {
1878 cpu = X86_CPU(cs);
1879
1880 if (cpu->apic_state) {
1881 device_reset(cpu->apic_state);
1882 }
1883 }
1884 }
1885
1886 static void pc_machine_wakeup(MachineState *machine)
1887 {
1888 cpu_synchronize_all_states();
1889 pc_machine_reset(machine);
1890 cpu_synchronize_all_post_reset();
1891 }
1892
1893 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1894 {
1895 X86IOMMUState *iommu = x86_iommu_get_default();
1896 IntelIOMMUState *intel_iommu;
1897
1898 if (iommu &&
1899 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1900 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1901 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1902 if (!intel_iommu->caching_mode) {
1903 error_setg(errp, "Device assignment is not allowed without "
1904 "enabling caching-mode=on for Intel IOMMU.");
1905 return false;
1906 }
1907 }
1908
1909 return true;
1910 }
1911
1912 static void pc_machine_class_init(ObjectClass *oc, void *data)
1913 {
1914 MachineClass *mc = MACHINE_CLASS(oc);
1915 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1916 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1917
1918 pcmc->pci_enabled = true;
1919 pcmc->has_acpi_build = true;
1920 pcmc->rsdp_in_ram = true;
1921 pcmc->smbios_defaults = true;
1922 pcmc->smbios_uuid_encoded = true;
1923 pcmc->gigabyte_align = true;
1924 pcmc->has_reserved_memory = true;
1925 pcmc->kvmclock_enabled = true;
1926 pcmc->enforce_aligned_dimm = true;
1927 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1928 * to be used at the moment, 32K should be enough for a while. */
1929 pcmc->acpi_data_size = 0x20000 + 0x8000;
1930 pcmc->linuxboot_dma_enabled = true;
1931 pcmc->pvh_enabled = true;
1932 assert(!mc->get_hotplug_handler);
1933 mc->get_hotplug_handler = pc_get_hotplug_handler;
1934 mc->hotplug_allowed = pc_hotplug_allowed;
1935 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1936 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1937 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1938 mc->auto_enable_numa_with_memhp = true;
1939 mc->has_hotpluggable_cpus = true;
1940 mc->default_boot_order = "cad";
1941 mc->hot_add_cpu = pc_hot_add_cpu;
1942 mc->smp_parse = pc_smp_parse;
1943 mc->block_default_type = IF_IDE;
1944 mc->max_cpus = 255;
1945 mc->reset = pc_machine_reset;
1946 mc->wakeup = pc_machine_wakeup;
1947 hc->pre_plug = pc_machine_device_pre_plug_cb;
1948 hc->plug = pc_machine_device_plug_cb;
1949 hc->unplug_request = pc_machine_device_unplug_request_cb;
1950 hc->unplug = pc_machine_device_unplug_cb;
1951 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1952 mc->nvdimm_supported = true;
1953 mc->numa_mem_supported = true;
1954
1955 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1956 pc_machine_get_device_memory_region_size, NULL,
1957 NULL, NULL, &error_abort);
1958
1959 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1960 pc_machine_get_vmport, pc_machine_set_vmport,
1961 NULL, NULL, &error_abort);
1962 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1963 "Enable vmport (pc & q35)", &error_abort);
1964
1965 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1966 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
1967
1968 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1969 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
1970
1971 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1972 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
1973 }
1974
1975 static const TypeInfo pc_machine_info = {
1976 .name = TYPE_PC_MACHINE,
1977 .parent = TYPE_X86_MACHINE,
1978 .abstract = true,
1979 .instance_size = sizeof(PCMachineState),
1980 .instance_init = pc_machine_initfn,
1981 .class_size = sizeof(PCMachineClass),
1982 .class_init = pc_machine_class_init,
1983 .interfaces = (InterfaceInfo[]) {
1984 { TYPE_HOTPLUG_HANDLER },
1985 { }
1986 },
1987 };
1988
1989 static void pc_machine_register_types(void)
1990 {
1991 type_register_static(&pc_machine_info);
1992 }
1993
1994 type_init(pc_machine_register_types)
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