hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "sysemu/cpus.h"
  34 #include "hw/block/fdc.h"
  35 #include "hw/ide.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/timer/hpet.h"
  40 #include "hw/firmware/smbios.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "multiboot.h"
  44 #include "hw/timer/mc146818rtc.h"
  45 #include "hw/dma/i8257.h"
  46 #include "hw/timer/i8254.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/audio/pcspk.h"
  49 #include "hw/pci/msi.h"
  50 #include "hw/sysbus.h"
  51 #include "sysemu/sysemu.h"
  52 #include "sysemu/numa.h"
  53 #include "sysemu/kvm.h"
  54 #include "sysemu/qtest.h"
  55 #include "kvm_i386.h"
  56 #include "hw/xen/xen.h"
  57 #include "hw/xen/start_info.h"
  58 #include "ui/qemu-spice.h"
  59 #include "exec/memory.h"
  60 #include "exec/address-spaces.h"
  61 #include "sysemu/arch_init.h"
  62 #include "qemu/bitmap.h"
  63 #include "qemu/config-file.h"
  64 #include "qemu/error-report.h"
  65 #include "qemu/option.h"
  66 #include "hw/acpi/acpi.h"
  67 #include "hw/acpi/cpu_hotplug.h"
  68 #include "hw/boards.h"
  69 #include "acpi-build.h"
  70 #include "hw/mem/pc-dimm.h"
  71 #include "qapi/error.h"
  72 #include "qapi/qapi-visit-common.h"
  73 #include "qapi/visitor.h"
  74 #include "qom/cpu.h"
  75 #include "hw/nmi.h"
  76 #include "hw/usb.h"
  77 #include "hw/i386/intel_iommu.h"
  78 #include "hw/net/ne2000-isa.h"
  79
  80 /* debug PC/ISA interrupts */
  81 //#define DEBUG_IRQ
  82
  83 #ifdef DEBUG_IRQ
  84 #define DPRINTF(fmt, ...)                                       \
  85     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  86 #else
  87 #define DPRINTF(fmt, ...)
  88 #endif
  89
  90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  95
  96 #define E820_NR_ENTRIES         16
  97
  98 struct e820_entry {
  99     uint64_t address;
 100     uint64_t length;
 101     uint32_t type;
 102 } QEMU_PACKED __attribute((__aligned__(4)));
 103
 104 struct e820_table {
 105     uint32_t count;
 106     struct e820_entry entry[E820_NR_ENTRIES];
 107 } QEMU_PACKED __attribute((__aligned__(4)));
 108
 109 static struct e820_table e820_reserve;
 110 static struct e820_entry *e820_table;
 111 static unsigned e820_entries;
 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
 113
 114 /* Physical Address of PVH entry point read from kernel ELF NOTE */
 115 static size_t pvh_start_addr;
 116
 117 GlobalProperty pc_compat_3_1[] = {
 118     { "intel-iommu", "dma-drain", "off" },
 119     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
 120     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
 121     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
 122     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
 123     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
 124     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
 125     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
 126     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
 127     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
 128     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
 129     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
 130     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
 131     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
 132     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
 133     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
 134     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
 135     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
 136     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
 137     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
 138 };
 139 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
 140
 141 GlobalProperty pc_compat_3_0[] = {
 142     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
 143     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
 144     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
 145 };
 146 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
 147
 148 GlobalProperty pc_compat_2_12[] = {
 149     { TYPE_X86_CPU, "legacy-cache", "on" },
 150     { TYPE_X86_CPU, "topoext", "off" },
 151     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
 152     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
 153 };
 154 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
 155
 156 GlobalProperty pc_compat_2_11[] = {
 157     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
 158     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
 159 };
 160 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
 161
 162 GlobalProperty pc_compat_2_10[] = {
 163     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
 164     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
 165     { "q35-pcihost", "x-pci-hole64-fix", "off" },
 166 };
 167 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
 168
 169 GlobalProperty pc_compat_2_9[] = {
 170     { "mch", "extended-tseg-mbytes", "0" },
 171 };
 172 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
 173
 174 GlobalProperty pc_compat_2_8[] = {
 175     { TYPE_X86_CPU, "tcg-cpuid", "off" },
 176     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
 177     { "ICH9-LPC", "x-smi-broadcast", "off" },
 178     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
 179     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
 180 };
 181 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
 182
 183 GlobalProperty pc_compat_2_7[] = {
 184     { TYPE_X86_CPU, "l3-cache", "off" },
 185     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
 186     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
 187     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
 188     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
 189     { "isa-pcspk", "migrate", "off" },
 190 };
 191 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
 192
 193 GlobalProperty pc_compat_2_6[] = {
 194     { TYPE_X86_CPU, "cpuid-0xb", "off" },
 195     { "vmxnet3", "romfile", "" },
 196     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
 197     { "apic-common", "legacy-instance-id", "on", }
 198 };
 199 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
 200
 201 GlobalProperty pc_compat_2_5[] = {};
 202 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
 203
 204 GlobalProperty pc_compat_2_4[] = {
 205     PC_CPU_MODEL_IDS("2.4.0")
 206     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
 207     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
 208     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
 209     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
 210     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
 211     { TYPE_X86_CPU, "check", "off" },
 212     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
 213     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
 214     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
 215     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
 216     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
 217     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
 218     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
 219     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
 220 };
 221 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
 222
 223 GlobalProperty pc_compat_2_3[] = {
 224     PC_CPU_MODEL_IDS("2.3.0")
 225     { TYPE_X86_CPU, "arat", "off" },
 226     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
 227     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
 228     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
 229     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
 230     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
 231     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
 232     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
 233     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 234     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 235     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 236     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 237     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 238     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 239     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 240     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 241     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 242     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 243     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
 244     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
 245 };
 246 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
 247
 248 GlobalProperty pc_compat_2_2[] = {
 249     PC_CPU_MODEL_IDS("2.2.0")
 250     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
 251     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
 252     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
 253     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
 254     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
 255     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
 256     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
 257     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
 258     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
 259     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
 260     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
 261     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
 262     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
 263     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
 264     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
 265     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
 266     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
 267     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
 268 };
 269 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
 270
 271 GlobalProperty pc_compat_2_1[] = {
 272     PC_CPU_MODEL_IDS("2.1.0")
 273     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
 274     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
 275 };
 276 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
 277
 278 GlobalProperty pc_compat_2_0[] = {
 279     PC_CPU_MODEL_IDS("2.0.0")
 280     { "virtio-scsi-pci", "any_layout", "off" },
 281     { "PIIX4_PM", "memory-hotplug-support", "off" },
 282     { "apic", "version", "0x11" },
 283     { "nec-usb-xhci", "superspeed-ports-first", "off" },
 284     { "nec-usb-xhci", "force-pcie-endcap", "on" },
 285     { "pci-serial", "prog_if", "0" },
 286     { "pci-serial-2x", "prog_if", "0" },
 287     { "pci-serial-4x", "prog_if", "0" },
 288     { "virtio-net-pci", "guest_announce", "off" },
 289     { "ICH9-LPC", "memory-hotplug-support", "off" },
 290     { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
 291     { "ioh3420", COMPAT_PROP_PCP, "off" },
 292 };
 293 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
 294
 295 GlobalProperty pc_compat_1_7[] = {
 296     PC_CPU_MODEL_IDS("1.7.0")
 297     { TYPE_USB_DEVICE, "msos-desc", "no" },
 298     { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
 299     { "hpet", HPET_INTCAP, "4" },
 300 };
 301 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
 302
 303 GlobalProperty pc_compat_1_6[] = {
 304     PC_CPU_MODEL_IDS("1.6.0")
 305     { "e1000", "mitigation", "off" },
 306     { "qemu64-" TYPE_X86_CPU, "model", "2" },
 307     { "qemu32-" TYPE_X86_CPU, "model", "3" },
 308     { "i440FX-pcihost", "short_root_bus", "1" },
 309     { "q35-pcihost", "short_root_bus", "1" },
 310 };
 311 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
 312
 313 GlobalProperty pc_compat_1_5[] = {
 314     PC_CPU_MODEL_IDS("1.5.0")
 315     { "Conroe-" TYPE_X86_CPU, "model", "2" },
 316     { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
 317     { "Penryn-" TYPE_X86_CPU, "model", "2" },
 318     { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
 319     { "Nehalem-" TYPE_X86_CPU, "model", "2" },
 320     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
 321     { "virtio-net-pci", "any_layout", "off" },
 322     { TYPE_X86_CPU, "pmu", "on" },
 323     { "i440FX-pcihost", "short_root_bus", "0" },
 324     { "q35-pcihost", "short_root_bus", "0" },
 325 };
 326 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
 327
 328 GlobalProperty pc_compat_1_4[] = {
 329     PC_CPU_MODEL_IDS("1.4.0")
 330     { "scsi-hd", "discard_granularity", "0" },
 331     { "scsi-cd", "discard_granularity", "0" },
 332     { "scsi-disk", "discard_granularity", "0" },
 333     { "ide-hd", "discard_granularity", "0" },
 334     { "ide-cd", "discard_granularity", "0" },
 335     { "ide-drive", "discard_granularity", "0" },
 336     { "virtio-blk-pci", "discard_granularity", "0" },
 337     /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
 338     { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
 339     { "virtio-net-pci", "ctrl_guest_offloads", "off" },
 340     { "e1000", "romfile", "pxe-e1000.rom" },
 341     { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
 342     { "pcnet", "romfile", "pxe-pcnet.rom" },
 343     { "rtl8139", "romfile", "pxe-rtl8139.rom" },
 344     { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
 345     { "486-" TYPE_X86_CPU, "model", "0" },
 346     { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
 347     { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
 348 };
 349 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
 350
 351 void gsi_handler(void *opaque, int n, int level)
 352 {
 353     GSIState *s = opaque;
 354
 355     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 356     if (n < ISA_NUM_IRQS) {
 357         qemu_set_irq(s->i8259_irq[n], level);
 358     }
 359     qemu_set_irq(s->ioapic_irq[n], level);
 360 }
 361
 362 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 363                            unsigned size)
 364 {
 365 }
 366
 367 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 368 {
 369     return 0xffffffffffffffffULL;
 370 }
 371
 372 /* MSDOS compatibility mode FPU exception support */
 373 static qemu_irq ferr_irq;
 374
 375 void pc_register_ferr_irq(qemu_irq irq)
 376 {
 377     ferr_irq = irq;
 378 }
 379
 380 /* XXX: add IGNNE support */
 381 void cpu_set_ferr(CPUX86State *s)
 382 {
 383     qemu_irq_raise(ferr_irq);
 384 }
 385
 386 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 387                            unsigned size)
 388 {
 389     qemu_irq_lower(ferr_irq);
 390 }
 391
 392 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 393 {
 394     return 0xffffffffffffffffULL;
 395 }
 396
 397 /* TSC handling */
 398 uint64_t cpu_get_tsc(CPUX86State *env)
 399 {
 400     return cpu_get_ticks();
 401 }
 402
 403 /* IRQ handling */
 404 int cpu_get_pic_interrupt(CPUX86State *env)
 405 {
 406     X86CPU *cpu = x86_env_get_cpu(env);
 407     int intno;
 408
 409     if (!kvm_irqchip_in_kernel()) {
 410         intno = apic_get_interrupt(cpu->apic_state);
 411         if (intno >= 0) {
 412             return intno;
 413         }
 414         /* read the irq from the PIC */
 415         if (!apic_accept_pic_intr(cpu->apic_state)) {
 416             return -1;
 417         }
 418     }
 419
 420     intno = pic_read_irq(isa_pic);
 421     return intno;
 422 }
 423
 424 static void pic_irq_request(void *opaque, int irq, int level)
 425 {
 426     CPUState *cs = first_cpu;
 427     X86CPU *cpu = X86_CPU(cs);
 428
 429     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 430     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 431         CPU_FOREACH(cs) {
 432             cpu = X86_CPU(cs);
 433             if (apic_accept_pic_intr(cpu->apic_state)) {
 434                 apic_deliver_pic_intr(cpu->apic_state, level);
 435             }
 436         }
 437     } else {
 438         if (level) {
 439             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 440         } else {
 441             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 442         }
 443     }
 444 }
 445
 446 /* PC cmos mappings */
 447
 448 #define REG_EQUIPMENT_BYTE          0x14
 449
 450 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 451 {
 452     int val;
 453
 454     switch (fd0) {
 455     case FLOPPY_DRIVE_TYPE_144:
 456         /* 1.44 Mb 3"5 drive */
 457         val = 4;
 458         break;
 459     case FLOPPY_DRIVE_TYPE_288:
 460         /* 2.88 Mb 3"5 drive */
 461         val = 5;
 462         break;
 463     case FLOPPY_DRIVE_TYPE_120:
 464         /* 1.2 Mb 5"5 drive */
 465         val = 2;
 466         break;
 467     case FLOPPY_DRIVE_TYPE_NONE:
 468     default:
 469         val = 0;
 470         break;
 471     }
 472     return val;
 473 }
 474
 475 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 476                          int16_t cylinders, int8_t heads, int8_t sectors)
 477 {
 478     rtc_set_memory(s, type_ofs, 47);
 479     rtc_set_memory(s, info_ofs, cylinders);
 480     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 481     rtc_set_memory(s, info_ofs + 2, heads);
 482     rtc_set_memory(s, info_ofs + 3, 0xff);
 483     rtc_set_memory(s, info_ofs + 4, 0xff);
 484     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 485     rtc_set_memory(s, info_ofs + 6, cylinders);
 486     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 487     rtc_set_memory(s, info_ofs + 8, sectors);
 488 }
 489
 490 /* convert boot_device letter to something recognizable by the bios */
 491 static int boot_device2nibble(char boot_device)
 492 {
 493     switch(boot_device) {
 494     case 'a':
 495     case 'b':
 496         return 0x01; /* floppy boot */
 497     case 'c':
 498         return 0x02; /* hard drive boot */
 499     case 'd':
 500         return 0x03; /* CD-ROM boot */
 501     case 'n':
 502         return 0x04; /* Network boot */
 503     }
 504     return 0;
 505 }
 506
 507 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 508 {
 509 #define PC_MAX_BOOT_DEVICES 3
 510     int nbds, bds[3] = { 0, };
 511     int i;
 512
 513     nbds = strlen(boot_device);
 514     if (nbds > PC_MAX_BOOT_DEVICES) {
 515         error_setg(errp, "Too many boot devices for PC");
 516         return;
 517     }
 518     for (i = 0; i < nbds; i++) {
 519         bds[i] = boot_device2nibble(boot_device[i]);
 520         if (bds[i] == 0) {
 521             error_setg(errp, "Invalid boot device for PC: '%c'",
 522                        boot_device[i]);
 523             return;
 524         }
 525     }
 526     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 527     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 528 }
 529
 530 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 531 {
 532     set_boot_dev(opaque, boot_device, errp);
 533 }
 534
 535 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 536 {
 537     int val, nb, i;
 538     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 539                                    FLOPPY_DRIVE_TYPE_NONE };
 540
 541     /* floppy type */
 542     if (floppy) {
 543         for (i = 0; i < 2; i++) {
 544             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 545         }
 546     }
 547     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 548         cmos_get_fd_drive_type(fd_type[1]);
 549     rtc_set_memory(rtc_state, 0x10, val);
 550
 551     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 552     nb = 0;
 553     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 554         nb++;
 555     }
 556     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 557         nb++;
 558     }
 559     switch (nb) {
 560     case 0:
 561         break;
 562     case 1:
 563         val |= 0x01; /* 1 drive, ready for boot */
 564         break;
 565     case 2:
 566         val |= 0x41; /* 2 drives, ready for boot */
 567         break;
 568     }
 569     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 570 }
 571
 572 typedef struct pc_cmos_init_late_arg {
 573     ISADevice *rtc_state;
 574     BusState *idebus[2];
 575 } pc_cmos_init_late_arg;
 576
 577 typedef struct check_fdc_state {
 578     ISADevice *floppy;
 579     bool multiple;
 580 } CheckFdcState;
 581
 582 static int check_fdc(Object *obj, void *opaque)
 583 {
 584     CheckFdcState *state = opaque;
 585     Object *fdc;
 586     uint32_t iobase;
 587     Error *local_err = NULL;
 588
 589     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 590     if (!fdc) {
 591         return 0;
 592     }
 593
 594     iobase = object_property_get_uint(obj, "iobase", &local_err);
 595     if (local_err || iobase != 0x3f0) {
 596         error_free(local_err);
 597         return 0;
 598     }
 599
 600     if (state->floppy) {
 601         state->multiple = true;
 602     } else {
 603         state->floppy = ISA_DEVICE(obj);
 604     }
 605     return 0;
 606 }
 607
 608 static const char * const fdc_container_path[] = {
 609     "/unattached", "/peripheral", "/peripheral-anon"
 610 };
 611
 612 /*
 613  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 614  * and ACPI objects.
 615  */
 616 ISADevice *pc_find_fdc0(void)
 617 {
 618     int i;
 619     Object *container;
 620     CheckFdcState state = { 0 };
 621
 622     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 623         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 624         object_child_foreach(container, check_fdc, &state);
 625     }
 626
 627     if (state.multiple) {
 628         warn_report("multiple floppy disk controllers with "
 629                     "iobase=0x3f0 have been found");
 630         error_printf("the one being picked for CMOS setup might not reflect "
 631                      "your intent");
 632     }
 633
 634     return state.floppy;
 635 }
 636
 637 static void pc_cmos_init_late(void *opaque)
 638 {
 639     pc_cmos_init_late_arg *arg = opaque;
 640     ISADevice *s = arg->rtc_state;
 641     int16_t cylinders;
 642     int8_t heads, sectors;
 643     int val;
 644     int i, trans;
 645
 646     val = 0;
 647     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 648                                            &cylinders, &heads, &sectors) >= 0) {
 649         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 650         val |= 0xf0;
 651     }
 652     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 653                                            &cylinders, &heads, &sectors) >= 0) {
 654         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 655         val |= 0x0f;
 656     }
 657     rtc_set_memory(s, 0x12, val);
 658
 659     val = 0;
 660     for (i = 0; i < 4; i++) {
 661         /* NOTE: ide_get_geometry() returns the physical
 662            geometry.  It is always such that: 1 <= sects <= 63, 1
 663            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 664            geometry can be different if a translation is done. */
 665         if (arg->idebus[i / 2] &&
 666             ide_get_geometry(arg->idebus[i / 2], i % 2,
 667                              &cylinders, &heads, &sectors) >= 0) {
 668             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 669             assert((trans & ~3) == 0);
 670             val |= trans << (i * 2);
 671         }
 672     }
 673     rtc_set_memory(s, 0x39, val);
 674
 675     pc_cmos_init_floppy(s, pc_find_fdc0());
 676
 677     qemu_unregister_reset(pc_cmos_init_late, opaque);
 678 }
 679
 680 void pc_cmos_init(PCMachineState *pcms,
 681                   BusState *idebus0, BusState *idebus1,
 682                   ISADevice *s)
 683 {
 684     int val;
 685     static pc_cmos_init_late_arg arg;
 686
 687     /* various important CMOS locations needed by PC/Bochs bios */
 688
 689     /* memory size */
 690     /* base memory (first MiB) */
 691     val = MIN(pcms->below_4g_mem_size / KiB, 640);
 692     rtc_set_memory(s, 0x15, val);
 693     rtc_set_memory(s, 0x16, val >> 8);
 694     /* extended memory (next 64MiB) */
 695     if (pcms->below_4g_mem_size > 1 * MiB) {
 696         val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
 697     } else {
 698         val = 0;
 699     }
 700     if (val > 65535)
 701         val = 65535;
 702     rtc_set_memory(s, 0x17, val);
 703     rtc_set_memory(s, 0x18, val >> 8);
 704     rtc_set_memory(s, 0x30, val);
 705     rtc_set_memory(s, 0x31, val >> 8);
 706     /* memory between 16MiB and 4GiB */
 707     if (pcms->below_4g_mem_size > 16 * MiB) {
 708         val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 709     } else {
 710         val = 0;
 711     }
 712     if (val > 65535)
 713         val = 65535;
 714     rtc_set_memory(s, 0x34, val);
 715     rtc_set_memory(s, 0x35, val >> 8);
 716     /* memory above 4GiB */
 717     val = pcms->above_4g_mem_size / 65536;
 718     rtc_set_memory(s, 0x5b, val);
 719     rtc_set_memory(s, 0x5c, val >> 8);
 720     rtc_set_memory(s, 0x5d, val >> 16);
 721
 722     object_property_add_link(OBJECT(pcms), "rtc_state",
 723                              TYPE_ISA_DEVICE,
 724                              (Object **)&pcms->rtc,
 725                              object_property_allow_set_link,
 726                              OBJ_PROP_LINK_STRONG, &error_abort);
 727     object_property_set_link(OBJECT(pcms), OBJECT(s),
 728                              "rtc_state", &error_abort);
 729
 730     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 731
 732     val = 0;
 733     val |= 0x02; /* FPU is there */
 734     val |= 0x04; /* PS/2 mouse installed */
 735     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 736
 737     /* hard drives and FDC */
 738     arg.rtc_state = s;
 739     arg.idebus[0] = idebus0;
 740     arg.idebus[1] = idebus1;
 741     qemu_register_reset(pc_cmos_init_late, &arg);
 742 }
 743
 744 #define TYPE_PORT92 "port92"
 745 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 746
 747 /* port 92 stuff: could be split off */
 748 typedef struct Port92State {
 749     ISADevice parent_obj;
 750
 751     MemoryRegion io;
 752     uint8_t outport;
 753     qemu_irq a20_out;
 754 } Port92State;
 755
 756 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 757                          unsigned size)
 758 {
 759     Port92State *s = opaque;
 760     int oldval = s->outport;
 761
 762     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
 763     s->outport = val;
 764     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 765     if ((val & 1) && !(oldval & 1)) {
 766         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 767     }
 768 }
 769
 770 static uint64_t port92_read(void *opaque, hwaddr addr,
 771                             unsigned size)
 772 {
 773     Port92State *s = opaque;
 774     uint32_t ret;
 775
 776     ret = s->outport;
 777     DPRINTF("port92: read 0x%02x\n", ret);
 778     return ret;
 779 }
 780
 781 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 782 {
 783     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 784 }
 785
 786 static const VMStateDescription vmstate_port92_isa = {
 787     .name = "port92",
 788     .version_id = 1,
 789     .minimum_version_id = 1,
 790     .fields = (VMStateField[]) {
 791         VMSTATE_UINT8(outport, Port92State),
 792         VMSTATE_END_OF_LIST()
 793     }
 794 };
 795
 796 static void port92_reset(DeviceState *d)
 797 {
 798     Port92State *s = PORT92(d);
 799
 800     s->outport &= ~1;
 801 }
 802
 803 static const MemoryRegionOps port92_ops = {
 804     .read = port92_read,
 805     .write = port92_write,
 806     .impl = {
 807         .min_access_size = 1,
 808         .max_access_size = 1,
 809     },
 810     .endianness = DEVICE_LITTLE_ENDIAN,
 811 };
 812
 813 static void port92_initfn(Object *obj)
 814 {
 815     Port92State *s = PORT92(obj);
 816
 817     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 818
 819     s->outport = 0;
 820
 821     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 822 }
 823
 824 static void port92_realizefn(DeviceState *dev, Error **errp)
 825 {
 826     ISADevice *isadev = ISA_DEVICE(dev);
 827     Port92State *s = PORT92(dev);
 828
 829     isa_register_ioport(isadev, &s->io, 0x92);
 830 }
 831
 832 static void port92_class_initfn(ObjectClass *klass, void *data)
 833 {
 834     DeviceClass *dc = DEVICE_CLASS(klass);
 835
 836     dc->realize = port92_realizefn;
 837     dc->reset = port92_reset;
 838     dc->vmsd = &vmstate_port92_isa;
 839     /*
 840      * Reason: unlike ordinary ISA devices, this one needs additional
 841      * wiring: its A20 output line needs to be wired up by
 842      * port92_init().
 843      */
 844     dc->user_creatable = false;
 845 }
 846
 847 static const TypeInfo port92_info = {
 848     .name          = TYPE_PORT92,
 849     .parent        = TYPE_ISA_DEVICE,
 850     .instance_size = sizeof(Port92State),
 851     .instance_init = port92_initfn,
 852     .class_init    = port92_class_initfn,
 853 };
 854
 855 static void port92_register_types(void)
 856 {
 857     type_register_static(&port92_info);
 858 }
 859
 860 type_init(port92_register_types)
 861
 862 static void handle_a20_line_change(void *opaque, int irq, int level)
 863 {
 864     X86CPU *cpu = opaque;
 865
 866     /* XXX: send to all CPUs ? */
 867     /* XXX: add logic to handle multiple A20 line sources */
 868     x86_cpu_set_a20(cpu, level);
 869 }
 870
 871 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 872 {
 873     int index = le32_to_cpu(e820_reserve.count);
 874     struct e820_entry *entry;
 875
 876     if (type != E820_RAM) {
 877         /* old FW_CFG_E820_TABLE entry -- reservations only */
 878         if (index >= E820_NR_ENTRIES) {
 879             return -EBUSY;
 880         }
 881         entry = &e820_reserve.entry[index++];
 882
 883         entry->address = cpu_to_le64(address);
 884         entry->length = cpu_to_le64(length);
 885         entry->type = cpu_to_le32(type);
 886
 887         e820_reserve.count = cpu_to_le32(index);
 888     }
 889
 890     /* new "etc/e820" file -- include ram too */
 891     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
 892     e820_table[e820_entries].address = cpu_to_le64(address);
 893     e820_table[e820_entries].length = cpu_to_le64(length);
 894     e820_table[e820_entries].type = cpu_to_le32(type);
 895     e820_entries++;
 896
 897     return e820_entries;
 898 }
 899
 900 int e820_get_num_entries(void)
 901 {
 902     return e820_entries;
 903 }
 904
 905 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
 906 {
 907     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
 908         *address = le64_to_cpu(e820_table[idx].address);
 909         *length = le64_to_cpu(e820_table[idx].length);
 910         return true;
 911     }
 912     return false;
 913 }
 914
 915 /* Enables contiguous-apic-ID mode, for compatibility */
 916 static bool compat_apic_id_mode;
 917
 918 void enable_compat_apic_id_mode(void)
 919 {
 920     compat_apic_id_mode = true;
 921 }
 922
 923 /* Calculates initial APIC ID for a specific CPU index
 924  *
 925  * Currently we need to be able to calculate the APIC ID from the CPU index
 926  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
 927  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
 928  * all CPUs up to max_cpus.
 929  */
 930 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
 931 {
 932     uint32_t correct_id;
 933     static bool warned;
 934
 935     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
 936     if (compat_apic_id_mode) {
 937         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
 938             error_report("APIC IDs set in compatibility mode, "
 939                          "CPU topology won't match the configuration");
 940             warned = true;
 941         }
 942         return cpu_index;
 943     } else {
 944         return correct_id;
 945     }
 946 }
 947
 948 static void pc_build_smbios(PCMachineState *pcms)
 949 {
 950     uint8_t *smbios_tables, *smbios_anchor;
 951     size_t smbios_tables_len, smbios_anchor_len;
 952     struct smbios_phys_mem_area *mem_array;
 953     unsigned i, array_count;
 954     MachineState *ms = MACHINE(pcms);
 955     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 956
 957     /* tell smbios about cpuid version and features */
 958     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 959
 960     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
 961     if (smbios_tables) {
 962         fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 963                          smbios_tables, smbios_tables_len);
 964     }
 965
 966     /* build the array of physical mem area from e820 table */
 967     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
 968     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
 969         uint64_t addr, len;
 970
 971         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
 972             mem_array[array_count].address = addr;
 973             mem_array[array_count].length = len;
 974             array_count++;
 975         }
 976     }
 977     smbios_get_tables(mem_array, array_count,
 978                       &smbios_tables, &smbios_tables_len,
 979                       &smbios_anchor, &smbios_anchor_len);
 980     g_free(mem_array);
 981
 982     if (smbios_anchor) {
 983         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
 984                         smbios_tables, smbios_tables_len);
 985         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
 986                         smbios_anchor, smbios_anchor_len);
 987     }
 988 }
 989
 990 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
 991 {
 992     FWCfgState *fw_cfg;
 993     uint64_t *numa_fw_cfg;
 994     int i;
 995     const CPUArchIdList *cpus;
 996     MachineClass *mc = MACHINE_GET_CLASS(pcms);
 997
 998     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
 999     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1000
1001     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1002      *
1003      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1004      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1005      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1006      * for CPU hotplug also uses APIC ID and not "CPU index".
1007      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1008      * but the "limit to the APIC ID values SeaBIOS may see".
1009      *
1010      * So for compatibility reasons with old BIOSes we are stuck with
1011      * "etc/max-cpus" actually being apic_id_limit
1012      */
1013     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
1014     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1015     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1016                      acpi_tables, acpi_tables_len);
1017     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
1018
1019     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
1020                      &e820_reserve, sizeof(e820_reserve));
1021     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1022                     sizeof(struct e820_entry) * e820_entries);
1023
1024     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
1025     /* allocate memory for the NUMA channel: one (64bit) word for the number
1026      * of nodes, one word for each VCPU->node and one word for each node to
1027      * hold the amount of memory.
1028      */
1029     numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
1030     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
1031     cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1032     for (i = 0; i < cpus->len; i++) {
1033         unsigned int apic_id = cpus->cpus[i].arch_id;
1034         assert(apic_id < pcms->apic_id_limit);
1035         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
1036     }
1037     for (i = 0; i < nb_numa_nodes; i++) {
1038         numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1039             cpu_to_le64(numa_info[i].node_mem);
1040     }
1041     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
1042                      (1 + pcms->apic_id_limit + nb_numa_nodes) *
1043                      sizeof(*numa_fw_cfg));
1044
1045     return fw_cfg;
1046 }
1047
1048 static long get_file_size(FILE *f)
1049 {
1050     long where, size;
1051
1052     /* XXX: on Unix systems, using fstat() probably makes more sense */
1053
1054     where = ftell(f);
1055     fseek(f, 0, SEEK_END);
1056     size = ftell(f);
1057     fseek(f, where, SEEK_SET);
1058
1059     return size;
1060 }
1061
1062 /* setup_data types */
1063 #define SETUP_NONE     0
1064 #define SETUP_E820_EXT 1
1065 #define SETUP_DTB      2
1066 #define SETUP_PCI      3
1067 #define SETUP_EFI      4
1068
1069 struct setup_data {
1070     uint64_t next;
1071     uint32_t type;
1072     uint32_t len;
1073     uint8_t data[0];
1074 } __attribute__((packed));
1075
1076
1077 /*
1078  * The entry point into the kernel for PVH boot is different from
1079  * the native entry point.  The PVH entry is defined by the x86/HVM
1080  * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1081  *
1082  * This function is passed to load_elf() when it is called from
1083  * load_elfboot() which then additionally checks for an ELF Note of
1084  * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1085  * parse the PVH entry address from the ELF Note.
1086  *
1087  * Due to trickery in elf_opts.h, load_elf() is actually available as
1088  * load_elf32() or load_elf64() and this routine needs to be able
1089  * to deal with being called as 32 or 64 bit.
1090  *
1091  * The address of the PVH entry point is saved to the 'pvh_start_addr'
1092  * global variable.  (although the entry point is 32-bit, the kernel
1093  * binary can be either 32-bit or 64-bit).
1094  */
1095 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1096 {
1097     size_t *elf_note_data_addr;
1098
1099     /* Check if ELF Note header passed in is valid */
1100     if (arg1 == NULL) {
1101         return 0;
1102     }
1103
1104     if (is64) {
1105         struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1106         uint64_t nhdr_size64 = sizeof(struct elf64_note);
1107         uint64_t phdr_align = *(uint64_t *)arg2;
1108         uint64_t nhdr_namesz = nhdr64->n_namesz;
1109
1110         elf_note_data_addr =
1111             ((void *)nhdr64) + nhdr_size64 +
1112             QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1113     } else {
1114         struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1115         uint32_t nhdr_size32 = sizeof(struct elf32_note);
1116         uint32_t phdr_align = *(uint32_t *)arg2;
1117         uint32_t nhdr_namesz = nhdr32->n_namesz;
1118
1119         elf_note_data_addr =
1120             ((void *)nhdr32) + nhdr_size32 +
1121             QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1122     }
1123
1124     pvh_start_addr = *elf_note_data_addr;
1125
1126     return pvh_start_addr;
1127 }
1128
1129 static bool load_elfboot(const char *kernel_filename,
1130                    int kernel_file_size,
1131                    uint8_t *header,
1132                    size_t pvh_xen_start_addr,
1133                    FWCfgState *fw_cfg)
1134 {
1135     uint32_t flags = 0;
1136     uint32_t mh_load_addr = 0;
1137     uint32_t elf_kernel_size = 0;
1138     uint64_t elf_entry;
1139     uint64_t elf_low, elf_high;
1140     int kernel_size;
1141
1142     if (ldl_p(header) != 0x464c457f) {
1143         return false; /* no elfboot */
1144     }
1145
1146     bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1147     flags = elf_is64 ?
1148         ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1149
1150     if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1151         error_report("elfboot unsupported flags = %x", flags);
1152         exit(1);
1153     }
1154
1155     uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1156     kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1157                            NULL, &elf_note_type, &elf_entry,
1158                            &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1159                            0, 0);
1160
1161     if (kernel_size < 0) {
1162         error_report("Error while loading elf kernel");
1163         exit(1);
1164     }
1165     mh_load_addr = elf_low;
1166     elf_kernel_size = elf_high - elf_low;
1167
1168     if (pvh_start_addr == 0) {
1169         error_report("Error loading uncompressed kernel without PVH ELF Note");
1170         exit(1);
1171     }
1172     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1173     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1174     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1175
1176     return true;
1177 }
1178
1179 static void load_linux(PCMachineState *pcms,
1180                        FWCfgState *fw_cfg)
1181 {
1182     uint16_t protocol;
1183     int setup_size, kernel_size, cmdline_size;
1184     int dtb_size, setup_data_offset;
1185     uint32_t initrd_max;
1186     uint8_t header[8192], *setup, *kernel;
1187     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1188     FILE *f;
1189     char *vmode;
1190     MachineState *machine = MACHINE(pcms);
1191     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1192     struct setup_data *setup_data;
1193     const char *kernel_filename = machine->kernel_filename;
1194     const char *initrd_filename = machine->initrd_filename;
1195     const char *dtb_filename = machine->dtb;
1196     const char *kernel_cmdline = machine->kernel_cmdline;
1197
1198     /* Align to 16 bytes as a paranoia measure */
1199     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1200
1201     /* load the kernel header */
1202     f = fopen(kernel_filename, "rb");
1203     if (!f || !(kernel_size = get_file_size(f)) ||
1204         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1205         MIN(ARRAY_SIZE(header), kernel_size)) {
1206         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1207                 kernel_filename, strerror(errno));
1208         exit(1);
1209     }
1210
1211     /* kernel protocol version */
1212 #if 0
1213     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
1214 #endif
1215     if (ldl_p(header+0x202) == 0x53726448) {
1216         protocol = lduw_p(header+0x206);
1217     } else {
1218         /*
1219          * Check if the file is an uncompressed kernel file (ELF) and load it,
1220          * saving the PVH entry point used by the x86/HVM direct boot ABI.
1221          * If load_elfboot() is successful, populate the fw_cfg info.
1222          */
1223         if (load_elfboot(kernel_filename, kernel_size,
1224                          header, pvh_start_addr, fw_cfg)) {
1225             struct hvm_modlist_entry ramdisk_mod = { 0 };
1226
1227             fclose(f);
1228
1229             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1230                 strlen(kernel_cmdline) + 1);
1231             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1232
1233             assert(machine->device_memory != NULL);
1234             ramdisk_mod.paddr = machine->device_memory->base;
1235             ramdisk_mod.size =
1236                 memory_region_size(&machine->device_memory->mr);
1237
1238             fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, &ramdisk_mod,
1239                              sizeof(ramdisk_mod));
1240             fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1241             fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1242                              header, sizeof(header));
1243
1244             return;
1245         }
1246         /* This looks like a multiboot kernel. If it is, let's stop
1247            treating it like a Linux kernel. */
1248         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1249                            kernel_cmdline, kernel_size, header)) {
1250             return;
1251         }
1252         protocol = 0;
1253     }
1254
1255     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
1256         /* Low kernel */
1257         real_addr    = 0x90000;
1258         cmdline_addr = 0x9a000 - cmdline_size;
1259         prot_addr    = 0x10000;
1260     } else if (protocol < 0x202) {
1261         /* High but ancient kernel */
1262         real_addr    = 0x90000;
1263         cmdline_addr = 0x9a000 - cmdline_size;
1264         prot_addr    = 0x100000;
1265     } else {
1266         /* High and recent kernel */
1267         real_addr    = 0x10000;
1268         cmdline_addr = 0x20000;
1269         prot_addr    = 0x100000;
1270     }
1271
1272 #if 0
1273     fprintf(stderr,
1274             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
1275             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
1276             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
1277             real_addr,
1278             cmdline_addr,
1279             prot_addr);
1280 #endif
1281
1282     /* highest address for loading the initrd */
1283     if (protocol >= 0x203) {
1284         initrd_max = ldl_p(header+0x22c);
1285     } else {
1286         initrd_max = 0x37ffffff;
1287     }
1288
1289     if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1290         initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1291     }
1292
1293     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1294     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
1295     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1296
1297     if (protocol >= 0x202) {
1298         stl_p(header+0x228, cmdline_addr);
1299     } else {
1300         stw_p(header+0x20, 0xA33F);
1301         stw_p(header+0x22, cmdline_addr-real_addr);
1302     }
1303
1304     /* handle vga= parameter */
1305     vmode = strstr(kernel_cmdline, "vga=");
1306     if (vmode) {
1307         unsigned int video_mode;
1308         /* skip "vga=" */
1309         vmode += 4;
1310         if (!strncmp(vmode, "normal", 6)) {
1311             video_mode = 0xffff;
1312         } else if (!strncmp(vmode, "ext", 3)) {
1313             video_mode = 0xfffe;
1314         } else if (!strncmp(vmode, "ask", 3)) {
1315             video_mode = 0xfffd;
1316         } else {
1317             video_mode = strtol(vmode, NULL, 0);
1318         }
1319         stw_p(header+0x1fa, video_mode);
1320     }
1321
1322     /* loader type */
1323     /* High nybble = B reserved for QEMU; low nybble is revision number.
1324        If this code is substantially changed, you may want to consider
1325        incrementing the revision. */
1326     if (protocol >= 0x200) {
1327         header[0x210] = 0xB0;
1328     }
1329     /* heap */
1330     if (protocol >= 0x201) {
1331         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
1332         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1333     }
1334
1335     /* load initrd */
1336     if (initrd_filename) {
1337         gsize initrd_size;
1338         gchar *initrd_data;
1339         GError *gerr = NULL;
1340
1341         if (protocol < 0x200) {
1342             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1343             exit(1);
1344         }
1345
1346         if (!g_file_get_contents(initrd_filename, &initrd_data,
1347                                  &initrd_size, &gerr)) {
1348             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1349                     initrd_filename, gerr->message);
1350             exit(1);
1351         }
1352         if (initrd_size >= initrd_max) {
1353             fprintf(stderr, "qemu: initrd is too large, cannot support."
1354                     "(max: %"PRIu32", need %"PRId64")\n",
1355                     initrd_max, (uint64_t)initrd_size);
1356             exit(1);
1357         }
1358
1359         initrd_addr = (initrd_max-initrd_size) & ~4095;
1360
1361         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1362         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1363         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1364
1365         stl_p(header+0x218, initrd_addr);
1366         stl_p(header+0x21c, initrd_size);
1367     }
1368
1369     /* load kernel and setup */
1370     setup_size = header[0x1f1];
1371     if (setup_size == 0) {
1372         setup_size = 4;
1373     }
1374     setup_size = (setup_size+1)*512;
1375     if (setup_size > kernel_size) {
1376         fprintf(stderr, "qemu: invalid kernel header\n");
1377         exit(1);
1378     }
1379     kernel_size -= setup_size;
1380
1381     setup  = g_malloc(setup_size);
1382     kernel = g_malloc(kernel_size);
1383     fseek(f, 0, SEEK_SET);
1384     if (fread(setup, 1, setup_size, f) != setup_size) {
1385         fprintf(stderr, "fread() failed\n");
1386         exit(1);
1387     }
1388     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1389         fprintf(stderr, "fread() failed\n");
1390         exit(1);
1391     }
1392     fclose(f);
1393
1394     /* append dtb to kernel */
1395     if (dtb_filename) {
1396         if (protocol < 0x209) {
1397             fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1398             exit(1);
1399         }
1400
1401         dtb_size = get_image_size(dtb_filename);
1402         if (dtb_size <= 0) {
1403             fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1404                     dtb_filename, strerror(errno));
1405             exit(1);
1406         }
1407
1408         setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1409         kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1410         kernel = g_realloc(kernel, kernel_size);
1411
1412         stq_p(header+0x250, prot_addr + setup_data_offset);
1413
1414         setup_data = (struct setup_data *)(kernel + setup_data_offset);
1415         setup_data->next = 0;
1416         setup_data->type = cpu_to_le32(SETUP_DTB);
1417         setup_data->len = cpu_to_le32(dtb_size);
1418
1419         load_image_size(dtb_filename, setup_data->data, dtb_size);
1420     }
1421
1422     memcpy(setup, header, MIN(sizeof(header), setup_size));
1423
1424     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1425     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1426     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1427
1428     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1429     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1430     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1431
1432     option_rom[nb_option_roms].bootindex = 0;
1433     option_rom[nb_option_roms].name = "linuxboot.bin";
1434     if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1435         option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1436     }
1437     nb_option_roms++;
1438 }
1439
1440 #define NE2000_NB_MAX 6
1441
1442 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1443                                               0x280, 0x380 };
1444 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1445
1446 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1447 {
1448     static int nb_ne2k = 0;
1449
1450     if (nb_ne2k == NE2000_NB_MAX)
1451         return;
1452     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1453                     ne2000_irq[nb_ne2k], nd);
1454     nb_ne2k++;
1455 }
1456
1457 DeviceState *cpu_get_current_apic(void)
1458 {
1459     if (current_cpu) {
1460         X86CPU *cpu = X86_CPU(current_cpu);
1461         return cpu->apic_state;
1462     } else {
1463         return NULL;
1464     }
1465 }
1466
1467 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1468 {
1469     X86CPU *cpu = opaque;
1470
1471     if (level) {
1472         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1473     }
1474 }
1475
1476 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1477 {
1478     Object *cpu = NULL;
1479     Error *local_err = NULL;
1480
1481     cpu = object_new(typename);
1482
1483     object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1484     object_property_set_bool(cpu, true, "realized", &local_err);
1485
1486     object_unref(cpu);
1487     error_propagate(errp, local_err);
1488 }
1489
1490 void pc_hot_add_cpu(const int64_t id, Error **errp)
1491 {
1492     MachineState *ms = MACHINE(qdev_get_machine());
1493     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1494     Error *local_err = NULL;
1495
1496     if (id < 0) {
1497         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1498         return;
1499     }
1500
1501     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1502         error_setg(errp, "Unable to add CPU: %" PRIi64
1503                    ", resulting APIC ID (%" PRIi64 ") is too large",
1504                    id, apic_id);
1505         return;
1506     }
1507
1508     pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1509     if (local_err) {
1510         error_propagate(errp, local_err);
1511         return;
1512     }
1513 }
1514
1515 void pc_cpus_init(PCMachineState *pcms)
1516 {
1517     int i;
1518     const CPUArchIdList *possible_cpus;
1519     MachineState *ms = MACHINE(pcms);
1520     MachineClass *mc = MACHINE_GET_CLASS(pcms);
1521
1522     /* Calculates the limit to CPU APIC ID values
1523      *
1524      * Limit for the APIC ID value, so that all
1525      * CPU APIC IDs are < pcms->apic_id_limit.
1526      *
1527      * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1528      */
1529     pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1530     possible_cpus = mc->possible_cpu_arch_ids(ms);
1531     for (i = 0; i < smp_cpus; i++) {
1532         pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1533                    &error_fatal);
1534     }
1535 }
1536
1537 static void pc_build_feature_control_file(PCMachineState *pcms)
1538 {
1539     MachineState *ms = MACHINE(pcms);
1540     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1541     CPUX86State *env = &cpu->env;
1542     uint32_t unused, ecx, edx;
1543     uint64_t feature_control_bits = 0;
1544     uint64_t *val;
1545
1546     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1547     if (ecx & CPUID_EXT_VMX) {
1548         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1549     }
1550
1551     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1552         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1553         (env->mcg_cap & MCG_LMCE_P)) {
1554         feature_control_bits |= FEATURE_CONTROL_LMCE;
1555     }
1556
1557     if (!feature_control_bits) {
1558         return;
1559     }
1560
1561     val = g_malloc(sizeof(*val));
1562     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1563     fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1564 }
1565
1566 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1567 {
1568     if (cpus_count > 0xff) {
1569         /* If the number of CPUs can't be represented in 8 bits, the
1570          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1571          * to make old BIOSes fail more predictably.
1572          */
1573         rtc_set_memory(rtc, 0x5f, 0);
1574     } else {
1575         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1576     }
1577 }
1578
1579 static
1580 void pc_machine_done(Notifier *notifier, void *data)
1581 {
1582     PCMachineState *pcms = container_of(notifier,
1583                                         PCMachineState, machine_done);
1584     PCIBus *bus = pcms->bus;
1585
1586     /* set the number of CPUs */
1587     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1588
1589     if (bus) {
1590         int extra_hosts = 0;
1591
1592         QLIST_FOREACH(bus, &bus->child, sibling) {
1593             /* look for expander root buses */
1594             if (pci_bus_is_root(bus)) {
1595                 extra_hosts++;
1596             }
1597         }
1598         if (extra_hosts && pcms->fw_cfg) {
1599             uint64_t *val = g_malloc(sizeof(*val));
1600             *val = cpu_to_le64(extra_hosts);
1601             fw_cfg_add_file(pcms->fw_cfg,
1602                     "etc/extra-pci-roots", val, sizeof(*val));
1603         }
1604     }
1605
1606     acpi_setup();
1607     if (pcms->fw_cfg) {
1608         pc_build_smbios(pcms);
1609         pc_build_feature_control_file(pcms);
1610         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1611         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1612     }
1613
1614     if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1615         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1616
1617         if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1618             iommu->intr_eim != ON_OFF_AUTO_ON) {
1619             error_report("current -smp configuration requires "
1620                          "Extended Interrupt Mode enabled. "
1621                          "You can add an IOMMU using: "
1622                          "-device intel-iommu,intremap=on,eim=on");
1623             exit(EXIT_FAILURE);
1624         }
1625     }
1626 }
1627
1628 void pc_guest_info_init(PCMachineState *pcms)
1629 {
1630     int i;
1631
1632     pcms->apic_xrupt_override = kvm_allows_irq0_override();
1633     pcms->numa_nodes = nb_numa_nodes;
1634     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1635                                     sizeof *pcms->node_mem);
1636     for (i = 0; i < nb_numa_nodes; i++) {
1637         pcms->node_mem[i] = numa_info[i].node_mem;
1638     }
1639
1640     pcms->machine_done.notify = pc_machine_done;
1641     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1642 }
1643
1644 /* setup pci memory address space mapping into system address space */
1645 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1646                             MemoryRegion *pci_address_space)
1647 {
1648     /* Set to lower priority than RAM */
1649     memory_region_add_subregion_overlap(system_memory, 0x0,
1650                                         pci_address_space, -1);
1651 }
1652
1653 void pc_acpi_init(const char *default_dsdt)
1654 {
1655     char *filename;
1656
1657     if (acpi_tables != NULL) {
1658         /* manually set via -acpitable, leave it alone */
1659         return;
1660     }
1661
1662     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1663     if (filename == NULL) {
1664         warn_report("failed to find %s", default_dsdt);
1665     } else {
1666         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1667                                           &error_abort);
1668         Error *err = NULL;
1669
1670         qemu_opt_set(opts, "file", filename, &error_abort);
1671
1672         acpi_table_add_builtin(opts, &err);
1673         if (err) {
1674             warn_reportf_err(err, "failed to load %s: ", filename);
1675         }
1676         g_free(filename);
1677     }
1678 }
1679
1680 void xen_load_linux(PCMachineState *pcms)
1681 {
1682     int i;
1683     FWCfgState *fw_cfg;
1684
1685     assert(MACHINE(pcms)->kernel_filename != NULL);
1686
1687     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1688     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1689     rom_set_fw(fw_cfg);
1690
1691     load_linux(pcms, fw_cfg);
1692     for (i = 0; i < nb_option_roms; i++) {
1693         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1694                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1695                !strcmp(option_rom[i].name, "multiboot.bin"));
1696         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1697     }
1698     pcms->fw_cfg = fw_cfg;
1699 }
1700
1701 void pc_memory_init(PCMachineState *pcms,
1702                     MemoryRegion *system_memory,
1703                     MemoryRegion *rom_memory,
1704                     MemoryRegion **ram_memory)
1705 {
1706     int linux_boot, i;
1707     MemoryRegion *ram, *option_rom_mr;
1708     MemoryRegion *ram_below_4g, *ram_above_4g;
1709     FWCfgState *fw_cfg;
1710     MachineState *machine = MACHINE(pcms);
1711     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1712
1713     assert(machine->ram_size == pcms->below_4g_mem_size +
1714                                 pcms->above_4g_mem_size);
1715
1716     linux_boot = (machine->kernel_filename != NULL);
1717
1718     /* Allocate RAM.  We allocate it as a single memory region and use
1719      * aliases to address portions of it, mostly for backwards compatibility
1720      * with older qemus that used qemu_ram_alloc().
1721      */
1722     ram = g_malloc(sizeof(*ram));
1723     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1724                                          machine->ram_size);
1725     *ram_memory = ram;
1726     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1727     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1728                              0, pcms->below_4g_mem_size);
1729     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1730     e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1731     if (pcms->above_4g_mem_size > 0) {
1732         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1733         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1734                                  pcms->below_4g_mem_size,
1735                                  pcms->above_4g_mem_size);
1736         memory_region_add_subregion(system_memory, 0x100000000ULL,
1737                                     ram_above_4g);
1738         e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1739     }
1740
1741     if (!pcmc->has_reserved_memory &&
1742         (machine->ram_slots ||
1743          (machine->maxram_size > machine->ram_size))) {
1744         MachineClass *mc = MACHINE_GET_CLASS(machine);
1745
1746         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1747                      mc->name);
1748         exit(EXIT_FAILURE);
1749     }
1750
1751     /* always allocate the device memory information */
1752     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1753
1754     /* initialize device memory address space */
1755     if (pcmc->has_reserved_memory &&
1756         (machine->ram_size < machine->maxram_size)) {
1757         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1758
1759         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1760             error_report("unsupported amount of memory slots: %"PRIu64,
1761                          machine->ram_slots);
1762             exit(EXIT_FAILURE);
1763         }
1764
1765         if (QEMU_ALIGN_UP(machine->maxram_size,
1766                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1767             error_report("maximum memory size must by aligned to multiple of "
1768                          "%d bytes", TARGET_PAGE_SIZE);
1769             exit(EXIT_FAILURE);
1770         }
1771
1772         machine->device_memory->base =
1773             ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1774
1775         if (pcmc->enforce_aligned_dimm) {
1776             /* size device region assuming 1G page max alignment per slot */
1777             device_mem_size += (1 * GiB) * machine->ram_slots;
1778         }
1779
1780         if ((machine->device_memory->base + device_mem_size) <
1781             device_mem_size) {
1782             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1783                          machine->maxram_size);
1784             exit(EXIT_FAILURE);
1785         }
1786
1787         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1788                            "device-memory", device_mem_size);
1789         memory_region_add_subregion(system_memory, machine->device_memory->base,
1790                                     &machine->device_memory->mr);
1791     }
1792
1793     /* Initialize PC system firmware */
1794     pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1795
1796     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1797     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1798                            &error_fatal);
1799     if (pcmc->pci_enabled) {
1800         memory_region_set_readonly(option_rom_mr, true);
1801     }
1802     memory_region_add_subregion_overlap(rom_memory,
1803                                         PC_ROM_MIN_VGA,
1804                                         option_rom_mr,
1805                                         1);
1806
1807     fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1808
1809     rom_set_fw(fw_cfg);
1810
1811     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1812         uint64_t *val = g_malloc(sizeof(*val));
1813         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1814         uint64_t res_mem_end = machine->device_memory->base;
1815
1816         if (!pcmc->broken_reserved_end) {
1817             res_mem_end += memory_region_size(&machine->device_memory->mr);
1818         }
1819         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1820         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1821     }
1822
1823     if (linux_boot) {
1824         load_linux(pcms, fw_cfg);
1825     }
1826
1827     for (i = 0; i < nb_option_roms; i++) {
1828         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1829     }
1830     pcms->fw_cfg = fw_cfg;
1831
1832     /* Init default IOAPIC address space */
1833     pcms->ioapic_as = &address_space_memory;
1834 }
1835
1836 /*
1837  * The 64bit pci hole starts after "above 4G RAM" and
1838  * potentially the space reserved for memory hotplug.
1839  */
1840 uint64_t pc_pci_hole64_start(void)
1841 {
1842     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1843     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1844     MachineState *ms = MACHINE(pcms);
1845     uint64_t hole64_start = 0;
1846
1847     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1848         hole64_start = ms->device_memory->base;
1849         if (!pcmc->broken_reserved_end) {
1850             hole64_start += memory_region_size(&ms->device_memory->mr);
1851         }
1852     } else {
1853         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1854     }
1855
1856     return ROUND_UP(hole64_start, 1 * GiB);
1857 }
1858
1859 qemu_irq pc_allocate_cpu_irq(void)
1860 {
1861     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1862 }
1863
1864 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1865 {
1866     DeviceState *dev = NULL;
1867
1868     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1869     if (pci_bus) {
1870         PCIDevice *pcidev = pci_vga_init(pci_bus);
1871         dev = pcidev ? &pcidev->qdev : NULL;
1872     } else if (isa_bus) {
1873         ISADevice *isadev = isa_vga_init(isa_bus);
1874         dev = isadev ? DEVICE(isadev) : NULL;
1875     }
1876     rom_reset_order_override();
1877     return dev;
1878 }
1879
1880 static const MemoryRegionOps ioport80_io_ops = {
1881     .write = ioport80_write,
1882     .read = ioport80_read,
1883     .endianness = DEVICE_NATIVE_ENDIAN,
1884     .impl = {
1885         .min_access_size = 1,
1886         .max_access_size = 1,
1887     },
1888 };
1889
1890 static const MemoryRegionOps ioportF0_io_ops = {
1891     .write = ioportF0_write,
1892     .read = ioportF0_read,
1893     .endianness = DEVICE_NATIVE_ENDIAN,
1894     .impl = {
1895         .min_access_size = 1,
1896         .max_access_size = 1,
1897     },
1898 };
1899
1900 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1901 {
1902     int i;
1903     DriveInfo *fd[MAX_FD];
1904     qemu_irq *a20_line;
1905     ISADevice *i8042, *port92, *vmmouse;
1906
1907     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1908     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1909
1910     for (i = 0; i < MAX_FD; i++) {
1911         fd[i] = drive_get(IF_FLOPPY, 0, i);
1912         create_fdctrl |= !!fd[i];
1913     }
1914     if (create_fdctrl) {
1915         fdctrl_init_isa(isa_bus, fd);
1916     }
1917
1918     i8042 = isa_create_simple(isa_bus, "i8042");
1919     if (!no_vmport) {
1920         vmport_init(isa_bus);
1921         vmmouse = isa_try_create(isa_bus, "vmmouse");
1922     } else {
1923         vmmouse = NULL;
1924     }
1925     if (vmmouse) {
1926         DeviceState *dev = DEVICE(vmmouse);
1927         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1928         qdev_init_nofail(dev);
1929     }
1930     port92 = isa_create_simple(isa_bus, "port92");
1931
1932     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1933     i8042_setup_a20_line(i8042, a20_line[0]);
1934     port92_init(port92, a20_line[1]);
1935     g_free(a20_line);
1936 }
1937
1938 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1939                           ISADevice **rtc_state,
1940                           bool create_fdctrl,
1941                           bool no_vmport,
1942                           bool has_pit,
1943                           uint32_t hpet_irqs)
1944 {
1945     int i;
1946     DeviceState *hpet = NULL;
1947     int pit_isa_irq = 0;
1948     qemu_irq pit_alt_irq = NULL;
1949     qemu_irq rtc_irq = NULL;
1950     ISADevice *pit = NULL;
1951     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1952     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1953
1954     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1955     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1956
1957     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1958     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1959
1960     /*
1961      * Check if an HPET shall be created.
1962      *
1963      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1964      * when the HPET wants to take over. Thus we have to disable the latter.
1965      */
1966     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1967         /* In order to set property, here not using sysbus_try_create_simple */
1968         hpet = qdev_try_create(NULL, TYPE_HPET);
1969         if (hpet) {
1970             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1971              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1972              * IRQ8 and IRQ2.
1973              */
1974             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1975                     HPET_INTCAP, NULL);
1976             if (!compat) {
1977                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1978             }
1979             qdev_init_nofail(hpet);
1980             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1981
1982             for (i = 0; i < GSI_NUM_PINS; i++) {
1983                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1984             }
1985             pit_isa_irq = -1;
1986             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1987             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1988         }
1989     }
1990     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1991
1992     qemu_register_boot_set(pc_boot_set, *rtc_state);
1993
1994     if (!xen_enabled() && has_pit) {
1995         if (kvm_pit_in_kernel()) {
1996             pit = kvm_pit_init(isa_bus, 0x40);
1997         } else {
1998             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1999         }
2000         if (hpet) {
2001             /* connect PIT to output control line of the HPET */
2002             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
2003         }
2004         pcspk_init(isa_bus, pit);
2005     }
2006
2007     i8257_dma_init(isa_bus, 0);
2008
2009     /* Super I/O */
2010     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
2011 }
2012
2013 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
2014 {
2015     int i;
2016
2017     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
2018     for (i = 0; i < nb_nics; i++) {
2019         NICInfo *nd = &nd_table[i];
2020         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
2021
2022         if (g_str_equal(model, "ne2k_isa")) {
2023             pc_init_ne2k_isa(isa_bus, nd);
2024         } else {
2025             pci_nic_init_nofail(nd, pci_bus, model, NULL);
2026         }
2027     }
2028     rom_reset_order_override();
2029 }
2030
2031 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2032 {
2033     DeviceState *dev;
2034     SysBusDevice *d;
2035     unsigned int i;
2036
2037     if (kvm_ioapic_in_kernel()) {
2038         dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
2039     } else {
2040         dev = qdev_create(NULL, TYPE_IOAPIC);
2041     }
2042     if (parent_name) {
2043         object_property_add_child(object_resolve_path(parent_name, NULL),
2044                                   "ioapic", OBJECT(dev), NULL);
2045     }
2046     qdev_init_nofail(dev);
2047     d = SYS_BUS_DEVICE(dev);
2048     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
2049
2050     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2051         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2052     }
2053 }
2054
2055 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2056                                Error **errp)
2057 {
2058     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2059     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2060     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2061     const uint64_t legacy_align = TARGET_PAGE_SIZE;
2062
2063     /*
2064      * When -no-acpi is used with Q35 machine type, no ACPI is built,
2065      * but pcms->acpi_dev is still created. Check !acpi_enabled in
2066      * addition to cover this case.
2067      */
2068     if (!pcms->acpi_dev || !acpi_enabled) {
2069         error_setg(errp,
2070                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
2071         return;
2072     }
2073
2074     if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
2075         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2076         return;
2077     }
2078
2079     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
2080                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
2081 }
2082
2083 static void pc_memory_plug(HotplugHandler *hotplug_dev,
2084                            DeviceState *dev, Error **errp)
2085 {
2086     HotplugHandlerClass *hhc;
2087     Error *local_err = NULL;
2088     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2089     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2090
2091     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
2092     if (local_err) {
2093         goto out;
2094     }
2095
2096     if (is_nvdimm) {
2097         nvdimm_plug(&pcms->acpi_nvdimm_state);
2098     }
2099
2100     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2101     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
2102 out:
2103     error_propagate(errp, local_err);
2104 }
2105
2106 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2107                                      DeviceState *dev, Error **errp)
2108 {
2109     HotplugHandlerClass *hhc;
2110     Error *local_err = NULL;
2111     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2112
2113     /*
2114      * When -no-acpi is used with Q35 machine type, no ACPI is built,
2115      * but pcms->acpi_dev is still created. Check !acpi_enabled in
2116      * addition to cover this case.
2117      */
2118     if (!pcms->acpi_dev || !acpi_enabled) {
2119         error_setg(&local_err,
2120                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
2121         goto out;
2122     }
2123
2124     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2125         error_setg(&local_err,
2126                    "nvdimm device hot unplug is not supported yet.");
2127         goto out;
2128     }
2129
2130     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2131     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2132
2133 out:
2134     error_propagate(errp, local_err);
2135 }
2136
2137 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2138                              DeviceState *dev, Error **errp)
2139 {
2140     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2141     HotplugHandlerClass *hhc;
2142     Error *local_err = NULL;
2143
2144     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2145     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2146
2147     if (local_err) {
2148         goto out;
2149     }
2150
2151     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
2152     object_unparent(OBJECT(dev));
2153
2154  out:
2155     error_propagate(errp, local_err);
2156 }
2157
2158 static int pc_apic_cmp(const void *a, const void *b)
2159 {
2160    CPUArchId *apic_a = (CPUArchId *)a;
2161    CPUArchId *apic_b = (CPUArchId *)b;
2162
2163    return apic_a->arch_id - apic_b->arch_id;
2164 }
2165
2166 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2167  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2168  * entry corresponding to CPU's apic_id returns NULL.
2169  */
2170 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2171 {
2172     CPUArchId apic_id, *found_cpu;
2173
2174     apic_id.arch_id = id;
2175     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2176         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
2177         pc_apic_cmp);
2178     if (found_cpu && idx) {
2179         *idx = found_cpu - ms->possible_cpus->cpus;
2180     }
2181     return found_cpu;
2182 }
2183
2184 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2185                         DeviceState *dev, Error **errp)
2186 {
2187     CPUArchId *found_cpu;
2188     HotplugHandlerClass *hhc;
2189     Error *local_err = NULL;
2190     X86CPU *cpu = X86_CPU(dev);
2191     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2192
2193     if (pcms->acpi_dev) {
2194         hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2195         hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2196         if (local_err) {
2197             goto out;
2198         }
2199     }
2200
2201     /* increment the number of CPUs */
2202     pcms->boot_cpus++;
2203     if (pcms->rtc) {
2204         rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2205     }
2206     if (pcms->fw_cfg) {
2207         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2208     }
2209
2210     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2211     found_cpu->cpu = OBJECT(dev);
2212 out:
2213     error_propagate(errp, local_err);
2214 }
2215 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2216                                      DeviceState *dev, Error **errp)
2217 {
2218     int idx = -1;
2219     HotplugHandlerClass *hhc;
2220     Error *local_err = NULL;
2221     X86CPU *cpu = X86_CPU(dev);
2222     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2223
2224     if (!pcms->acpi_dev) {
2225         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2226         goto out;
2227     }
2228
2229     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2230     assert(idx != -1);
2231     if (idx == 0) {
2232         error_setg(&local_err, "Boot CPU is unpluggable");
2233         goto out;
2234     }
2235
2236     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2237     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2238
2239     if (local_err) {
2240         goto out;
2241     }
2242
2243  out:
2244     error_propagate(errp, local_err);
2245
2246 }
2247
2248 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2249                              DeviceState *dev, Error **errp)
2250 {
2251     CPUArchId *found_cpu;
2252     HotplugHandlerClass *hhc;
2253     Error *local_err = NULL;
2254     X86CPU *cpu = X86_CPU(dev);
2255     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2256
2257     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2258     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2259
2260     if (local_err) {
2261         goto out;
2262     }
2263
2264     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2265     found_cpu->cpu = NULL;
2266     object_unparent(OBJECT(dev));
2267
2268     /* decrement the number of CPUs */
2269     pcms->boot_cpus--;
2270     /* Update the number of CPUs in CMOS */
2271     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2272     fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2273  out:
2274     error_propagate(errp, local_err);
2275 }
2276
2277 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2278                             DeviceState *dev, Error **errp)
2279 {
2280     int idx;
2281     CPUState *cs;
2282     CPUArchId *cpu_slot;
2283     X86CPUTopoInfo topo;
2284     X86CPU *cpu = X86_CPU(dev);
2285     MachineState *ms = MACHINE(hotplug_dev);
2286     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2287
2288     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2289         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2290                    ms->cpu_type);
2291         return;
2292     }
2293
2294     /* if APIC ID is not set, set it based on socket/core/thread properties */
2295     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2296         int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2297
2298         if (cpu->socket_id < 0) {
2299             error_setg(errp, "CPU socket-id is not set");
2300             return;
2301         } else if (cpu->socket_id > max_socket) {
2302             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2303                        cpu->socket_id, max_socket);
2304             return;
2305         }
2306         if (cpu->core_id < 0) {
2307             error_setg(errp, "CPU core-id is not set");
2308             return;
2309         } else if (cpu->core_id > (smp_cores - 1)) {
2310             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2311                        cpu->core_id, smp_cores - 1);
2312             return;
2313         }
2314         if (cpu->thread_id < 0) {
2315             error_setg(errp, "CPU thread-id is not set");
2316             return;
2317         } else if (cpu->thread_id > (smp_threads - 1)) {
2318             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2319                        cpu->thread_id, smp_threads - 1);
2320             return;
2321         }
2322
2323         topo.pkg_id = cpu->socket_id;
2324         topo.core_id = cpu->core_id;
2325         topo.smt_id = cpu->thread_id;
2326         cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2327     }
2328
2329     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2330     if (!cpu_slot) {
2331         MachineState *ms = MACHINE(pcms);
2332
2333         x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2334         error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2335                   " APIC ID %" PRIu32 ", valid index range 0:%d",
2336                    topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
2337                    ms->possible_cpus->len - 1);
2338         return;
2339     }
2340
2341     if (cpu_slot->cpu) {
2342         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2343                    idx, cpu->apic_id);
2344         return;
2345     }
2346
2347     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2348      * so that machine_query_hotpluggable_cpus would show correct values
2349      */
2350     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2351      * once -smp refactoring is complete and there will be CPU private
2352      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2353     x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2354     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2355         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2356             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2357         return;
2358     }
2359     cpu->socket_id = topo.pkg_id;
2360
2361     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2362         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2363             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2364         return;
2365     }
2366     cpu->core_id = topo.core_id;
2367
2368     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2369         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2370             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2371         return;
2372     }
2373     cpu->thread_id = topo.smt_id;
2374
2375     if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2376         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2377         return;
2378     }
2379
2380     cs = CPU(cpu);
2381     cs->cpu_index = idx;
2382
2383     numa_cpu_pre_plug(cpu_slot, dev, errp);
2384 }
2385
2386 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2387                                           DeviceState *dev, Error **errp)
2388 {
2389     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2390         pc_memory_pre_plug(hotplug_dev, dev, errp);
2391     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2392         pc_cpu_pre_plug(hotplug_dev, dev, errp);
2393     }
2394 }
2395
2396 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2397                                       DeviceState *dev, Error **errp)
2398 {
2399     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2400         pc_memory_plug(hotplug_dev, dev, errp);
2401     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2402         pc_cpu_plug(hotplug_dev, dev, errp);
2403     }
2404 }
2405
2406 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2407                                                 DeviceState *dev, Error **errp)
2408 {
2409     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2410         pc_memory_unplug_request(hotplug_dev, dev, errp);
2411     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2412         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2413     } else {
2414         error_setg(errp, "acpi: device unplug request for not supported device"
2415                    " type: %s", object_get_typename(OBJECT(dev)));
2416     }
2417 }
2418
2419 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2420                                         DeviceState *dev, Error **errp)
2421 {
2422     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2423         pc_memory_unplug(hotplug_dev, dev, errp);
2424     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2425         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2426     } else {
2427         error_setg(errp, "acpi: device unplug for not supported device"
2428                    " type: %s", object_get_typename(OBJECT(dev)));
2429     }
2430 }
2431
2432 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
2433                                              DeviceState *dev)
2434 {
2435     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2436         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2437         return HOTPLUG_HANDLER(machine);
2438     }
2439
2440     return NULL;
2441 }
2442
2443 static void
2444 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2445                                          const char *name, void *opaque,
2446                                          Error **errp)
2447 {
2448     MachineState *ms = MACHINE(obj);
2449     int64_t value = memory_region_size(&ms->device_memory->mr);
2450
2451     visit_type_int(v, name, &value, errp);
2452 }
2453
2454 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2455                                             const char *name, void *opaque,
2456                                             Error **errp)
2457 {
2458     PCMachineState *pcms = PC_MACHINE(obj);
2459     uint64_t value = pcms->max_ram_below_4g;
2460
2461     visit_type_size(v, name, &value, errp);
2462 }
2463
2464 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2465                                             const char *name, void *opaque,
2466                                             Error **errp)
2467 {
2468     PCMachineState *pcms = PC_MACHINE(obj);
2469     Error *error = NULL;
2470     uint64_t value;
2471
2472     visit_type_size(v, name, &value, &error);
2473     if (error) {
2474         error_propagate(errp, error);
2475         return;
2476     }
2477     if (value > 4 * GiB) {
2478         error_setg(&error,
2479                    "Machine option 'max-ram-below-4g=%"PRIu64
2480                    "' expects size less than or equal to 4G", value);
2481         error_propagate(errp, error);
2482         return;
2483     }
2484
2485     if (value < 1 * MiB) {
2486         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2487                     "BIOS may not work with less than 1MiB", value);
2488     }
2489
2490     pcms->max_ram_below_4g = value;
2491 }
2492
2493 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2494                                   void *opaque, Error **errp)
2495 {
2496     PCMachineState *pcms = PC_MACHINE(obj);
2497     OnOffAuto vmport = pcms->vmport;
2498
2499     visit_type_OnOffAuto(v, name, &vmport, errp);
2500 }
2501
2502 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2503                                   void *opaque, Error **errp)
2504 {
2505     PCMachineState *pcms = PC_MACHINE(obj);
2506
2507     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2508 }
2509
2510 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2511 {
2512     bool smm_available = false;
2513
2514     if (pcms->smm == ON_OFF_AUTO_OFF) {
2515         return false;
2516     }
2517
2518     if (tcg_enabled() || qtest_enabled()) {
2519         smm_available = true;
2520     } else if (kvm_enabled()) {
2521         smm_available = kvm_has_smm();
2522     }
2523
2524     if (smm_available) {
2525         return true;
2526     }
2527
2528     if (pcms->smm == ON_OFF_AUTO_ON) {
2529         error_report("System Management Mode not supported by this hypervisor.");
2530         exit(1);
2531     }
2532     return false;
2533 }
2534
2535 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2536                                void *opaque, Error **errp)
2537 {
2538     PCMachineState *pcms = PC_MACHINE(obj);
2539     OnOffAuto smm = pcms->smm;
2540
2541     visit_type_OnOffAuto(v, name, &smm, errp);
2542 }
2543
2544 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2545                                void *opaque, Error **errp)
2546 {
2547     PCMachineState *pcms = PC_MACHINE(obj);
2548
2549     visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2550 }
2551
2552 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2553 {
2554     PCMachineState *pcms = PC_MACHINE(obj);
2555
2556     return pcms->acpi_nvdimm_state.is_enabled;
2557 }
2558
2559 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2560 {
2561     PCMachineState *pcms = PC_MACHINE(obj);
2562
2563     pcms->acpi_nvdimm_state.is_enabled = value;
2564 }
2565
2566 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2567 {
2568     PCMachineState *pcms = PC_MACHINE(obj);
2569
2570     return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2571 }
2572
2573 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2574                                                Error **errp)
2575 {
2576     PCMachineState *pcms = PC_MACHINE(obj);
2577     AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2578
2579     if (strcmp(value, "cpu") == 0)
2580         nvdimm_state->persistence = 3;
2581     else if (strcmp(value, "mem-ctrl") == 0)
2582         nvdimm_state->persistence = 2;
2583     else {
2584         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2585                    value);
2586         return;
2587     }
2588
2589     g_free(nvdimm_state->persistence_string);
2590     nvdimm_state->persistence_string = g_strdup(value);
2591 }
2592
2593 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2594 {
2595     PCMachineState *pcms = PC_MACHINE(obj);
2596
2597     return pcms->smbus_enabled;
2598 }
2599
2600 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2601 {
2602     PCMachineState *pcms = PC_MACHINE(obj);
2603
2604     pcms->smbus_enabled = value;
2605 }
2606
2607 static bool pc_machine_get_sata(Object *obj, Error **errp)
2608 {
2609     PCMachineState *pcms = PC_MACHINE(obj);
2610
2611     return pcms->sata_enabled;
2612 }
2613
2614 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2615 {
2616     PCMachineState *pcms = PC_MACHINE(obj);
2617
2618     pcms->sata_enabled = value;
2619 }
2620
2621 static bool pc_machine_get_pit(Object *obj, Error **errp)
2622 {
2623     PCMachineState *pcms = PC_MACHINE(obj);
2624
2625     return pcms->pit_enabled;
2626 }
2627
2628 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2629 {
2630     PCMachineState *pcms = PC_MACHINE(obj);
2631
2632     pcms->pit_enabled = value;
2633 }
2634
2635 static void pc_machine_initfn(Object *obj)
2636 {
2637     PCMachineState *pcms = PC_MACHINE(obj);
2638
2639     pcms->max_ram_below_4g = 0; /* use default */
2640     pcms->smm = ON_OFF_AUTO_AUTO;
2641     pcms->vmport = ON_OFF_AUTO_AUTO;
2642     /* nvdimm is disabled on default. */
2643     pcms->acpi_nvdimm_state.is_enabled = false;
2644     /* acpi build is enabled by default if machine supports it */
2645     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2646     pcms->smbus_enabled = true;
2647     pcms->sata_enabled = true;
2648     pcms->pit_enabled = true;
2649 }
2650
2651 static void pc_machine_reset(void)
2652 {
2653     CPUState *cs;
2654     X86CPU *cpu;
2655
2656     qemu_devices_reset();
2657
2658     /* Reset APIC after devices have been reset to cancel
2659      * any changes that qemu_devices_reset() might have done.
2660      */
2661     CPU_FOREACH(cs) {
2662         cpu = X86_CPU(cs);
2663
2664         if (cpu->apic_state) {
2665             device_reset(cpu->apic_state);
2666         }
2667     }
2668 }
2669
2670 static CpuInstanceProperties
2671 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2672 {
2673     MachineClass *mc = MACHINE_GET_CLASS(ms);
2674     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2675
2676     assert(cpu_index < possible_cpus->len);
2677     return possible_cpus->cpus[cpu_index].props;
2678 }
2679
2680 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2681 {
2682    X86CPUTopoInfo topo;
2683
2684    assert(idx < ms->possible_cpus->len);
2685    x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2686                             smp_cores, smp_threads, &topo);
2687    return topo.pkg_id % nb_numa_nodes;
2688 }
2689
2690 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2691 {
2692     int i;
2693
2694     if (ms->possible_cpus) {
2695         /*
2696          * make sure that max_cpus hasn't changed since the first use, i.e.
2697          * -smp hasn't been parsed after it
2698         */
2699         assert(ms->possible_cpus->len == max_cpus);
2700         return ms->possible_cpus;
2701     }
2702
2703     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2704                                   sizeof(CPUArchId) * max_cpus);
2705     ms->possible_cpus->len = max_cpus;
2706     for (i = 0; i < ms->possible_cpus->len; i++) {
2707         X86CPUTopoInfo topo;
2708
2709         ms->possible_cpus->cpus[i].type = ms->cpu_type;
2710         ms->possible_cpus->cpus[i].vcpus_count = 1;
2711         ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2712         x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2713                                  smp_cores, smp_threads, &topo);
2714         ms->possible_cpus->cpus[i].props.has_socket_id = true;
2715         ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2716         ms->possible_cpus->cpus[i].props.has_core_id = true;
2717         ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2718         ms->possible_cpus->cpus[i].props.has_thread_id = true;
2719         ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2720     }
2721     return ms->possible_cpus;
2722 }
2723
2724 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2725 {
2726     /* cpu index isn't used */
2727     CPUState *cs;
2728
2729     CPU_FOREACH(cs) {
2730         X86CPU *cpu = X86_CPU(cs);
2731
2732         if (!cpu->apic_state) {
2733             cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2734         } else {
2735             apic_deliver_nmi(cpu->apic_state);
2736         }
2737     }
2738 }
2739
2740 static void pc_machine_class_init(ObjectClass *oc, void *data)
2741 {
2742     MachineClass *mc = MACHINE_CLASS(oc);
2743     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2744     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2745     NMIClass *nc = NMI_CLASS(oc);
2746
2747     pcmc->pci_enabled = true;
2748     pcmc->has_acpi_build = true;
2749     pcmc->rsdp_in_ram = true;
2750     pcmc->smbios_defaults = true;
2751     pcmc->smbios_uuid_encoded = true;
2752     pcmc->gigabyte_align = true;
2753     pcmc->has_reserved_memory = true;
2754     pcmc->kvmclock_enabled = true;
2755     pcmc->enforce_aligned_dimm = true;
2756     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2757      * to be used at the moment, 32K should be enough for a while.  */
2758     pcmc->acpi_data_size = 0x20000 + 0x8000;
2759     pcmc->save_tsc_khz = true;
2760     pcmc->linuxboot_dma_enabled = true;
2761     assert(!mc->get_hotplug_handler);
2762     mc->get_hotplug_handler = pc_get_hotplug_handler;
2763     mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2764     mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2765     mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2766     mc->auto_enable_numa_with_memhp = true;
2767     mc->has_hotpluggable_cpus = true;
2768     mc->default_boot_order = "cad";
2769     mc->hot_add_cpu = pc_hot_add_cpu;
2770     mc->block_default_type = IF_IDE;
2771     mc->max_cpus = 255;
2772     mc->reset = pc_machine_reset;
2773     hc->pre_plug = pc_machine_device_pre_plug_cb;
2774     hc->plug = pc_machine_device_plug_cb;
2775     hc->unplug_request = pc_machine_device_unplug_request_cb;
2776     hc->unplug = pc_machine_device_unplug_cb;
2777     nc->nmi_monitor_handler = x86_nmi;
2778     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2779
2780     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2781         pc_machine_get_device_memory_region_size, NULL,
2782         NULL, NULL, &error_abort);
2783
2784     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2785         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2786         NULL, NULL, &error_abort);
2787
2788     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2789         "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2790
2791     object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2792         pc_machine_get_smm, pc_machine_set_smm,
2793         NULL, NULL, &error_abort);
2794     object_class_property_set_description(oc, PC_MACHINE_SMM,
2795         "Enable SMM (pc & q35)", &error_abort);
2796
2797     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2798         pc_machine_get_vmport, pc_machine_set_vmport,
2799         NULL, NULL, &error_abort);
2800     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2801         "Enable vmport (pc & q35)", &error_abort);
2802
2803     object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2804         pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2805
2806     object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2807         pc_machine_get_nvdimm_persistence,
2808         pc_machine_set_nvdimm_persistence, &error_abort);
2809
2810     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2811         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2812
2813     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2814         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2815
2816     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2817         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2818 }
2819
2820 static const TypeInfo pc_machine_info = {
2821     .name = TYPE_PC_MACHINE,
2822     .parent = TYPE_MACHINE,
2823     .abstract = true,
2824     .instance_size = sizeof(PCMachineState),
2825     .instance_init = pc_machine_initfn,
2826     .class_size = sizeof(PCMachineClass),
2827     .class_init = pc_machine_class_init,
2828     .interfaces = (InterfaceInfo[]) {
2829          { TYPE_HOTPLUG_HANDLER },
2830          { TYPE_NMI },
2831          { }
2832     },
2833 };
2834
2835 static void pc_machine_register_types(void)
2836 {
2837     type_register_static(&pc_machine_info);
2838 }
2839
2840 type_init(pc_machine_register_types)