hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "sysemu/cpus.h"
  34 #include "hw/block/fdc.h"
  35 #include "hw/ide.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/timer/hpet.h"
  40 #include "hw/firmware/smbios.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "multiboot.h"
  44 #include "hw/timer/mc146818rtc.h"
  45 #include "hw/dma/i8257.h"
  46 #include "hw/timer/i8254.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/audio/pcspk.h"
  49 #include "hw/pci/msi.h"
  50 #include "hw/sysbus.h"
  51 #include "sysemu/sysemu.h"
  52 #include "sysemu/numa.h"
  53 #include "sysemu/kvm.h"
  54 #include "sysemu/qtest.h"
  55 #include "kvm_i386.h"
  56 #include "hw/xen/xen.h"
  57 #include "ui/qemu-spice.h"
  58 #include "exec/memory.h"
  59 #include "exec/address-spaces.h"
  60 #include "sysemu/arch_init.h"
  61 #include "qemu/bitmap.h"
  62 #include "qemu/config-file.h"
  63 #include "qemu/error-report.h"
  64 #include "qemu/option.h"
  65 #include "hw/acpi/acpi.h"
  66 #include "hw/acpi/cpu_hotplug.h"
  67 #include "hw/boards.h"
  68 #include "acpi-build.h"
  69 #include "hw/mem/pc-dimm.h"
  70 #include "qapi/error.h"
  71 #include "qapi/qapi-visit-common.h"
  72 #include "qapi/visitor.h"
  73 #include "qom/cpu.h"
  74 #include "hw/nmi.h"
  75 #include "hw/i386/intel_iommu.h"
  76 #include "hw/net/ne2000-isa.h"
  77
  78 /* debug PC/ISA interrupts */
  79 //#define DEBUG_IRQ
  80
  81 #ifdef DEBUG_IRQ
  82 #define DPRINTF(fmt, ...)                                       \
  83     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  84 #else
  85 #define DPRINTF(fmt, ...)
  86 #endif
  87
  88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  93
  94 #define E820_NR_ENTRIES         16
  95
  96 struct e820_entry {
  97     uint64_t address;
  98     uint64_t length;
  99     uint32_t type;
 100 } QEMU_PACKED __attribute((__aligned__(4)));
 101
 102 struct e820_table {
 103     uint32_t count;
 104     struct e820_entry entry[E820_NR_ENTRIES];
 105 } QEMU_PACKED __attribute((__aligned__(4)));
 106
 107 static struct e820_table e820_reserve;
 108 static struct e820_entry *e820_table;
 109 static unsigned e820_entries;
 110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
 111
 112 GlobalProperty pc_compat_3_1[] = {
 113     {
 114         .driver   = "intel-iommu",
 115         .property = "dma-drain",
 116         .value    = "off",
 117     },
 118 };
 119 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
 120
 121 void gsi_handler(void *opaque, int n, int level)
 122 {
 123     GSIState *s = opaque;
 124
 125     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 126     if (n < ISA_NUM_IRQS) {
 127         qemu_set_irq(s->i8259_irq[n], level);
 128     }
 129     qemu_set_irq(s->ioapic_irq[n], level);
 130 }
 131
 132 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 133                            unsigned size)
 134 {
 135 }
 136
 137 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 138 {
 139     return 0xffffffffffffffffULL;
 140 }
 141
 142 /* MSDOS compatibility mode FPU exception support */
 143 static qemu_irq ferr_irq;
 144
 145 void pc_register_ferr_irq(qemu_irq irq)
 146 {
 147     ferr_irq = irq;
 148 }
 149
 150 /* XXX: add IGNNE support */
 151 void cpu_set_ferr(CPUX86State *s)
 152 {
 153     qemu_irq_raise(ferr_irq);
 154 }
 155
 156 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 157                            unsigned size)
 158 {
 159     qemu_irq_lower(ferr_irq);
 160 }
 161
 162 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 163 {
 164     return 0xffffffffffffffffULL;
 165 }
 166
 167 /* TSC handling */
 168 uint64_t cpu_get_tsc(CPUX86State *env)
 169 {
 170     return cpu_get_ticks();
 171 }
 172
 173 /* IRQ handling */
 174 int cpu_get_pic_interrupt(CPUX86State *env)
 175 {
 176     X86CPU *cpu = x86_env_get_cpu(env);
 177     int intno;
 178
 179     if (!kvm_irqchip_in_kernel()) {
 180         intno = apic_get_interrupt(cpu->apic_state);
 181         if (intno >= 0) {
 182             return intno;
 183         }
 184         /* read the irq from the PIC */
 185         if (!apic_accept_pic_intr(cpu->apic_state)) {
 186             return -1;
 187         }
 188     }
 189
 190     intno = pic_read_irq(isa_pic);
 191     return intno;
 192 }
 193
 194 static void pic_irq_request(void *opaque, int irq, int level)
 195 {
 196     CPUState *cs = first_cpu;
 197     X86CPU *cpu = X86_CPU(cs);
 198
 199     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 200     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 201         CPU_FOREACH(cs) {
 202             cpu = X86_CPU(cs);
 203             if (apic_accept_pic_intr(cpu->apic_state)) {
 204                 apic_deliver_pic_intr(cpu->apic_state, level);
 205             }
 206         }
 207     } else {
 208         if (level) {
 209             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 210         } else {
 211             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 212         }
 213     }
 214 }
 215
 216 /* PC cmos mappings */
 217
 218 #define REG_EQUIPMENT_BYTE          0x14
 219
 220 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 221 {
 222     int val;
 223
 224     switch (fd0) {
 225     case FLOPPY_DRIVE_TYPE_144:
 226         /* 1.44 Mb 3"5 drive */
 227         val = 4;
 228         break;
 229     case FLOPPY_DRIVE_TYPE_288:
 230         /* 2.88 Mb 3"5 drive */
 231         val = 5;
 232         break;
 233     case FLOPPY_DRIVE_TYPE_120:
 234         /* 1.2 Mb 5"5 drive */
 235         val = 2;
 236         break;
 237     case FLOPPY_DRIVE_TYPE_NONE:
 238     default:
 239         val = 0;
 240         break;
 241     }
 242     return val;
 243 }
 244
 245 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 246                          int16_t cylinders, int8_t heads, int8_t sectors)
 247 {
 248     rtc_set_memory(s, type_ofs, 47);
 249     rtc_set_memory(s, info_ofs, cylinders);
 250     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 251     rtc_set_memory(s, info_ofs + 2, heads);
 252     rtc_set_memory(s, info_ofs + 3, 0xff);
 253     rtc_set_memory(s, info_ofs + 4, 0xff);
 254     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 255     rtc_set_memory(s, info_ofs + 6, cylinders);
 256     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 257     rtc_set_memory(s, info_ofs + 8, sectors);
 258 }
 259
 260 /* convert boot_device letter to something recognizable by the bios */
 261 static int boot_device2nibble(char boot_device)
 262 {
 263     switch(boot_device) {
 264     case 'a':
 265     case 'b':
 266         return 0x01; /* floppy boot */
 267     case 'c':
 268         return 0x02; /* hard drive boot */
 269     case 'd':
 270         return 0x03; /* CD-ROM boot */
 271     case 'n':
 272         return 0x04; /* Network boot */
 273     }
 274     return 0;
 275 }
 276
 277 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 278 {
 279 #define PC_MAX_BOOT_DEVICES 3
 280     int nbds, bds[3] = { 0, };
 281     int i;
 282
 283     nbds = strlen(boot_device);
 284     if (nbds > PC_MAX_BOOT_DEVICES) {
 285         error_setg(errp, "Too many boot devices for PC");
 286         return;
 287     }
 288     for (i = 0; i < nbds; i++) {
 289         bds[i] = boot_device2nibble(boot_device[i]);
 290         if (bds[i] == 0) {
 291             error_setg(errp, "Invalid boot device for PC: '%c'",
 292                        boot_device[i]);
 293             return;
 294         }
 295     }
 296     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 297     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 298 }
 299
 300 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 301 {
 302     set_boot_dev(opaque, boot_device, errp);
 303 }
 304
 305 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 306 {
 307     int val, nb, i;
 308     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 309                                    FLOPPY_DRIVE_TYPE_NONE };
 310
 311     /* floppy type */
 312     if (floppy) {
 313         for (i = 0; i < 2; i++) {
 314             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 315         }
 316     }
 317     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 318         cmos_get_fd_drive_type(fd_type[1]);
 319     rtc_set_memory(rtc_state, 0x10, val);
 320
 321     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 322     nb = 0;
 323     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 324         nb++;
 325     }
 326     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 327         nb++;
 328     }
 329     switch (nb) {
 330     case 0:
 331         break;
 332     case 1:
 333         val |= 0x01; /* 1 drive, ready for boot */
 334         break;
 335     case 2:
 336         val |= 0x41; /* 2 drives, ready for boot */
 337         break;
 338     }
 339     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 340 }
 341
 342 typedef struct pc_cmos_init_late_arg {
 343     ISADevice *rtc_state;
 344     BusState *idebus[2];
 345 } pc_cmos_init_late_arg;
 346
 347 typedef struct check_fdc_state {
 348     ISADevice *floppy;
 349     bool multiple;
 350 } CheckFdcState;
 351
 352 static int check_fdc(Object *obj, void *opaque)
 353 {
 354     CheckFdcState *state = opaque;
 355     Object *fdc;
 356     uint32_t iobase;
 357     Error *local_err = NULL;
 358
 359     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 360     if (!fdc) {
 361         return 0;
 362     }
 363
 364     iobase = object_property_get_uint(obj, "iobase", &local_err);
 365     if (local_err || iobase != 0x3f0) {
 366         error_free(local_err);
 367         return 0;
 368     }
 369
 370     if (state->floppy) {
 371         state->multiple = true;
 372     } else {
 373         state->floppy = ISA_DEVICE(obj);
 374     }
 375     return 0;
 376 }
 377
 378 static const char * const fdc_container_path[] = {
 379     "/unattached", "/peripheral", "/peripheral-anon"
 380 };
 381
 382 /*
 383  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 384  * and ACPI objects.
 385  */
 386 ISADevice *pc_find_fdc0(void)
 387 {
 388     int i;
 389     Object *container;
 390     CheckFdcState state = { 0 };
 391
 392     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 393         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 394         object_child_foreach(container, check_fdc, &state);
 395     }
 396
 397     if (state.multiple) {
 398         warn_report("multiple floppy disk controllers with "
 399                     "iobase=0x3f0 have been found");
 400         error_printf("the one being picked for CMOS setup might not reflect "
 401                      "your intent");
 402     }
 403
 404     return state.floppy;
 405 }
 406
 407 static void pc_cmos_init_late(void *opaque)
 408 {
 409     pc_cmos_init_late_arg *arg = opaque;
 410     ISADevice *s = arg->rtc_state;
 411     int16_t cylinders;
 412     int8_t heads, sectors;
 413     int val;
 414     int i, trans;
 415
 416     val = 0;
 417     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 418                                            &cylinders, &heads, &sectors) >= 0) {
 419         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 420         val |= 0xf0;
 421     }
 422     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 423                                            &cylinders, &heads, &sectors) >= 0) {
 424         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 425         val |= 0x0f;
 426     }
 427     rtc_set_memory(s, 0x12, val);
 428
 429     val = 0;
 430     for (i = 0; i < 4; i++) {
 431         /* NOTE: ide_get_geometry() returns the physical
 432            geometry.  It is always such that: 1 <= sects <= 63, 1
 433            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 434            geometry can be different if a translation is done. */
 435         if (arg->idebus[i / 2] &&
 436             ide_get_geometry(arg->idebus[i / 2], i % 2,
 437                              &cylinders, &heads, &sectors) >= 0) {
 438             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 439             assert((trans & ~3) == 0);
 440             val |= trans << (i * 2);
 441         }
 442     }
 443     rtc_set_memory(s, 0x39, val);
 444
 445     pc_cmos_init_floppy(s, pc_find_fdc0());
 446
 447     qemu_unregister_reset(pc_cmos_init_late, opaque);
 448 }
 449
 450 void pc_cmos_init(PCMachineState *pcms,
 451                   BusState *idebus0, BusState *idebus1,
 452                   ISADevice *s)
 453 {
 454     int val;
 455     static pc_cmos_init_late_arg arg;
 456
 457     /* various important CMOS locations needed by PC/Bochs bios */
 458
 459     /* memory size */
 460     /* base memory (first MiB) */
 461     val = MIN(pcms->below_4g_mem_size / KiB, 640);
 462     rtc_set_memory(s, 0x15, val);
 463     rtc_set_memory(s, 0x16, val >> 8);
 464     /* extended memory (next 64MiB) */
 465     if (pcms->below_4g_mem_size > 1 * MiB) {
 466         val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
 467     } else {
 468         val = 0;
 469     }
 470     if (val > 65535)
 471         val = 65535;
 472     rtc_set_memory(s, 0x17, val);
 473     rtc_set_memory(s, 0x18, val >> 8);
 474     rtc_set_memory(s, 0x30, val);
 475     rtc_set_memory(s, 0x31, val >> 8);
 476     /* memory between 16MiB and 4GiB */
 477     if (pcms->below_4g_mem_size > 16 * MiB) {
 478         val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 479     } else {
 480         val = 0;
 481     }
 482     if (val > 65535)
 483         val = 65535;
 484     rtc_set_memory(s, 0x34, val);
 485     rtc_set_memory(s, 0x35, val >> 8);
 486     /* memory above 4GiB */
 487     val = pcms->above_4g_mem_size / 65536;
 488     rtc_set_memory(s, 0x5b, val);
 489     rtc_set_memory(s, 0x5c, val >> 8);
 490     rtc_set_memory(s, 0x5d, val >> 16);
 491
 492     object_property_add_link(OBJECT(pcms), "rtc_state",
 493                              TYPE_ISA_DEVICE,
 494                              (Object **)&pcms->rtc,
 495                              object_property_allow_set_link,
 496                              OBJ_PROP_LINK_STRONG, &error_abort);
 497     object_property_set_link(OBJECT(pcms), OBJECT(s),
 498                              "rtc_state", &error_abort);
 499
 500     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 501
 502     val = 0;
 503     val |= 0x02; /* FPU is there */
 504     val |= 0x04; /* PS/2 mouse installed */
 505     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 506
 507     /* hard drives and FDC */
 508     arg.rtc_state = s;
 509     arg.idebus[0] = idebus0;
 510     arg.idebus[1] = idebus1;
 511     qemu_register_reset(pc_cmos_init_late, &arg);
 512 }
 513
 514 #define TYPE_PORT92 "port92"
 515 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 516
 517 /* port 92 stuff: could be split off */
 518 typedef struct Port92State {
 519     ISADevice parent_obj;
 520
 521     MemoryRegion io;
 522     uint8_t outport;
 523     qemu_irq a20_out;
 524 } Port92State;
 525
 526 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 527                          unsigned size)
 528 {
 529     Port92State *s = opaque;
 530     int oldval = s->outport;
 531
 532     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
 533     s->outport = val;
 534     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 535     if ((val & 1) && !(oldval & 1)) {
 536         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 537     }
 538 }
 539
 540 static uint64_t port92_read(void *opaque, hwaddr addr,
 541                             unsigned size)
 542 {
 543     Port92State *s = opaque;
 544     uint32_t ret;
 545
 546     ret = s->outport;
 547     DPRINTF("port92: read 0x%02x\n", ret);
 548     return ret;
 549 }
 550
 551 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 552 {
 553     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 554 }
 555
 556 static const VMStateDescription vmstate_port92_isa = {
 557     .name = "port92",
 558     .version_id = 1,
 559     .minimum_version_id = 1,
 560     .fields = (VMStateField[]) {
 561         VMSTATE_UINT8(outport, Port92State),
 562         VMSTATE_END_OF_LIST()
 563     }
 564 };
 565
 566 static void port92_reset(DeviceState *d)
 567 {
 568     Port92State *s = PORT92(d);
 569
 570     s->outport &= ~1;
 571 }
 572
 573 static const MemoryRegionOps port92_ops = {
 574     .read = port92_read,
 575     .write = port92_write,
 576     .impl = {
 577         .min_access_size = 1,
 578         .max_access_size = 1,
 579     },
 580     .endianness = DEVICE_LITTLE_ENDIAN,
 581 };
 582
 583 static void port92_initfn(Object *obj)
 584 {
 585     Port92State *s = PORT92(obj);
 586
 587     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 588
 589     s->outport = 0;
 590
 591     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 592 }
 593
 594 static void port92_realizefn(DeviceState *dev, Error **errp)
 595 {
 596     ISADevice *isadev = ISA_DEVICE(dev);
 597     Port92State *s = PORT92(dev);
 598
 599     isa_register_ioport(isadev, &s->io, 0x92);
 600 }
 601
 602 static void port92_class_initfn(ObjectClass *klass, void *data)
 603 {
 604     DeviceClass *dc = DEVICE_CLASS(klass);
 605
 606     dc->realize = port92_realizefn;
 607     dc->reset = port92_reset;
 608     dc->vmsd = &vmstate_port92_isa;
 609     /*
 610      * Reason: unlike ordinary ISA devices, this one needs additional
 611      * wiring: its A20 output line needs to be wired up by
 612      * port92_init().
 613      */
 614     dc->user_creatable = false;
 615 }
 616
 617 static const TypeInfo port92_info = {
 618     .name          = TYPE_PORT92,
 619     .parent        = TYPE_ISA_DEVICE,
 620     .instance_size = sizeof(Port92State),
 621     .instance_init = port92_initfn,
 622     .class_init    = port92_class_initfn,
 623 };
 624
 625 static void port92_register_types(void)
 626 {
 627     type_register_static(&port92_info);
 628 }
 629
 630 type_init(port92_register_types)
 631
 632 static void handle_a20_line_change(void *opaque, int irq, int level)
 633 {
 634     X86CPU *cpu = opaque;
 635
 636     /* XXX: send to all CPUs ? */
 637     /* XXX: add logic to handle multiple A20 line sources */
 638     x86_cpu_set_a20(cpu, level);
 639 }
 640
 641 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 642 {
 643     int index = le32_to_cpu(e820_reserve.count);
 644     struct e820_entry *entry;
 645
 646     if (type != E820_RAM) {
 647         /* old FW_CFG_E820_TABLE entry -- reservations only */
 648         if (index >= E820_NR_ENTRIES) {
 649             return -EBUSY;
 650         }
 651         entry = &e820_reserve.entry[index++];
 652
 653         entry->address = cpu_to_le64(address);
 654         entry->length = cpu_to_le64(length);
 655         entry->type = cpu_to_le32(type);
 656
 657         e820_reserve.count = cpu_to_le32(index);
 658     }
 659
 660     /* new "etc/e820" file -- include ram too */
 661     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
 662     e820_table[e820_entries].address = cpu_to_le64(address);
 663     e820_table[e820_entries].length = cpu_to_le64(length);
 664     e820_table[e820_entries].type = cpu_to_le32(type);
 665     e820_entries++;
 666
 667     return e820_entries;
 668 }
 669
 670 int e820_get_num_entries(void)
 671 {
 672     return e820_entries;
 673 }
 674
 675 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
 676 {
 677     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
 678         *address = le64_to_cpu(e820_table[idx].address);
 679         *length = le64_to_cpu(e820_table[idx].length);
 680         return true;
 681     }
 682     return false;
 683 }
 684
 685 /* Enables contiguous-apic-ID mode, for compatibility */
 686 static bool compat_apic_id_mode;
 687
 688 void enable_compat_apic_id_mode(void)
 689 {
 690     compat_apic_id_mode = true;
 691 }
 692
 693 /* Calculates initial APIC ID for a specific CPU index
 694  *
 695  * Currently we need to be able to calculate the APIC ID from the CPU index
 696  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
 697  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
 698  * all CPUs up to max_cpus.
 699  */
 700 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
 701 {
 702     uint32_t correct_id;
 703     static bool warned;
 704
 705     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
 706     if (compat_apic_id_mode) {
 707         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
 708             error_report("APIC IDs set in compatibility mode, "
 709                          "CPU topology won't match the configuration");
 710             warned = true;
 711         }
 712         return cpu_index;
 713     } else {
 714         return correct_id;
 715     }
 716 }
 717
 718 static void pc_build_smbios(PCMachineState *pcms)
 719 {
 720     uint8_t *smbios_tables, *smbios_anchor;
 721     size_t smbios_tables_len, smbios_anchor_len;
 722     struct smbios_phys_mem_area *mem_array;
 723     unsigned i, array_count;
 724     MachineState *ms = MACHINE(pcms);
 725     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 726
 727     /* tell smbios about cpuid version and features */
 728     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 729
 730     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
 731     if (smbios_tables) {
 732         fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 733                          smbios_tables, smbios_tables_len);
 734     }
 735
 736     /* build the array of physical mem area from e820 table */
 737     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
 738     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
 739         uint64_t addr, len;
 740
 741         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
 742             mem_array[array_count].address = addr;
 743             mem_array[array_count].length = len;
 744             array_count++;
 745         }
 746     }
 747     smbios_get_tables(mem_array, array_count,
 748                       &smbios_tables, &smbios_tables_len,
 749                       &smbios_anchor, &smbios_anchor_len);
 750     g_free(mem_array);
 751
 752     if (smbios_anchor) {
 753         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
 754                         smbios_tables, smbios_tables_len);
 755         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
 756                         smbios_anchor, smbios_anchor_len);
 757     }
 758 }
 759
 760 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
 761 {
 762     FWCfgState *fw_cfg;
 763     uint64_t *numa_fw_cfg;
 764     int i;
 765     const CPUArchIdList *cpus;
 766     MachineClass *mc = MACHINE_GET_CLASS(pcms);
 767
 768     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
 769     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
 770
 771     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 772      *
 773      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 774      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 775      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 776      * for CPU hotplug also uses APIC ID and not "CPU index".
 777      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 778      * but the "limit to the APIC ID values SeaBIOS may see".
 779      *
 780      * So for compatibility reasons with old BIOSes we are stuck with
 781      * "etc/max-cpus" actually being apic_id_limit
 782      */
 783     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
 784     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 785     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 786                      acpi_tables, acpi_tables_len);
 787     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 788
 789     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 790                      &e820_reserve, sizeof(e820_reserve));
 791     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 792                     sizeof(struct e820_entry) * e820_entries);
 793
 794     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 795     /* allocate memory for the NUMA channel: one (64bit) word for the number
 796      * of nodes, one word for each VCPU->node and one word for each node to
 797      * hold the amount of memory.
 798      */
 799     numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
 800     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 801     cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
 802     for (i = 0; i < cpus->len; i++) {
 803         unsigned int apic_id = cpus->cpus[i].arch_id;
 804         assert(apic_id < pcms->apic_id_limit);
 805         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 806     }
 807     for (i = 0; i < nb_numa_nodes; i++) {
 808         numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
 809             cpu_to_le64(numa_info[i].node_mem);
 810     }
 811     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 812                      (1 + pcms->apic_id_limit + nb_numa_nodes) *
 813                      sizeof(*numa_fw_cfg));
 814
 815     return fw_cfg;
 816 }
 817
 818 static long get_file_size(FILE *f)
 819 {
 820     long where, size;
 821
 822     /* XXX: on Unix systems, using fstat() probably makes more sense */
 823
 824     where = ftell(f);
 825     fseek(f, 0, SEEK_END);
 826     size = ftell(f);
 827     fseek(f, where, SEEK_SET);
 828
 829     return size;
 830 }
 831
 832 /* setup_data types */
 833 #define SETUP_NONE     0
 834 #define SETUP_E820_EXT 1
 835 #define SETUP_DTB      2
 836 #define SETUP_PCI      3
 837 #define SETUP_EFI      4
 838
 839 struct setup_data {
 840     uint64_t next;
 841     uint32_t type;
 842     uint32_t len;
 843     uint8_t data[0];
 844 } __attribute__((packed));
 845
 846 static void load_linux(PCMachineState *pcms,
 847                        FWCfgState *fw_cfg)
 848 {
 849     uint16_t protocol;
 850     int setup_size, kernel_size, cmdline_size;
 851     int dtb_size, setup_data_offset;
 852     uint32_t initrd_max;
 853     uint8_t header[8192], *setup, *kernel;
 854     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 855     FILE *f;
 856     char *vmode;
 857     MachineState *machine = MACHINE(pcms);
 858     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 859     struct setup_data *setup_data;
 860     const char *kernel_filename = machine->kernel_filename;
 861     const char *initrd_filename = machine->initrd_filename;
 862     const char *dtb_filename = machine->dtb;
 863     const char *kernel_cmdline = machine->kernel_cmdline;
 864
 865     /* Align to 16 bytes as a paranoia measure */
 866     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 867
 868     /* load the kernel header */
 869     f = fopen(kernel_filename, "rb");
 870     if (!f || !(kernel_size = get_file_size(f)) ||
 871         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 872         MIN(ARRAY_SIZE(header), kernel_size)) {
 873         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 874                 kernel_filename, strerror(errno));
 875         exit(1);
 876     }
 877
 878     /* kernel protocol version */
 879 #if 0
 880     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 881 #endif
 882     if (ldl_p(header+0x202) == 0x53726448) {
 883         protocol = lduw_p(header+0x206);
 884     } else {
 885         /* This looks like a multiboot kernel. If it is, let's stop
 886            treating it like a Linux kernel. */
 887         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 888                            kernel_cmdline, kernel_size, header)) {
 889             return;
 890         }
 891         protocol = 0;
 892     }
 893
 894     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 895         /* Low kernel */
 896         real_addr    = 0x90000;
 897         cmdline_addr = 0x9a000 - cmdline_size;
 898         prot_addr    = 0x10000;
 899     } else if (protocol < 0x202) {
 900         /* High but ancient kernel */
 901         real_addr    = 0x90000;
 902         cmdline_addr = 0x9a000 - cmdline_size;
 903         prot_addr    = 0x100000;
 904     } else {
 905         /* High and recent kernel */
 906         real_addr    = 0x10000;
 907         cmdline_addr = 0x20000;
 908         prot_addr    = 0x100000;
 909     }
 910
 911 #if 0
 912     fprintf(stderr,
 913             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 914             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 915             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 916             real_addr,
 917             cmdline_addr,
 918             prot_addr);
 919 #endif
 920
 921     /* highest address for loading the initrd */
 922     if (protocol >= 0x203) {
 923         initrd_max = ldl_p(header+0x22c);
 924     } else {
 925         initrd_max = 0x37ffffff;
 926     }
 927
 928     if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
 929         initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
 930     }
 931
 932     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 933     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 934     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 935
 936     if (protocol >= 0x202) {
 937         stl_p(header+0x228, cmdline_addr);
 938     } else {
 939         stw_p(header+0x20, 0xA33F);
 940         stw_p(header+0x22, cmdline_addr-real_addr);
 941     }
 942
 943     /* handle vga= parameter */
 944     vmode = strstr(kernel_cmdline, "vga=");
 945     if (vmode) {
 946         unsigned int video_mode;
 947         /* skip "vga=" */
 948         vmode += 4;
 949         if (!strncmp(vmode, "normal", 6)) {
 950             video_mode = 0xffff;
 951         } else if (!strncmp(vmode, "ext", 3)) {
 952             video_mode = 0xfffe;
 953         } else if (!strncmp(vmode, "ask", 3)) {
 954             video_mode = 0xfffd;
 955         } else {
 956             video_mode = strtol(vmode, NULL, 0);
 957         }
 958         stw_p(header+0x1fa, video_mode);
 959     }
 960
 961     /* loader type */
 962     /* High nybble = B reserved for QEMU; low nybble is revision number.
 963        If this code is substantially changed, you may want to consider
 964        incrementing the revision. */
 965     if (protocol >= 0x200) {
 966         header[0x210] = 0xB0;
 967     }
 968     /* heap */
 969     if (protocol >= 0x201) {
 970         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 971         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 972     }
 973
 974     /* load initrd */
 975     if (initrd_filename) {
 976         gsize initrd_size;
 977         gchar *initrd_data;
 978         GError *gerr = NULL;
 979
 980         if (protocol < 0x200) {
 981             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 982             exit(1);
 983         }
 984
 985         if (!g_file_get_contents(initrd_filename, &initrd_data,
 986                                  &initrd_size, &gerr)) {
 987             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
 988                     initrd_filename, gerr->message);
 989             exit(1);
 990         }
 991         if (initrd_size >= initrd_max) {
 992             fprintf(stderr, "qemu: initrd is too large, cannot support."
 993                     "(max: %"PRIu32", need %"PRId64")\n",
 994                     initrd_max, (uint64_t)initrd_size);
 995             exit(1);
 996         }
 997
 998         initrd_addr = (initrd_max-initrd_size) & ~4095;
 999
1000         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1001         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1002         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1003
1004         stl_p(header+0x218, initrd_addr);
1005         stl_p(header+0x21c, initrd_size);
1006     }
1007
1008     /* load kernel and setup */
1009     setup_size = header[0x1f1];
1010     if (setup_size == 0) {
1011         setup_size = 4;
1012     }
1013     setup_size = (setup_size+1)*512;
1014     if (setup_size > kernel_size) {
1015         fprintf(stderr, "qemu: invalid kernel header\n");
1016         exit(1);
1017     }
1018     kernel_size -= setup_size;
1019
1020     setup  = g_malloc(setup_size);
1021     kernel = g_malloc(kernel_size);
1022     fseek(f, 0, SEEK_SET);
1023     if (fread(setup, 1, setup_size, f) != setup_size) {
1024         fprintf(stderr, "fread() failed\n");
1025         exit(1);
1026     }
1027     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1028         fprintf(stderr, "fread() failed\n");
1029         exit(1);
1030     }
1031     fclose(f);
1032
1033     /* append dtb to kernel */
1034     if (dtb_filename) {
1035         if (protocol < 0x209) {
1036             fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1037             exit(1);
1038         }
1039
1040         dtb_size = get_image_size(dtb_filename);
1041         if (dtb_size <= 0) {
1042             fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1043                     dtb_filename, strerror(errno));
1044             exit(1);
1045         }
1046
1047         setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1048         kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1049         kernel = g_realloc(kernel, kernel_size);
1050
1051         stq_p(header+0x250, prot_addr + setup_data_offset);
1052
1053         setup_data = (struct setup_data *)(kernel + setup_data_offset);
1054         setup_data->next = 0;
1055         setup_data->type = cpu_to_le32(SETUP_DTB);
1056         setup_data->len = cpu_to_le32(dtb_size);
1057
1058         load_image_size(dtb_filename, setup_data->data, dtb_size);
1059     }
1060
1061     memcpy(setup, header, MIN(sizeof(header), setup_size));
1062
1063     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1064     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1065     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1066
1067     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1068     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1069     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1070
1071     option_rom[nb_option_roms].bootindex = 0;
1072     option_rom[nb_option_roms].name = "linuxboot.bin";
1073     if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1074         option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1075     }
1076     nb_option_roms++;
1077 }
1078
1079 #define NE2000_NB_MAX 6
1080
1081 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1082                                               0x280, 0x380 };
1083 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1084
1085 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1086 {
1087     static int nb_ne2k = 0;
1088
1089     if (nb_ne2k == NE2000_NB_MAX)
1090         return;
1091     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1092                     ne2000_irq[nb_ne2k], nd);
1093     nb_ne2k++;
1094 }
1095
1096 DeviceState *cpu_get_current_apic(void)
1097 {
1098     if (current_cpu) {
1099         X86CPU *cpu = X86_CPU(current_cpu);
1100         return cpu->apic_state;
1101     } else {
1102         return NULL;
1103     }
1104 }
1105
1106 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1107 {
1108     X86CPU *cpu = opaque;
1109
1110     if (level) {
1111         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1112     }
1113 }
1114
1115 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1116 {
1117     Object *cpu = NULL;
1118     Error *local_err = NULL;
1119
1120     cpu = object_new(typename);
1121
1122     object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1123     object_property_set_bool(cpu, true, "realized", &local_err);
1124
1125     object_unref(cpu);
1126     error_propagate(errp, local_err);
1127 }
1128
1129 void pc_hot_add_cpu(const int64_t id, Error **errp)
1130 {
1131     MachineState *ms = MACHINE(qdev_get_machine());
1132     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1133     Error *local_err = NULL;
1134
1135     if (id < 0) {
1136         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1137         return;
1138     }
1139
1140     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1141         error_setg(errp, "Unable to add CPU: %" PRIi64
1142                    ", resulting APIC ID (%" PRIi64 ") is too large",
1143                    id, apic_id);
1144         return;
1145     }
1146
1147     pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1148     if (local_err) {
1149         error_propagate(errp, local_err);
1150         return;
1151     }
1152 }
1153
1154 void pc_cpus_init(PCMachineState *pcms)
1155 {
1156     int i;
1157     const CPUArchIdList *possible_cpus;
1158     MachineState *ms = MACHINE(pcms);
1159     MachineClass *mc = MACHINE_GET_CLASS(pcms);
1160
1161     /* Calculates the limit to CPU APIC ID values
1162      *
1163      * Limit for the APIC ID value, so that all
1164      * CPU APIC IDs are < pcms->apic_id_limit.
1165      *
1166      * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1167      */
1168     pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1169     possible_cpus = mc->possible_cpu_arch_ids(ms);
1170     for (i = 0; i < smp_cpus; i++) {
1171         pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1172                    &error_fatal);
1173     }
1174 }
1175
1176 static void pc_build_feature_control_file(PCMachineState *pcms)
1177 {
1178     MachineState *ms = MACHINE(pcms);
1179     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1180     CPUX86State *env = &cpu->env;
1181     uint32_t unused, ecx, edx;
1182     uint64_t feature_control_bits = 0;
1183     uint64_t *val;
1184
1185     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1186     if (ecx & CPUID_EXT_VMX) {
1187         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1188     }
1189
1190     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1191         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1192         (env->mcg_cap & MCG_LMCE_P)) {
1193         feature_control_bits |= FEATURE_CONTROL_LMCE;
1194     }
1195
1196     if (!feature_control_bits) {
1197         return;
1198     }
1199
1200     val = g_malloc(sizeof(*val));
1201     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1202     fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1203 }
1204
1205 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1206 {
1207     if (cpus_count > 0xff) {
1208         /* If the number of CPUs can't be represented in 8 bits, the
1209          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1210          * to make old BIOSes fail more predictably.
1211          */
1212         rtc_set_memory(rtc, 0x5f, 0);
1213     } else {
1214         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1215     }
1216 }
1217
1218 static
1219 void pc_machine_done(Notifier *notifier, void *data)
1220 {
1221     PCMachineState *pcms = container_of(notifier,
1222                                         PCMachineState, machine_done);
1223     PCIBus *bus = pcms->bus;
1224
1225     /* set the number of CPUs */
1226     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1227
1228     if (bus) {
1229         int extra_hosts = 0;
1230
1231         QLIST_FOREACH(bus, &bus->child, sibling) {
1232             /* look for expander root buses */
1233             if (pci_bus_is_root(bus)) {
1234                 extra_hosts++;
1235             }
1236         }
1237         if (extra_hosts && pcms->fw_cfg) {
1238             uint64_t *val = g_malloc(sizeof(*val));
1239             *val = cpu_to_le64(extra_hosts);
1240             fw_cfg_add_file(pcms->fw_cfg,
1241                     "etc/extra-pci-roots", val, sizeof(*val));
1242         }
1243     }
1244
1245     acpi_setup();
1246     if (pcms->fw_cfg) {
1247         pc_build_smbios(pcms);
1248         pc_build_feature_control_file(pcms);
1249         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1250         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1251     }
1252
1253     if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1254         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1255
1256         if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1257             iommu->intr_eim != ON_OFF_AUTO_ON) {
1258             error_report("current -smp configuration requires "
1259                          "Extended Interrupt Mode enabled. "
1260                          "You can add an IOMMU using: "
1261                          "-device intel-iommu,intremap=on,eim=on");
1262             exit(EXIT_FAILURE);
1263         }
1264     }
1265 }
1266
1267 void pc_guest_info_init(PCMachineState *pcms)
1268 {
1269     int i;
1270
1271     pcms->apic_xrupt_override = kvm_allows_irq0_override();
1272     pcms->numa_nodes = nb_numa_nodes;
1273     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1274                                     sizeof *pcms->node_mem);
1275     for (i = 0; i < nb_numa_nodes; i++) {
1276         pcms->node_mem[i] = numa_info[i].node_mem;
1277     }
1278
1279     pcms->machine_done.notify = pc_machine_done;
1280     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1281 }
1282
1283 /* setup pci memory address space mapping into system address space */
1284 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1285                             MemoryRegion *pci_address_space)
1286 {
1287     /* Set to lower priority than RAM */
1288     memory_region_add_subregion_overlap(system_memory, 0x0,
1289                                         pci_address_space, -1);
1290 }
1291
1292 void pc_acpi_init(const char *default_dsdt)
1293 {
1294     char *filename;
1295
1296     if (acpi_tables != NULL) {
1297         /* manually set via -acpitable, leave it alone */
1298         return;
1299     }
1300
1301     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1302     if (filename == NULL) {
1303         warn_report("failed to find %s", default_dsdt);
1304     } else {
1305         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1306                                           &error_abort);
1307         Error *err = NULL;
1308
1309         qemu_opt_set(opts, "file", filename, &error_abort);
1310
1311         acpi_table_add_builtin(opts, &err);
1312         if (err) {
1313             warn_reportf_err(err, "failed to load %s: ", filename);
1314         }
1315         g_free(filename);
1316     }
1317 }
1318
1319 void xen_load_linux(PCMachineState *pcms)
1320 {
1321     int i;
1322     FWCfgState *fw_cfg;
1323
1324     assert(MACHINE(pcms)->kernel_filename != NULL);
1325
1326     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1327     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1328     rom_set_fw(fw_cfg);
1329
1330     load_linux(pcms, fw_cfg);
1331     for (i = 0; i < nb_option_roms; i++) {
1332         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1333                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1334                !strcmp(option_rom[i].name, "multiboot.bin"));
1335         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1336     }
1337     pcms->fw_cfg = fw_cfg;
1338 }
1339
1340 void pc_memory_init(PCMachineState *pcms,
1341                     MemoryRegion *system_memory,
1342                     MemoryRegion *rom_memory,
1343                     MemoryRegion **ram_memory)
1344 {
1345     int linux_boot, i;
1346     MemoryRegion *ram, *option_rom_mr;
1347     MemoryRegion *ram_below_4g, *ram_above_4g;
1348     FWCfgState *fw_cfg;
1349     MachineState *machine = MACHINE(pcms);
1350     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1351
1352     assert(machine->ram_size == pcms->below_4g_mem_size +
1353                                 pcms->above_4g_mem_size);
1354
1355     linux_boot = (machine->kernel_filename != NULL);
1356
1357     /* Allocate RAM.  We allocate it as a single memory region and use
1358      * aliases to address portions of it, mostly for backwards compatibility
1359      * with older qemus that used qemu_ram_alloc().
1360      */
1361     ram = g_malloc(sizeof(*ram));
1362     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1363                                          machine->ram_size);
1364     *ram_memory = ram;
1365     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1366     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1367                              0, pcms->below_4g_mem_size);
1368     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1369     e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1370     if (pcms->above_4g_mem_size > 0) {
1371         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1372         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1373                                  pcms->below_4g_mem_size,
1374                                  pcms->above_4g_mem_size);
1375         memory_region_add_subregion(system_memory, 0x100000000ULL,
1376                                     ram_above_4g);
1377         e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1378     }
1379
1380     if (!pcmc->has_reserved_memory &&
1381         (machine->ram_slots ||
1382          (machine->maxram_size > machine->ram_size))) {
1383         MachineClass *mc = MACHINE_GET_CLASS(machine);
1384
1385         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1386                      mc->name);
1387         exit(EXIT_FAILURE);
1388     }
1389
1390     /* always allocate the device memory information */
1391     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1392
1393     /* initialize device memory address space */
1394     if (pcmc->has_reserved_memory &&
1395         (machine->ram_size < machine->maxram_size)) {
1396         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1397
1398         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1399             error_report("unsupported amount of memory slots: %"PRIu64,
1400                          machine->ram_slots);
1401             exit(EXIT_FAILURE);
1402         }
1403
1404         if (QEMU_ALIGN_UP(machine->maxram_size,
1405                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1406             error_report("maximum memory size must by aligned to multiple of "
1407                          "%d bytes", TARGET_PAGE_SIZE);
1408             exit(EXIT_FAILURE);
1409         }
1410
1411         machine->device_memory->base =
1412             ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1413
1414         if (pcmc->enforce_aligned_dimm) {
1415             /* size device region assuming 1G page max alignment per slot */
1416             device_mem_size += (1 * GiB) * machine->ram_slots;
1417         }
1418
1419         if ((machine->device_memory->base + device_mem_size) <
1420             device_mem_size) {
1421             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1422                          machine->maxram_size);
1423             exit(EXIT_FAILURE);
1424         }
1425
1426         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1427                            "device-memory", device_mem_size);
1428         memory_region_add_subregion(system_memory, machine->device_memory->base,
1429                                     &machine->device_memory->mr);
1430     }
1431
1432     /* Initialize PC system firmware */
1433     pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1434
1435     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1436     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1437                            &error_fatal);
1438     if (pcmc->pci_enabled) {
1439         memory_region_set_readonly(option_rom_mr, true);
1440     }
1441     memory_region_add_subregion_overlap(rom_memory,
1442                                         PC_ROM_MIN_VGA,
1443                                         option_rom_mr,
1444                                         1);
1445
1446     fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1447
1448     rom_set_fw(fw_cfg);
1449
1450     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1451         uint64_t *val = g_malloc(sizeof(*val));
1452         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1453         uint64_t res_mem_end = machine->device_memory->base;
1454
1455         if (!pcmc->broken_reserved_end) {
1456             res_mem_end += memory_region_size(&machine->device_memory->mr);
1457         }
1458         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1459         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1460     }
1461
1462     if (linux_boot) {
1463         load_linux(pcms, fw_cfg);
1464     }
1465
1466     for (i = 0; i < nb_option_roms; i++) {
1467         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1468     }
1469     pcms->fw_cfg = fw_cfg;
1470
1471     /* Init default IOAPIC address space */
1472     pcms->ioapic_as = &address_space_memory;
1473 }
1474
1475 /*
1476  * The 64bit pci hole starts after "above 4G RAM" and
1477  * potentially the space reserved for memory hotplug.
1478  */
1479 uint64_t pc_pci_hole64_start(void)
1480 {
1481     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1482     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1483     MachineState *ms = MACHINE(pcms);
1484     uint64_t hole64_start = 0;
1485
1486     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1487         hole64_start = ms->device_memory->base;
1488         if (!pcmc->broken_reserved_end) {
1489             hole64_start += memory_region_size(&ms->device_memory->mr);
1490         }
1491     } else {
1492         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1493     }
1494
1495     return ROUND_UP(hole64_start, 1 * GiB);
1496 }
1497
1498 qemu_irq pc_allocate_cpu_irq(void)
1499 {
1500     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1501 }
1502
1503 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1504 {
1505     DeviceState *dev = NULL;
1506
1507     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1508     if (pci_bus) {
1509         PCIDevice *pcidev = pci_vga_init(pci_bus);
1510         dev = pcidev ? &pcidev->qdev : NULL;
1511     } else if (isa_bus) {
1512         ISADevice *isadev = isa_vga_init(isa_bus);
1513         dev = isadev ? DEVICE(isadev) : NULL;
1514     }
1515     rom_reset_order_override();
1516     return dev;
1517 }
1518
1519 static const MemoryRegionOps ioport80_io_ops = {
1520     .write = ioport80_write,
1521     .read = ioport80_read,
1522     .endianness = DEVICE_NATIVE_ENDIAN,
1523     .impl = {
1524         .min_access_size = 1,
1525         .max_access_size = 1,
1526     },
1527 };
1528
1529 static const MemoryRegionOps ioportF0_io_ops = {
1530     .write = ioportF0_write,
1531     .read = ioportF0_read,
1532     .endianness = DEVICE_NATIVE_ENDIAN,
1533     .impl = {
1534         .min_access_size = 1,
1535         .max_access_size = 1,
1536     },
1537 };
1538
1539 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1540 {
1541     int i;
1542     DriveInfo *fd[MAX_FD];
1543     qemu_irq *a20_line;
1544     ISADevice *i8042, *port92, *vmmouse;
1545
1546     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1547     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1548
1549     for (i = 0; i < MAX_FD; i++) {
1550         fd[i] = drive_get(IF_FLOPPY, 0, i);
1551         create_fdctrl |= !!fd[i];
1552     }
1553     if (create_fdctrl) {
1554         fdctrl_init_isa(isa_bus, fd);
1555     }
1556
1557     i8042 = isa_create_simple(isa_bus, "i8042");
1558     if (!no_vmport) {
1559         vmport_init(isa_bus);
1560         vmmouse = isa_try_create(isa_bus, "vmmouse");
1561     } else {
1562         vmmouse = NULL;
1563     }
1564     if (vmmouse) {
1565         DeviceState *dev = DEVICE(vmmouse);
1566         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1567         qdev_init_nofail(dev);
1568     }
1569     port92 = isa_create_simple(isa_bus, "port92");
1570
1571     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1572     i8042_setup_a20_line(i8042, a20_line[0]);
1573     port92_init(port92, a20_line[1]);
1574     g_free(a20_line);
1575 }
1576
1577 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1578                           ISADevice **rtc_state,
1579                           bool create_fdctrl,
1580                           bool no_vmport,
1581                           bool has_pit,
1582                           uint32_t hpet_irqs)
1583 {
1584     int i;
1585     DeviceState *hpet = NULL;
1586     int pit_isa_irq = 0;
1587     qemu_irq pit_alt_irq = NULL;
1588     qemu_irq rtc_irq = NULL;
1589     ISADevice *pit = NULL;
1590     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1591     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1592
1593     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1594     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1595
1596     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1597     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1598
1599     /*
1600      * Check if an HPET shall be created.
1601      *
1602      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1603      * when the HPET wants to take over. Thus we have to disable the latter.
1604      */
1605     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1606         /* In order to set property, here not using sysbus_try_create_simple */
1607         hpet = qdev_try_create(NULL, TYPE_HPET);
1608         if (hpet) {
1609             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1610              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1611              * IRQ8 and IRQ2.
1612              */
1613             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1614                     HPET_INTCAP, NULL);
1615             if (!compat) {
1616                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1617             }
1618             qdev_init_nofail(hpet);
1619             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1620
1621             for (i = 0; i < GSI_NUM_PINS; i++) {
1622                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1623             }
1624             pit_isa_irq = -1;
1625             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1626             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1627         }
1628     }
1629     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1630
1631     qemu_register_boot_set(pc_boot_set, *rtc_state);
1632
1633     if (!xen_enabled() && has_pit) {
1634         if (kvm_pit_in_kernel()) {
1635             pit = kvm_pit_init(isa_bus, 0x40);
1636         } else {
1637             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1638         }
1639         if (hpet) {
1640             /* connect PIT to output control line of the HPET */
1641             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1642         }
1643         pcspk_init(isa_bus, pit);
1644     }
1645
1646     i8257_dma_init(isa_bus, 0);
1647
1648     /* Super I/O */
1649     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1650 }
1651
1652 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1653 {
1654     int i;
1655
1656     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1657     for (i = 0; i < nb_nics; i++) {
1658         NICInfo *nd = &nd_table[i];
1659         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1660
1661         if (g_str_equal(model, "ne2k_isa")) {
1662             pc_init_ne2k_isa(isa_bus, nd);
1663         } else {
1664             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1665         }
1666     }
1667     rom_reset_order_override();
1668 }
1669
1670 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1671 {
1672     DeviceState *dev;
1673     SysBusDevice *d;
1674     unsigned int i;
1675
1676     if (kvm_ioapic_in_kernel()) {
1677         dev = qdev_create(NULL, "kvm-ioapic");
1678     } else {
1679         dev = qdev_create(NULL, "ioapic");
1680     }
1681     if (parent_name) {
1682         object_property_add_child(object_resolve_path(parent_name, NULL),
1683                                   "ioapic", OBJECT(dev), NULL);
1684     }
1685     qdev_init_nofail(dev);
1686     d = SYS_BUS_DEVICE(dev);
1687     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1688
1689     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1690         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1691     }
1692 }
1693
1694 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1695                                Error **errp)
1696 {
1697     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1698     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1699     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1700     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1701
1702     /*
1703      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1704      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1705      * addition to cover this case.
1706      */
1707     if (!pcms->acpi_dev || !acpi_enabled) {
1708         error_setg(errp,
1709                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1710         return;
1711     }
1712
1713     if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1714         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1715         return;
1716     }
1717
1718     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1719                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1720 }
1721
1722 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1723                            DeviceState *dev, Error **errp)
1724 {
1725     HotplugHandlerClass *hhc;
1726     Error *local_err = NULL;
1727     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1728     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1729
1730     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1731     if (local_err) {
1732         goto out;
1733     }
1734
1735     if (is_nvdimm) {
1736         nvdimm_plug(&pcms->acpi_nvdimm_state);
1737     }
1738
1739     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1740     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1741 out:
1742     error_propagate(errp, local_err);
1743 }
1744
1745 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1746                                      DeviceState *dev, Error **errp)
1747 {
1748     HotplugHandlerClass *hhc;
1749     Error *local_err = NULL;
1750     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1751
1752     /*
1753      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1754      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1755      * addition to cover this case.
1756      */
1757     if (!pcms->acpi_dev || !acpi_enabled) {
1758         error_setg(&local_err,
1759                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1760         goto out;
1761     }
1762
1763     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1764         error_setg(&local_err,
1765                    "nvdimm device hot unplug is not supported yet.");
1766         goto out;
1767     }
1768
1769     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1770     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1771
1772 out:
1773     error_propagate(errp, local_err);
1774 }
1775
1776 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1777                              DeviceState *dev, Error **errp)
1778 {
1779     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1780     HotplugHandlerClass *hhc;
1781     Error *local_err = NULL;
1782
1783     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1784     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1785
1786     if (local_err) {
1787         goto out;
1788     }
1789
1790     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1791     object_unparent(OBJECT(dev));
1792
1793  out:
1794     error_propagate(errp, local_err);
1795 }
1796
1797 static int pc_apic_cmp(const void *a, const void *b)
1798 {
1799    CPUArchId *apic_a = (CPUArchId *)a;
1800    CPUArchId *apic_b = (CPUArchId *)b;
1801
1802    return apic_a->arch_id - apic_b->arch_id;
1803 }
1804
1805 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1806  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1807  * entry corresponding to CPU's apic_id returns NULL.
1808  */
1809 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1810 {
1811     CPUArchId apic_id, *found_cpu;
1812
1813     apic_id.arch_id = id;
1814     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1815         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1816         pc_apic_cmp);
1817     if (found_cpu && idx) {
1818         *idx = found_cpu - ms->possible_cpus->cpus;
1819     }
1820     return found_cpu;
1821 }
1822
1823 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1824                         DeviceState *dev, Error **errp)
1825 {
1826     CPUArchId *found_cpu;
1827     HotplugHandlerClass *hhc;
1828     Error *local_err = NULL;
1829     X86CPU *cpu = X86_CPU(dev);
1830     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1831
1832     if (pcms->acpi_dev) {
1833         hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1834         hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1835         if (local_err) {
1836             goto out;
1837         }
1838     }
1839
1840     /* increment the number of CPUs */
1841     pcms->boot_cpus++;
1842     if (pcms->rtc) {
1843         rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1844     }
1845     if (pcms->fw_cfg) {
1846         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1847     }
1848
1849     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1850     found_cpu->cpu = OBJECT(dev);
1851 out:
1852     error_propagate(errp, local_err);
1853 }
1854 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1855                                      DeviceState *dev, Error **errp)
1856 {
1857     int idx = -1;
1858     HotplugHandlerClass *hhc;
1859     Error *local_err = NULL;
1860     X86CPU *cpu = X86_CPU(dev);
1861     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1862
1863     if (!pcms->acpi_dev) {
1864         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1865         goto out;
1866     }
1867
1868     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1869     assert(idx != -1);
1870     if (idx == 0) {
1871         error_setg(&local_err, "Boot CPU is unpluggable");
1872         goto out;
1873     }
1874
1875     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1876     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1877
1878     if (local_err) {
1879         goto out;
1880     }
1881
1882  out:
1883     error_propagate(errp, local_err);
1884
1885 }
1886
1887 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1888                              DeviceState *dev, Error **errp)
1889 {
1890     CPUArchId *found_cpu;
1891     HotplugHandlerClass *hhc;
1892     Error *local_err = NULL;
1893     X86CPU *cpu = X86_CPU(dev);
1894     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1895
1896     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1897     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1898
1899     if (local_err) {
1900         goto out;
1901     }
1902
1903     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1904     found_cpu->cpu = NULL;
1905     object_unparent(OBJECT(dev));
1906
1907     /* decrement the number of CPUs */
1908     pcms->boot_cpus--;
1909     /* Update the number of CPUs in CMOS */
1910     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1911     fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1912  out:
1913     error_propagate(errp, local_err);
1914 }
1915
1916 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1917                             DeviceState *dev, Error **errp)
1918 {
1919     int idx;
1920     CPUState *cs;
1921     CPUArchId *cpu_slot;
1922     X86CPUTopoInfo topo;
1923     X86CPU *cpu = X86_CPU(dev);
1924     MachineState *ms = MACHINE(hotplug_dev);
1925     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1926
1927     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1928         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1929                    ms->cpu_type);
1930         return;
1931     }
1932
1933     /* if APIC ID is not set, set it based on socket/core/thread properties */
1934     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1935         int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1936
1937         if (cpu->socket_id < 0) {
1938             error_setg(errp, "CPU socket-id is not set");
1939             return;
1940         } else if (cpu->socket_id > max_socket) {
1941             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1942                        cpu->socket_id, max_socket);
1943             return;
1944         }
1945         if (cpu->core_id < 0) {
1946             error_setg(errp, "CPU core-id is not set");
1947             return;
1948         } else if (cpu->core_id > (smp_cores - 1)) {
1949             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1950                        cpu->core_id, smp_cores - 1);
1951             return;
1952         }
1953         if (cpu->thread_id < 0) {
1954             error_setg(errp, "CPU thread-id is not set");
1955             return;
1956         } else if (cpu->thread_id > (smp_threads - 1)) {
1957             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1958                        cpu->thread_id, smp_threads - 1);
1959             return;
1960         }
1961
1962         topo.pkg_id = cpu->socket_id;
1963         topo.core_id = cpu->core_id;
1964         topo.smt_id = cpu->thread_id;
1965         cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1966     }
1967
1968     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1969     if (!cpu_slot) {
1970         MachineState *ms = MACHINE(pcms);
1971
1972         x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1973         error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1974                   " APIC ID %" PRIu32 ", valid index range 0:%d",
1975                    topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1976                    ms->possible_cpus->len - 1);
1977         return;
1978     }
1979
1980     if (cpu_slot->cpu) {
1981         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1982                    idx, cpu->apic_id);
1983         return;
1984     }
1985
1986     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1987      * so that machine_query_hotpluggable_cpus would show correct values
1988      */
1989     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1990      * once -smp refactoring is complete and there will be CPU private
1991      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1992     x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1993     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1994         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1995             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1996         return;
1997     }
1998     cpu->socket_id = topo.pkg_id;
1999
2000     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2001         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2002             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2003         return;
2004     }
2005     cpu->core_id = topo.core_id;
2006
2007     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2008         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2009             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2010         return;
2011     }
2012     cpu->thread_id = topo.smt_id;
2013
2014     if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2015         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2016         return;
2017     }
2018
2019     cs = CPU(cpu);
2020     cs->cpu_index = idx;
2021
2022     numa_cpu_pre_plug(cpu_slot, dev, errp);
2023 }
2024
2025 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2026                                           DeviceState *dev, Error **errp)
2027 {
2028     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2029         pc_memory_pre_plug(hotplug_dev, dev, errp);
2030     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2031         pc_cpu_pre_plug(hotplug_dev, dev, errp);
2032     }
2033 }
2034
2035 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2036                                       DeviceState *dev, Error **errp)
2037 {
2038     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2039         pc_memory_plug(hotplug_dev, dev, errp);
2040     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2041         pc_cpu_plug(hotplug_dev, dev, errp);
2042     }
2043 }
2044
2045 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2046                                                 DeviceState *dev, Error **errp)
2047 {
2048     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2049         pc_memory_unplug_request(hotplug_dev, dev, errp);
2050     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2051         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2052     } else {
2053         error_setg(errp, "acpi: device unplug request for not supported device"
2054                    " type: %s", object_get_typename(OBJECT(dev)));
2055     }
2056 }
2057
2058 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2059                                         DeviceState *dev, Error **errp)
2060 {
2061     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2062         pc_memory_unplug(hotplug_dev, dev, errp);
2063     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2064         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2065     } else {
2066         error_setg(errp, "acpi: device unplug for not supported device"
2067                    " type: %s", object_get_typename(OBJECT(dev)));
2068     }
2069 }
2070
2071 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2072                                              DeviceState *dev)
2073 {
2074     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2075         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2076         return HOTPLUG_HANDLER(machine);
2077     }
2078
2079     return NULL;
2080 }
2081
2082 static void
2083 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2084                                          const char *name, void *opaque,
2085                                          Error **errp)
2086 {
2087     MachineState *ms = MACHINE(obj);
2088     int64_t value = memory_region_size(&ms->device_memory->mr);
2089
2090     visit_type_int(v, name, &value, errp);
2091 }
2092
2093 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2094                                             const char *name, void *opaque,
2095                                             Error **errp)
2096 {
2097     PCMachineState *pcms = PC_MACHINE(obj);
2098     uint64_t value = pcms->max_ram_below_4g;
2099
2100     visit_type_size(v, name, &value, errp);
2101 }
2102
2103 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2104                                             const char *name, void *opaque,
2105                                             Error **errp)
2106 {
2107     PCMachineState *pcms = PC_MACHINE(obj);
2108     Error *error = NULL;
2109     uint64_t value;
2110
2111     visit_type_size(v, name, &value, &error);
2112     if (error) {
2113         error_propagate(errp, error);
2114         return;
2115     }
2116     if (value > 4 * GiB) {
2117         error_setg(&error,
2118                    "Machine option 'max-ram-below-4g=%"PRIu64
2119                    "' expects size less than or equal to 4G", value);
2120         error_propagate(errp, error);
2121         return;
2122     }
2123
2124     if (value < 1 * MiB) {
2125         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2126                     "BIOS may not work with less than 1MiB", value);
2127     }
2128
2129     pcms->max_ram_below_4g = value;
2130 }
2131
2132 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2133                                   void *opaque, Error **errp)
2134 {
2135     PCMachineState *pcms = PC_MACHINE(obj);
2136     OnOffAuto vmport = pcms->vmport;
2137
2138     visit_type_OnOffAuto(v, name, &vmport, errp);
2139 }
2140
2141 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2142                                   void *opaque, Error **errp)
2143 {
2144     PCMachineState *pcms = PC_MACHINE(obj);
2145
2146     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2147 }
2148
2149 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2150 {
2151     bool smm_available = false;
2152
2153     if (pcms->smm == ON_OFF_AUTO_OFF) {
2154         return false;
2155     }
2156
2157     if (tcg_enabled() || qtest_enabled()) {
2158         smm_available = true;
2159     } else if (kvm_enabled()) {
2160         smm_available = kvm_has_smm();
2161     }
2162
2163     if (smm_available) {
2164         return true;
2165     }
2166
2167     if (pcms->smm == ON_OFF_AUTO_ON) {
2168         error_report("System Management Mode not supported by this hypervisor.");
2169         exit(1);
2170     }
2171     return false;
2172 }
2173
2174 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2175                                void *opaque, Error **errp)
2176 {
2177     PCMachineState *pcms = PC_MACHINE(obj);
2178     OnOffAuto smm = pcms->smm;
2179
2180     visit_type_OnOffAuto(v, name, &smm, errp);
2181 }
2182
2183 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2184                                void *opaque, Error **errp)
2185 {
2186     PCMachineState *pcms = PC_MACHINE(obj);
2187
2188     visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2189 }
2190
2191 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2192 {
2193     PCMachineState *pcms = PC_MACHINE(obj);
2194
2195     return pcms->acpi_nvdimm_state.is_enabled;
2196 }
2197
2198 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2199 {
2200     PCMachineState *pcms = PC_MACHINE(obj);
2201
2202     pcms->acpi_nvdimm_state.is_enabled = value;
2203 }
2204
2205 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2206 {
2207     PCMachineState *pcms = PC_MACHINE(obj);
2208
2209     return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2210 }
2211
2212 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2213                                                Error **errp)
2214 {
2215     PCMachineState *pcms = PC_MACHINE(obj);
2216     AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2217
2218     if (strcmp(value, "cpu") == 0)
2219         nvdimm_state->persistence = 3;
2220     else if (strcmp(value, "mem-ctrl") == 0)
2221         nvdimm_state->persistence = 2;
2222     else {
2223         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2224                    value);
2225         return;
2226     }
2227
2228     g_free(nvdimm_state->persistence_string);
2229     nvdimm_state->persistence_string = g_strdup(value);
2230 }
2231
2232 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2233 {
2234     PCMachineState *pcms = PC_MACHINE(obj);
2235
2236     return pcms->smbus_enabled;
2237 }
2238
2239 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2240 {
2241     PCMachineState *pcms = PC_MACHINE(obj);
2242
2243     pcms->smbus_enabled = value;
2244 }
2245
2246 static bool pc_machine_get_sata(Object *obj, Error **errp)
2247 {
2248     PCMachineState *pcms = PC_MACHINE(obj);
2249
2250     return pcms->sata_enabled;
2251 }
2252
2253 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2254 {
2255     PCMachineState *pcms = PC_MACHINE(obj);
2256
2257     pcms->sata_enabled = value;
2258 }
2259
2260 static bool pc_machine_get_pit(Object *obj, Error **errp)
2261 {
2262     PCMachineState *pcms = PC_MACHINE(obj);
2263
2264     return pcms->pit_enabled;
2265 }
2266
2267 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2268 {
2269     PCMachineState *pcms = PC_MACHINE(obj);
2270
2271     pcms->pit_enabled = value;
2272 }
2273
2274 static void pc_machine_initfn(Object *obj)
2275 {
2276     PCMachineState *pcms = PC_MACHINE(obj);
2277
2278     pcms->max_ram_below_4g = 0; /* use default */
2279     pcms->smm = ON_OFF_AUTO_AUTO;
2280     pcms->vmport = ON_OFF_AUTO_AUTO;
2281     /* nvdimm is disabled on default. */
2282     pcms->acpi_nvdimm_state.is_enabled = false;
2283     /* acpi build is enabled by default if machine supports it */
2284     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2285     pcms->smbus_enabled = true;
2286     pcms->sata_enabled = true;
2287     pcms->pit_enabled = true;
2288 }
2289
2290 static void pc_machine_reset(void)
2291 {
2292     CPUState *cs;
2293     X86CPU *cpu;
2294
2295     qemu_devices_reset();
2296
2297     /* Reset APIC after devices have been reset to cancel
2298      * any changes that qemu_devices_reset() might have done.
2299      */
2300     CPU_FOREACH(cs) {
2301         cpu = X86_CPU(cs);
2302
2303         if (cpu->apic_state) {
2304             device_reset(cpu->apic_state);
2305         }
2306     }
2307 }
2308
2309 static CpuInstanceProperties
2310 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2311 {
2312     MachineClass *mc = MACHINE_GET_CLASS(ms);
2313     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2314
2315     assert(cpu_index < possible_cpus->len);
2316     return possible_cpus->cpus[cpu_index].props;
2317 }
2318
2319 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2320 {
2321    X86CPUTopoInfo topo;
2322
2323    assert(idx < ms->possible_cpus->len);
2324    x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2325                             smp_cores, smp_threads, &topo);
2326    return topo.pkg_id % nb_numa_nodes;
2327 }
2328
2329 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2330 {
2331     int i;
2332
2333     if (ms->possible_cpus) {
2334         /*
2335          * make sure that max_cpus hasn't changed since the first use, i.e.
2336          * -smp hasn't been parsed after it
2337         */
2338         assert(ms->possible_cpus->len == max_cpus);
2339         return ms->possible_cpus;
2340     }
2341
2342     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2343                                   sizeof(CPUArchId) * max_cpus);
2344     ms->possible_cpus->len = max_cpus;
2345     for (i = 0; i < ms->possible_cpus->len; i++) {
2346         X86CPUTopoInfo topo;
2347
2348         ms->possible_cpus->cpus[i].type = ms->cpu_type;
2349         ms->possible_cpus->cpus[i].vcpus_count = 1;
2350         ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2351         x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2352                                  smp_cores, smp_threads, &topo);
2353         ms->possible_cpus->cpus[i].props.has_socket_id = true;
2354         ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2355         ms->possible_cpus->cpus[i].props.has_core_id = true;
2356         ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2357         ms->possible_cpus->cpus[i].props.has_thread_id = true;
2358         ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2359     }
2360     return ms->possible_cpus;
2361 }
2362
2363 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2364 {
2365     /* cpu index isn't used */
2366     CPUState *cs;
2367
2368     CPU_FOREACH(cs) {
2369         X86CPU *cpu = X86_CPU(cs);
2370
2371         if (!cpu->apic_state) {
2372             cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2373         } else {
2374             apic_deliver_nmi(cpu->apic_state);
2375         }
2376     }
2377 }
2378
2379 static void pc_machine_class_init(ObjectClass *oc, void *data)
2380 {
2381     MachineClass *mc = MACHINE_CLASS(oc);
2382     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2383     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2384     NMIClass *nc = NMI_CLASS(oc);
2385
2386     pcmc->pci_enabled = true;
2387     pcmc->has_acpi_build = true;
2388     pcmc->rsdp_in_ram = true;
2389     pcmc->smbios_defaults = true;
2390     pcmc->smbios_uuid_encoded = true;
2391     pcmc->gigabyte_align = true;
2392     pcmc->has_reserved_memory = true;
2393     pcmc->kvmclock_enabled = true;
2394     pcmc->enforce_aligned_dimm = true;
2395     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2396      * to be used at the moment, 32K should be enough for a while.  */
2397     pcmc->acpi_data_size = 0x20000 + 0x8000;
2398     pcmc->save_tsc_khz = true;
2399     pcmc->linuxboot_dma_enabled = true;
2400     assert(!mc->get_hotplug_handler);
2401     mc->get_hotplug_handler = pc_get_hotpug_handler;
2402     mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2403     mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2404     mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2405     mc->auto_enable_numa_with_memhp = true;
2406     mc->has_hotpluggable_cpus = true;
2407     mc->default_boot_order = "cad";
2408     mc->hot_add_cpu = pc_hot_add_cpu;
2409     mc->block_default_type = IF_IDE;
2410     mc->max_cpus = 255;
2411     mc->reset = pc_machine_reset;
2412     hc->pre_plug = pc_machine_device_pre_plug_cb;
2413     hc->plug = pc_machine_device_plug_cb;
2414     hc->unplug_request = pc_machine_device_unplug_request_cb;
2415     hc->unplug = pc_machine_device_unplug_cb;
2416     nc->nmi_monitor_handler = x86_nmi;
2417     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2418
2419     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2420         pc_machine_get_device_memory_region_size, NULL,
2421         NULL, NULL, &error_abort);
2422
2423     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2424         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2425         NULL, NULL, &error_abort);
2426
2427     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2428         "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2429
2430     object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2431         pc_machine_get_smm, pc_machine_set_smm,
2432         NULL, NULL, &error_abort);
2433     object_class_property_set_description(oc, PC_MACHINE_SMM,
2434         "Enable SMM (pc & q35)", &error_abort);
2435
2436     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2437         pc_machine_get_vmport, pc_machine_set_vmport,
2438         NULL, NULL, &error_abort);
2439     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2440         "Enable vmport (pc & q35)", &error_abort);
2441
2442     object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2443         pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2444
2445     object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2446         pc_machine_get_nvdimm_persistence,
2447         pc_machine_set_nvdimm_persistence, &error_abort);
2448
2449     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2450         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2451
2452     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2453         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2454
2455     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2456         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2457 }
2458
2459 static const TypeInfo pc_machine_info = {
2460     .name = TYPE_PC_MACHINE,
2461     .parent = TYPE_MACHINE,
2462     .abstract = true,
2463     .instance_size = sizeof(PCMachineState),
2464     .instance_init = pc_machine_initfn,
2465     .class_size = sizeof(PCMachineClass),
2466     .class_init = pc_machine_class_init,
2467     .interfaces = (InterfaceInfo[]) {
2468          { TYPE_HOTPLUG_HANDLER },
2469          { TYPE_NMI },
2470          { }
2471     },
2472 };
2473
2474 static void pc_machine_register_types(void)
2475 {
2476     type_register_static(&pc_machine_info);
2477 }
2478
2479 type_init(pc_machine_register_types)