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[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "hw/i386/vmport.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide/internal.h"
37 #include "hw/ide/isa.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/intc/ioapic.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
53 #include "hw/irq.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-md-pci.h"
92 #include "hw/i386/kvm/xen_overlay.h"
93 #include "hw/i386/kvm/xen_evtchn.h"
94 #include "hw/i386/kvm/xen_gnttab.h"
95 #include "hw/i386/kvm/xen_xenstore.h"
96 #include "sysemu/replay.h"
97 #include "target/i386/cpu.h"
98 #include "e820_memory_layout.h"
99 #include "fw_cfg.h"
100 #include "trace.h"
101 #include CONFIG_DEVICES
102
103 #ifdef CONFIG_XEN_EMU
104 #include "hw/xen/xen-legacy-backend.h"
105 #include "hw/xen/xen-bus.h"
106 #endif
107
108 /*
109 * Helper for setting model-id for CPU models that changed model-id
110 * depending on QEMU versions up to QEMU 2.4.
111 */
112 #define PC_CPU_MODEL_IDS(v) \
113 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
114 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
115 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
116
117 GlobalProperty pc_compat_8_1[] = {};
118 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
119
120 GlobalProperty pc_compat_8_0[] = {
121 { "virtio-mem", "unplugged-inaccessible", "auto" },
122 };
123 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
124
125 GlobalProperty pc_compat_7_2[] = {
126 { "ICH9-LPC", "noreboot", "true" },
127 };
128 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
129
130 GlobalProperty pc_compat_7_1[] = {};
131 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
132
133 GlobalProperty pc_compat_7_0[] = {};
134 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
135
136 GlobalProperty pc_compat_6_2[] = {
137 { "virtio-mem", "unplugged-inaccessible", "off" },
138 };
139 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
140
141 GlobalProperty pc_compat_6_1[] = {
142 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
143 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
144 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
145 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
146 };
147 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
148
149 GlobalProperty pc_compat_6_0[] = {
150 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
151 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
152 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
153 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
154 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
155 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
156 };
157 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
158
159 GlobalProperty pc_compat_5_2[] = {
160 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
161 };
162 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
163
164 GlobalProperty pc_compat_5_1[] = {
165 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
166 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
167 };
168 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
169
170 GlobalProperty pc_compat_5_0[] = {
171 };
172 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
173
174 GlobalProperty pc_compat_4_2[] = {
175 { "mch", "smbase-smram", "off" },
176 };
177 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
178
179 GlobalProperty pc_compat_4_1[] = {};
180 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
181
182 GlobalProperty pc_compat_4_0[] = {};
183 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
184
185 GlobalProperty pc_compat_3_1[] = {
186 { "intel-iommu", "dma-drain", "off" },
187 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
188 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
189 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
190 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
191 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
192 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
193 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
194 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
195 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
196 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
197 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
198 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
199 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
200 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
201 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
202 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
203 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
204 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
205 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
206 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
207 };
208 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
209
210 GlobalProperty pc_compat_3_0[] = {
211 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
212 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
213 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
214 };
215 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
216
217 GlobalProperty pc_compat_2_12[] = {
218 { TYPE_X86_CPU, "legacy-cache", "on" },
219 { TYPE_X86_CPU, "topoext", "off" },
220 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
221 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
222 };
223 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
224
225 GlobalProperty pc_compat_2_11[] = {
226 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
227 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
228 };
229 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
230
231 GlobalProperty pc_compat_2_10[] = {
232 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
233 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
234 { "q35-pcihost", "x-pci-hole64-fix", "off" },
235 };
236 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
237
238 GlobalProperty pc_compat_2_9[] = {
239 { "mch", "extended-tseg-mbytes", "0" },
240 };
241 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
242
243 GlobalProperty pc_compat_2_8[] = {
244 { TYPE_X86_CPU, "tcg-cpuid", "off" },
245 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
246 { "ICH9-LPC", "x-smi-broadcast", "off" },
247 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
248 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
249 };
250 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
251
252 GlobalProperty pc_compat_2_7[] = {
253 { TYPE_X86_CPU, "l3-cache", "off" },
254 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
255 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
256 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
257 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
258 { "isa-pcspk", "migrate", "off" },
259 };
260 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
261
262 GlobalProperty pc_compat_2_6[] = {
263 { TYPE_X86_CPU, "cpuid-0xb", "off" },
264 { "vmxnet3", "romfile", "" },
265 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
266 { "apic-common", "legacy-instance-id", "on", }
267 };
268 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
269
270 GlobalProperty pc_compat_2_5[] = {};
271 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
272
273 GlobalProperty pc_compat_2_4[] = {
274 PC_CPU_MODEL_IDS("2.4.0")
275 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
276 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
277 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
278 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
279 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
280 { TYPE_X86_CPU, "check", "off" },
281 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
282 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
283 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
284 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
285 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
286 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
287 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
288 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
289 };
290 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
291
292 GlobalProperty pc_compat_2_3[] = {
293 PC_CPU_MODEL_IDS("2.3.0")
294 { TYPE_X86_CPU, "arat", "off" },
295 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
296 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
297 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
298 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
299 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
300 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
301 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
302 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
303 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
304 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
305 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
306 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
307 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
308 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
309 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
310 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
311 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
312 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
313 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
314 };
315 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
316
317 GlobalProperty pc_compat_2_2[] = {
318 PC_CPU_MODEL_IDS("2.2.0")
319 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
320 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
321 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
322 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
323 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
324 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
325 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
326 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
327 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
328 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
329 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
330 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
331 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
332 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
333 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
334 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
335 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
336 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
337 };
338 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
339
340 GlobalProperty pc_compat_2_1[] = {
341 PC_CPU_MODEL_IDS("2.1.0")
342 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
343 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
344 };
345 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
346
347 GlobalProperty pc_compat_2_0[] = {
348 PC_CPU_MODEL_IDS("2.0.0")
349 { "virtio-scsi-pci", "any_layout", "off" },
350 { "PIIX4_PM", "memory-hotplug-support", "off" },
351 { "apic", "version", "0x11" },
352 { "nec-usb-xhci", "superspeed-ports-first", "off" },
353 { "nec-usb-xhci", "force-pcie-endcap", "on" },
354 { "pci-serial", "prog_if", "0" },
355 { "pci-serial-2x", "prog_if", "0" },
356 { "pci-serial-4x", "prog_if", "0" },
357 { "virtio-net-pci", "guest_announce", "off" },
358 { "ICH9-LPC", "memory-hotplug-support", "off" },
359 };
360 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
361
362 GlobalProperty pc_compat_1_7[] = {
363 PC_CPU_MODEL_IDS("1.7.0")
364 { TYPE_USB_DEVICE, "msos-desc", "no" },
365 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
366 { "hpet", HPET_INTCAP, "4" },
367 };
368 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
369
370 GlobalProperty pc_compat_1_6[] = {
371 PC_CPU_MODEL_IDS("1.6.0")
372 { "e1000", "mitigation", "off" },
373 { "qemu64-" TYPE_X86_CPU, "model", "2" },
374 { "qemu32-" TYPE_X86_CPU, "model", "3" },
375 { "i440FX-pcihost", "short_root_bus", "1" },
376 { "q35-pcihost", "short_root_bus", "1" },
377 };
378 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
379
380 GlobalProperty pc_compat_1_5[] = {
381 PC_CPU_MODEL_IDS("1.5.0")
382 { "Conroe-" TYPE_X86_CPU, "model", "2" },
383 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
384 { "Penryn-" TYPE_X86_CPU, "model", "2" },
385 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
386 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
387 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
388 { "virtio-net-pci", "any_layout", "off" },
389 { TYPE_X86_CPU, "pmu", "on" },
390 { "i440FX-pcihost", "short_root_bus", "0" },
391 { "q35-pcihost", "short_root_bus", "0" },
392 };
393 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
394
395 GlobalProperty pc_compat_1_4[] = {
396 PC_CPU_MODEL_IDS("1.4.0")
397 { "scsi-hd", "discard_granularity", "0" },
398 { "scsi-cd", "discard_granularity", "0" },
399 { "ide-hd", "discard_granularity", "0" },
400 { "ide-cd", "discard_granularity", "0" },
401 { "virtio-blk-pci", "discard_granularity", "0" },
402 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
403 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
404 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
405 { "e1000", "romfile", "pxe-e1000.rom" },
406 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
407 { "pcnet", "romfile", "pxe-pcnet.rom" },
408 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
409 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
410 { "486-" TYPE_X86_CPU, "model", "0" },
411 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
412 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
413 };
414 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
415
416 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
417 {
418 GSIState *s;
419
420 s = g_new0(GSIState, 1);
421 if (kvm_ioapic_in_kernel()) {
422 kvm_pc_setup_irq_routing(pci_enabled);
423 }
424 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
425
426 return s;
427 }
428
429 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
430 unsigned size)
431 {
432 }
433
434 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
435 {
436 return 0xffffffffffffffffULL;
437 }
438
439 /* MS-DOS compatibility mode FPU exception support */
440 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
441 unsigned size)
442 {
443 if (tcg_enabled()) {
444 cpu_set_ignne();
445 }
446 }
447
448 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
449 {
450 return 0xffffffffffffffffULL;
451 }
452
453 /* PC cmos mappings */
454
455 #define REG_EQUIPMENT_BYTE 0x14
456
457 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
458 int16_t cylinders, int8_t heads, int8_t sectors)
459 {
460 mc146818rtc_set_cmos_data(s, type_ofs, 47);
461 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
462 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
463 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
464 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
465 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
466 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
467 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
468 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
469 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
470 }
471
472 /* convert boot_device letter to something recognizable by the bios */
473 static int boot_device2nibble(char boot_device)
474 {
475 switch(boot_device) {
476 case 'a':
477 case 'b':
478 return 0x01; /* floppy boot */
479 case 'c':
480 return 0x02; /* hard drive boot */
481 case 'd':
482 return 0x03; /* CD-ROM boot */
483 case 'n':
484 return 0x04; /* Network boot */
485 }
486 return 0;
487 }
488
489 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
490 Error **errp)
491 {
492 #define PC_MAX_BOOT_DEVICES 3
493 int nbds, bds[3] = { 0, };
494 int i;
495
496 nbds = strlen(boot_device);
497 if (nbds > PC_MAX_BOOT_DEVICES) {
498 error_setg(errp, "Too many boot devices for PC");
499 return;
500 }
501 for (i = 0; i < nbds; i++) {
502 bds[i] = boot_device2nibble(boot_device[i]);
503 if (bds[i] == 0) {
504 error_setg(errp, "Invalid boot device for PC: '%c'",
505 boot_device[i]);
506 return;
507 }
508 }
509 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
510 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
511 }
512
513 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
514 {
515 set_boot_dev(opaque, boot_device, errp);
516 }
517
518 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
519 {
520 int val, nb, i;
521 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
522 FLOPPY_DRIVE_TYPE_NONE };
523
524 /* floppy type */
525 if (floppy) {
526 for (i = 0; i < 2; i++) {
527 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
528 }
529 }
530 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
531 cmos_get_fd_drive_type(fd_type[1]);
532 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
533
534 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
535 nb = 0;
536 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
537 nb++;
538 }
539 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
540 nb++;
541 }
542 switch (nb) {
543 case 0:
544 break;
545 case 1:
546 val |= 0x01; /* 1 drive, ready for boot */
547 break;
548 case 2:
549 val |= 0x41; /* 2 drives, ready for boot */
550 break;
551 }
552 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
553 }
554
555 typedef struct pc_cmos_init_late_arg {
556 MC146818RtcState *rtc_state;
557 BusState *idebus[2];
558 } pc_cmos_init_late_arg;
559
560 typedef struct check_fdc_state {
561 ISADevice *floppy;
562 bool multiple;
563 } CheckFdcState;
564
565 static int check_fdc(Object *obj, void *opaque)
566 {
567 CheckFdcState *state = opaque;
568 Object *fdc;
569 uint32_t iobase;
570 Error *local_err = NULL;
571
572 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
573 if (!fdc) {
574 return 0;
575 }
576
577 iobase = object_property_get_uint(obj, "iobase", &local_err);
578 if (local_err || iobase != 0x3f0) {
579 error_free(local_err);
580 return 0;
581 }
582
583 if (state->floppy) {
584 state->multiple = true;
585 } else {
586 state->floppy = ISA_DEVICE(obj);
587 }
588 return 0;
589 }
590
591 static const char * const fdc_container_path[] = {
592 "/unattached", "/peripheral", "/peripheral-anon"
593 };
594
595 /*
596 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
597 * and ACPI objects.
598 */
599 static ISADevice *pc_find_fdc0(void)
600 {
601 int i;
602 Object *container;
603 CheckFdcState state = { 0 };
604
605 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
606 container = container_get(qdev_get_machine(), fdc_container_path[i]);
607 object_child_foreach(container, check_fdc, &state);
608 }
609
610 if (state.multiple) {
611 warn_report("multiple floppy disk controllers with "
612 "iobase=0x3f0 have been found");
613 error_printf("the one being picked for CMOS setup might not reflect "
614 "your intent");
615 }
616
617 return state.floppy;
618 }
619
620 static void pc_cmos_init_late(void *opaque)
621 {
622 pc_cmos_init_late_arg *arg = opaque;
623 MC146818RtcState *s = arg->rtc_state;
624 int16_t cylinders;
625 int8_t heads, sectors;
626 int val;
627 int i, trans;
628
629 val = 0;
630 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
631 &cylinders, &heads, &sectors) >= 0) {
632 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
633 val |= 0xf0;
634 }
635 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
636 &cylinders, &heads, &sectors) >= 0) {
637 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
638 val |= 0x0f;
639 }
640 mc146818rtc_set_cmos_data(s, 0x12, val);
641
642 val = 0;
643 for (i = 0; i < 4; i++) {
644 /* NOTE: ide_get_geometry() returns the physical
645 geometry. It is always such that: 1 <= sects <= 63, 1
646 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
647 geometry can be different if a translation is done. */
648 if (arg->idebus[i / 2] &&
649 ide_get_geometry(arg->idebus[i / 2], i % 2,
650 &cylinders, &heads, &sectors) >= 0) {
651 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
652 assert((trans & ~3) == 0);
653 val |= trans << (i * 2);
654 }
655 }
656 mc146818rtc_set_cmos_data(s, 0x39, val);
657
658 pc_cmos_init_floppy(s, pc_find_fdc0());
659
660 qemu_unregister_reset(pc_cmos_init_late, opaque);
661 }
662
663 void pc_cmos_init(PCMachineState *pcms,
664 BusState *idebus0, BusState *idebus1,
665 ISADevice *rtc)
666 {
667 int val;
668 static pc_cmos_init_late_arg arg;
669 X86MachineState *x86ms = X86_MACHINE(pcms);
670 MC146818RtcState *s = MC146818_RTC(rtc);
671
672 /* various important CMOS locations needed by PC/Bochs bios */
673
674 /* memory size */
675 /* base memory (first MiB) */
676 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
677 mc146818rtc_set_cmos_data(s, 0x15, val);
678 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
679 /* extended memory (next 64MiB) */
680 if (x86ms->below_4g_mem_size > 1 * MiB) {
681 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
682 } else {
683 val = 0;
684 }
685 if (val > 65535)
686 val = 65535;
687 mc146818rtc_set_cmos_data(s, 0x17, val);
688 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
689 mc146818rtc_set_cmos_data(s, 0x30, val);
690 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
691 /* memory between 16MiB and 4GiB */
692 if (x86ms->below_4g_mem_size > 16 * MiB) {
693 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
694 } else {
695 val = 0;
696 }
697 if (val > 65535)
698 val = 65535;
699 mc146818rtc_set_cmos_data(s, 0x34, val);
700 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
701 /* memory above 4GiB */
702 val = x86ms->above_4g_mem_size / 65536;
703 mc146818rtc_set_cmos_data(s, 0x5b, val);
704 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
705 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
706
707 object_property_add_link(OBJECT(pcms), "rtc_state",
708 TYPE_ISA_DEVICE,
709 (Object **)&x86ms->rtc,
710 object_property_allow_set_link,
711 OBJ_PROP_LINK_STRONG);
712 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
713 &error_abort);
714
715 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
716
717 val = 0;
718 val |= 0x02; /* FPU is there */
719 val |= 0x04; /* PS/2 mouse installed */
720 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
721
722 /* hard drives and FDC */
723 arg.rtc_state = s;
724 arg.idebus[0] = idebus0;
725 arg.idebus[1] = idebus1;
726 qemu_register_reset(pc_cmos_init_late, &arg);
727 }
728
729 static void handle_a20_line_change(void *opaque, int irq, int level)
730 {
731 X86CPU *cpu = opaque;
732
733 /* XXX: send to all CPUs ? */
734 /* XXX: add logic to handle multiple A20 line sources */
735 x86_cpu_set_a20(cpu, level);
736 }
737
738 #define NE2000_NB_MAX 6
739
740 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
741 0x280, 0x380 };
742 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
743
744 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
745 {
746 static int nb_ne2k = 0;
747
748 if (nb_ne2k == NE2000_NB_MAX)
749 return;
750 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
751 ne2000_irq[nb_ne2k], nd);
752 nb_ne2k++;
753 }
754
755 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
756 {
757 X86CPU *cpu = opaque;
758
759 if (level) {
760 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
761 }
762 }
763
764 static
765 void pc_machine_done(Notifier *notifier, void *data)
766 {
767 PCMachineState *pcms = container_of(notifier,
768 PCMachineState, machine_done);
769 X86MachineState *x86ms = X86_MACHINE(pcms);
770
771 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
772 &error_fatal);
773
774 if (pcms->cxl_devices_state.is_enabled) {
775 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
776 }
777
778 /* set the number of CPUs */
779 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
780
781 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
782
783 acpi_setup();
784 if (x86ms->fw_cfg) {
785 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
786 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
787 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
788 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
789 }
790 }
791
792 void pc_guest_info_init(PCMachineState *pcms)
793 {
794 X86MachineState *x86ms = X86_MACHINE(pcms);
795
796 x86ms->apic_xrupt_override = true;
797 pcms->machine_done.notify = pc_machine_done;
798 qemu_add_machine_init_done_notifier(&pcms->machine_done);
799 }
800
801 /* setup pci memory address space mapping into system address space */
802 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
803 MemoryRegion *pci_address_space)
804 {
805 /* Set to lower priority than RAM */
806 memory_region_add_subregion_overlap(system_memory, 0x0,
807 pci_address_space, -1);
808 }
809
810 void xen_load_linux(PCMachineState *pcms)
811 {
812 int i;
813 FWCfgState *fw_cfg;
814 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
815 X86MachineState *x86ms = X86_MACHINE(pcms);
816
817 assert(MACHINE(pcms)->kernel_filename != NULL);
818
819 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
820 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
821 rom_set_fw(fw_cfg);
822
823 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
824 pcmc->pvh_enabled);
825 for (i = 0; i < nb_option_roms; i++) {
826 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
827 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
828 !strcmp(option_rom[i].name, "pvh.bin") ||
829 !strcmp(option_rom[i].name, "multiboot.bin") ||
830 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
831 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
832 }
833 x86ms->fw_cfg = fw_cfg;
834 }
835
836 #define PC_ROM_MIN_VGA 0xc0000
837 #define PC_ROM_MIN_OPTION 0xc8000
838 #define PC_ROM_MAX 0xe0000
839 #define PC_ROM_ALIGN 0x800
840 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
841
842 static hwaddr pc_above_4g_end(PCMachineState *pcms)
843 {
844 X86MachineState *x86ms = X86_MACHINE(pcms);
845
846 if (pcms->sgx_epc.size != 0) {
847 return sgx_epc_above_4g_end(&pcms->sgx_epc);
848 }
849
850 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
851 }
852
853 static void pc_get_device_memory_range(PCMachineState *pcms,
854 hwaddr *base,
855 ram_addr_t *device_mem_size)
856 {
857 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
858 MachineState *machine = MACHINE(pcms);
859 ram_addr_t size;
860 hwaddr addr;
861
862 size = machine->maxram_size - machine->ram_size;
863 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
864
865 if (pcmc->enforce_aligned_dimm) {
866 /* size device region assuming 1G page max alignment per slot */
867 size += (1 * GiB) * machine->ram_slots;
868 }
869
870 *base = addr;
871 *device_mem_size = size;
872 }
873
874 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
875 {
876 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
877 hwaddr cxl_base;
878 ram_addr_t size;
879
880 if (pcmc->has_reserved_memory) {
881 pc_get_device_memory_range(pcms, &cxl_base, &size);
882 cxl_base += size;
883 } else {
884 cxl_base = pc_above_4g_end(pcms);
885 }
886
887 return cxl_base;
888 }
889
890 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
891 {
892 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
893
894 if (pcms->cxl_devices_state.fixed_windows) {
895 GList *it;
896
897 start = ROUND_UP(start, 256 * MiB);
898 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
899 CXLFixedWindow *fw = it->data;
900 start += fw->size;
901 }
902 }
903
904 return start;
905 }
906
907 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
908 {
909 X86CPU *cpu = X86_CPU(first_cpu);
910
911 /* 32-bit systems don't have hole64 thus return max CPU address */
912 if (cpu->phys_bits <= 32) {
913 return ((hwaddr)1 << cpu->phys_bits) - 1;
914 }
915
916 return pc_pci_hole64_start() + pci_hole64_size - 1;
917 }
918
919 /*
920 * AMD systems with an IOMMU have an additional hole close to the
921 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
922 * on kernel version, VFIO may or may not let you DMA map those ranges.
923 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
924 * with certain memory sizes. It's also wrong to use those IOVA ranges
925 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
926 * The ranges reserved for Hyper-Transport are:
927 *
928 * FD_0000_0000h - FF_FFFF_FFFFh
929 *
930 * The ranges represent the following:
931 *
932 * Base Address Top Address Use
933 *
934 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
935 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
936 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
937 * FD_F910_0000h FD_F91F_FFFFh System Management
938 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
939 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
940 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
941 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
942 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
943 * FE_2000_0000h FF_FFFF_FFFFh Reserved
944 *
945 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
946 * Table 3: Special Address Controls (GPA) for more information.
947 */
948 #define AMD_HT_START 0xfd00000000UL
949 #define AMD_HT_END 0xffffffffffUL
950 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
951 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
952
953 void pc_memory_init(PCMachineState *pcms,
954 MemoryRegion *system_memory,
955 MemoryRegion *rom_memory,
956 uint64_t pci_hole64_size)
957 {
958 int linux_boot, i;
959 MemoryRegion *option_rom_mr;
960 MemoryRegion *ram_below_4g, *ram_above_4g;
961 FWCfgState *fw_cfg;
962 MachineState *machine = MACHINE(pcms);
963 MachineClass *mc = MACHINE_GET_CLASS(machine);
964 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
965 X86MachineState *x86ms = X86_MACHINE(pcms);
966 hwaddr maxphysaddr, maxusedaddr;
967 hwaddr cxl_base, cxl_resv_end = 0;
968 X86CPU *cpu = X86_CPU(first_cpu);
969
970 assert(machine->ram_size == x86ms->below_4g_mem_size +
971 x86ms->above_4g_mem_size);
972
973 linux_boot = (machine->kernel_filename != NULL);
974
975 /*
976 * The HyperTransport range close to the 1T boundary is unique to AMD
977 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
978 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
979 * older machine types (<= 7.0) for compatibility purposes.
980 */
981 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
982 /* Bail out if max possible address does not cross HT range */
983 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
984 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
985 }
986
987 /*
988 * Advertise the HT region if address space covers the reserved
989 * region or if we relocate.
990 */
991 if (cpu->phys_bits >= 40) {
992 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
993 }
994 }
995
996 /*
997 * phys-bits is required to be appropriately configured
998 * to make sure max used GPA is reachable.
999 */
1000 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
1001 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
1002 if (maxphysaddr < maxusedaddr) {
1003 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
1004 " phys-bits too low (%u)",
1005 maxphysaddr, maxusedaddr, cpu->phys_bits);
1006 exit(EXIT_FAILURE);
1007 }
1008
1009 /*
1010 * Split single memory region and use aliases to address portions of it,
1011 * done for backwards compatibility with older qemus.
1012 */
1013 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1014 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
1015 0, x86ms->below_4g_mem_size);
1016 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1017 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1018 if (x86ms->above_4g_mem_size > 0) {
1019 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1020 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1021 machine->ram,
1022 x86ms->below_4g_mem_size,
1023 x86ms->above_4g_mem_size);
1024 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1025 ram_above_4g);
1026 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1027 E820_RAM);
1028 }
1029
1030 if (pcms->sgx_epc.size != 0) {
1031 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1032 }
1033
1034 if (!pcmc->has_reserved_memory &&
1035 (machine->ram_slots ||
1036 (machine->maxram_size > machine->ram_size))) {
1037
1038 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1039 mc->name);
1040 exit(EXIT_FAILURE);
1041 }
1042
1043 /* initialize device memory address space */
1044 if (pcmc->has_reserved_memory &&
1045 (machine->ram_size < machine->maxram_size)) {
1046 ram_addr_t device_mem_size;
1047 hwaddr device_mem_base;
1048
1049 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1050 error_report("unsupported amount of memory slots: %"PRIu64,
1051 machine->ram_slots);
1052 exit(EXIT_FAILURE);
1053 }
1054
1055 if (QEMU_ALIGN_UP(machine->maxram_size,
1056 TARGET_PAGE_SIZE) != machine->maxram_size) {
1057 error_report("maximum memory size must by aligned to multiple of "
1058 "%d bytes", TARGET_PAGE_SIZE);
1059 exit(EXIT_FAILURE);
1060 }
1061
1062 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
1063
1064 if (device_mem_base + device_mem_size < device_mem_size) {
1065 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1066 machine->maxram_size);
1067 exit(EXIT_FAILURE);
1068 }
1069 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
1070 }
1071
1072 if (pcms->cxl_devices_state.is_enabled) {
1073 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1074 hwaddr cxl_size = MiB;
1075
1076 cxl_base = pc_get_cxl_range_start(pcms);
1077 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1078 memory_region_add_subregion(system_memory, cxl_base, mr);
1079 cxl_resv_end = cxl_base + cxl_size;
1080 if (pcms->cxl_devices_state.fixed_windows) {
1081 hwaddr cxl_fmw_base;
1082 GList *it;
1083
1084 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1085 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1086 CXLFixedWindow *fw = it->data;
1087
1088 fw->base = cxl_fmw_base;
1089 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1090 "cxl-fixed-memory-region", fw->size);
1091 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1092 cxl_fmw_base += fw->size;
1093 cxl_resv_end = cxl_fmw_base;
1094 }
1095 }
1096 }
1097
1098 /* Initialize PC system firmware */
1099 pc_system_firmware_init(pcms, rom_memory);
1100
1101 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1102 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1103 &error_fatal);
1104 if (pcmc->pci_enabled) {
1105 memory_region_set_readonly(option_rom_mr, true);
1106 }
1107 memory_region_add_subregion_overlap(rom_memory,
1108 PC_ROM_MIN_VGA,
1109 option_rom_mr,
1110 1);
1111
1112 fw_cfg = fw_cfg_arch_create(machine,
1113 x86ms->boot_cpus, x86ms->apic_id_limit);
1114
1115 rom_set_fw(fw_cfg);
1116
1117 if (machine->device_memory) {
1118 uint64_t *val = g_malloc(sizeof(*val));
1119 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1120 uint64_t res_mem_end = machine->device_memory->base;
1121
1122 if (!pcmc->broken_reserved_end) {
1123 res_mem_end += memory_region_size(&machine->device_memory->mr);
1124 }
1125
1126 if (pcms->cxl_devices_state.is_enabled) {
1127 res_mem_end = cxl_resv_end;
1128 }
1129 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1130 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1131 }
1132
1133 if (linux_boot) {
1134 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1135 pcmc->pvh_enabled);
1136 }
1137
1138 for (i = 0; i < nb_option_roms; i++) {
1139 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1140 }
1141 x86ms->fw_cfg = fw_cfg;
1142
1143 /* Init default IOAPIC address space */
1144 x86ms->ioapic_as = &address_space_memory;
1145
1146 /* Init ACPI memory hotplug IO base address */
1147 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1148 }
1149
1150 /*
1151 * The 64bit pci hole starts after "above 4G RAM" and
1152 * potentially the space reserved for memory hotplug.
1153 */
1154 uint64_t pc_pci_hole64_start(void)
1155 {
1156 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1157 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1158 MachineState *ms = MACHINE(pcms);
1159 uint64_t hole64_start = 0;
1160 ram_addr_t size = 0;
1161
1162 if (pcms->cxl_devices_state.is_enabled) {
1163 hole64_start = pc_get_cxl_range_end(pcms);
1164 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1165 pc_get_device_memory_range(pcms, &hole64_start, &size);
1166 if (!pcmc->broken_reserved_end) {
1167 hole64_start += size;
1168 }
1169 } else {
1170 hole64_start = pc_above_4g_end(pcms);
1171 }
1172
1173 return ROUND_UP(hole64_start, 1 * GiB);
1174 }
1175
1176 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1177 {
1178 DeviceState *dev = NULL;
1179
1180 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1181 if (pci_bus) {
1182 PCIDevice *pcidev = pci_vga_init(pci_bus);
1183 dev = pcidev ? &pcidev->qdev : NULL;
1184 } else if (isa_bus) {
1185 ISADevice *isadev = isa_vga_init(isa_bus);
1186 dev = isadev ? DEVICE(isadev) : NULL;
1187 }
1188 rom_reset_order_override();
1189 return dev;
1190 }
1191
1192 static const MemoryRegionOps ioport80_io_ops = {
1193 .write = ioport80_write,
1194 .read = ioport80_read,
1195 .endianness = DEVICE_NATIVE_ENDIAN,
1196 .impl = {
1197 .min_access_size = 1,
1198 .max_access_size = 1,
1199 },
1200 };
1201
1202 static const MemoryRegionOps ioportF0_io_ops = {
1203 .write = ioportF0_write,
1204 .read = ioportF0_read,
1205 .endianness = DEVICE_NATIVE_ENDIAN,
1206 .impl = {
1207 .min_access_size = 1,
1208 .max_access_size = 1,
1209 },
1210 };
1211
1212 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1213 bool create_i8042, bool no_vmport)
1214 {
1215 int i;
1216 DriveInfo *fd[MAX_FD];
1217 qemu_irq *a20_line;
1218 ISADevice *fdc, *i8042, *port92, *vmmouse;
1219
1220 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1221 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1222
1223 for (i = 0; i < MAX_FD; i++) {
1224 fd[i] = drive_get(IF_FLOPPY, 0, i);
1225 create_fdctrl |= !!fd[i];
1226 }
1227 if (create_fdctrl) {
1228 fdc = isa_new(TYPE_ISA_FDC);
1229 if (fdc) {
1230 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1231 isa_fdc_init_drives(fdc, fd);
1232 }
1233 }
1234
1235 if (!create_i8042) {
1236 return;
1237 }
1238
1239 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1240 if (!no_vmport) {
1241 isa_create_simple(isa_bus, TYPE_VMPORT);
1242 vmmouse = isa_try_new("vmmouse");
1243 } else {
1244 vmmouse = NULL;
1245 }
1246 if (vmmouse) {
1247 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1248 &error_abort);
1249 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1250 }
1251 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1252
1253 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1254 i8042_setup_a20_line(i8042, a20_line[0]);
1255 qdev_connect_gpio_out_named(DEVICE(port92),
1256 PORT92_A20_LINE, 0, a20_line[1]);
1257 g_free(a20_line);
1258 }
1259
1260 void pc_basic_device_init(struct PCMachineState *pcms,
1261 ISABus *isa_bus, qemu_irq *gsi,
1262 ISADevice *rtc_state,
1263 bool create_fdctrl,
1264 uint32_t hpet_irqs)
1265 {
1266 int i;
1267 DeviceState *hpet = NULL;
1268 int pit_isa_irq = 0;
1269 qemu_irq pit_alt_irq = NULL;
1270 qemu_irq rtc_irq = NULL;
1271 ISADevice *pit = NULL;
1272 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1273 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1274 X86MachineState *x86ms = X86_MACHINE(pcms);
1275
1276 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1277 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1278
1279 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1280 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1281
1282 /*
1283 * Check if an HPET shall be created.
1284 *
1285 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1286 * when the HPET wants to take over. Thus we have to disable the latter.
1287 */
1288 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1289 kvm_has_pit_state2())) {
1290 hpet = qdev_try_new(TYPE_HPET);
1291 if (!hpet) {
1292 error_report("couldn't create HPET device");
1293 exit(1);
1294 }
1295 /*
1296 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1297 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1298 * IRQ2.
1299 */
1300 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1301 HPET_INTCAP, NULL);
1302 if (!compat) {
1303 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1304 }
1305 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1306 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1307
1308 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1309 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1310 }
1311 pit_isa_irq = -1;
1312 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1313 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1314 }
1315
1316 if (rtc_irq) {
1317 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1318 } else {
1319 uint32_t irq = object_property_get_uint(OBJECT(rtc_state),
1320 "irq",
1321 &error_fatal);
1322 isa_connect_gpio_out(rtc_state, 0, irq);
1323 }
1324 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1325 "date");
1326
1327 #ifdef CONFIG_XEN_EMU
1328 if (xen_mode == XEN_EMULATE) {
1329 xen_overlay_create();
1330 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1331 xen_gnttab_create();
1332 xen_xenstore_create();
1333 if (pcms->bus) {
1334 pci_create_simple(pcms->bus, -1, "xen-platform");
1335 }
1336 xen_bus_init();
1337 xen_be_init();
1338 }
1339 #endif
1340
1341 qemu_register_boot_set(pc_boot_set, rtc_state);
1342
1343 if (!xen_enabled() &&
1344 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1345 if (kvm_pit_in_kernel()) {
1346 pit = kvm_pit_init(isa_bus, 0x40);
1347 } else {
1348 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1349 }
1350 if (hpet) {
1351 /* connect PIT to output control line of the HPET */
1352 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1353 }
1354 pcspk_init(pcms->pcspk, isa_bus, pit);
1355 }
1356
1357 /* Super I/O */
1358 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1359 pcms->vmport != ON_OFF_AUTO_ON);
1360 }
1361
1362 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1363 {
1364 MachineClass *mc = MACHINE_CLASS(pcmc);
1365 int i;
1366
1367 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1368 for (i = 0; i < nb_nics; i++) {
1369 NICInfo *nd = &nd_table[i];
1370 const char *model = nd->model ? nd->model : mc->default_nic;
1371
1372 if (g_str_equal(model, "ne2k_isa")) {
1373 pc_init_ne2k_isa(isa_bus, nd);
1374 } else {
1375 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1376 }
1377 }
1378 rom_reset_order_override();
1379 }
1380
1381 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1382 {
1383 qemu_irq *i8259;
1384
1385 if (kvm_pic_in_kernel()) {
1386 i8259 = kvm_i8259_init(isa_bus);
1387 } else if (xen_enabled()) {
1388 i8259 = xen_interrupt_controller_init();
1389 } else {
1390 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1391 }
1392
1393 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1394 i8259_irqs[i] = i8259[i];
1395 }
1396
1397 g_free(i8259);
1398 }
1399
1400 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1401 Error **errp)
1402 {
1403 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1404 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1405 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1406 const MachineState *ms = MACHINE(hotplug_dev);
1407 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1408 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1409 Error *local_err = NULL;
1410
1411 /*
1412 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1413 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1414 * addition to cover this case.
1415 */
1416 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1417 error_setg(errp,
1418 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1419 return;
1420 }
1421
1422 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1423 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1424 return;
1425 }
1426
1427 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1428 if (local_err) {
1429 error_propagate(errp, local_err);
1430 return;
1431 }
1432
1433 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1434 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1435 }
1436
1437 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1438 DeviceState *dev, Error **errp)
1439 {
1440 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1441 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1442 MachineState *ms = MACHINE(hotplug_dev);
1443 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1444
1445 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1446
1447 if (is_nvdimm) {
1448 nvdimm_plug(ms->nvdimms_state);
1449 }
1450
1451 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1452 }
1453
1454 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1455 DeviceState *dev, Error **errp)
1456 {
1457 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1458
1459 /*
1460 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1461 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1462 * addition to cover this case.
1463 */
1464 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1465 error_setg(errp,
1466 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1467 return;
1468 }
1469
1470 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1471 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1472 return;
1473 }
1474
1475 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1476 errp);
1477 }
1478
1479 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1480 DeviceState *dev, Error **errp)
1481 {
1482 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1483 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1484 Error *local_err = NULL;
1485
1486 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1487 if (local_err) {
1488 goto out;
1489 }
1490
1491 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1492 qdev_unrealize(dev);
1493 out:
1494 error_propagate(errp, local_err);
1495 }
1496
1497 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1498 DeviceState *dev, Error **errp)
1499 {
1500 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1501 pc_memory_pre_plug(hotplug_dev, dev, errp);
1502 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1503 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1504 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1505 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1507 /* Declare the APIC range as the reserved MSI region */
1508 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1509 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1510
1511 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1512 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1513 resv_prop_str, errp);
1514 g_free(resv_prop_str);
1515 }
1516
1517 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1518 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1519 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1520
1521 if (pcms->iommu) {
1522 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1523 "for x86 yet.");
1524 return;
1525 }
1526 pcms->iommu = dev;
1527 }
1528 }
1529
1530 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1531 DeviceState *dev, Error **errp)
1532 {
1533 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1534 pc_memory_plug(hotplug_dev, dev, errp);
1535 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1536 x86_cpu_plug(hotplug_dev, dev, errp);
1537 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1538 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1539 }
1540 }
1541
1542 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1543 DeviceState *dev, Error **errp)
1544 {
1545 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1546 pc_memory_unplug_request(hotplug_dev, dev, errp);
1547 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1548 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1549 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1550 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1551 errp);
1552 } else {
1553 error_setg(errp, "acpi: device unplug request for not supported device"
1554 " type: %s", object_get_typename(OBJECT(dev)));
1555 }
1556 }
1557
1558 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1559 DeviceState *dev, Error **errp)
1560 {
1561 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1562 pc_memory_unplug(hotplug_dev, dev, errp);
1563 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1564 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1565 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1566 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1567 } else {
1568 error_setg(errp, "acpi: device unplug for not supported device"
1569 " type: %s", object_get_typename(OBJECT(dev)));
1570 }
1571 }
1572
1573 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1574 DeviceState *dev)
1575 {
1576 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1577 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1578 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1579 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1580 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1581 return HOTPLUG_HANDLER(machine);
1582 }
1583
1584 return NULL;
1585 }
1586
1587 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1588 void *opaque, Error **errp)
1589 {
1590 PCMachineState *pcms = PC_MACHINE(obj);
1591 OnOffAuto vmport = pcms->vmport;
1592
1593 visit_type_OnOffAuto(v, name, &vmport, errp);
1594 }
1595
1596 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1597 void *opaque, Error **errp)
1598 {
1599 PCMachineState *pcms = PC_MACHINE(obj);
1600
1601 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1602 }
1603
1604 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1605 {
1606 PCMachineState *pcms = PC_MACHINE(obj);
1607
1608 return pcms->smbus_enabled;
1609 }
1610
1611 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1612 {
1613 PCMachineState *pcms = PC_MACHINE(obj);
1614
1615 pcms->smbus_enabled = value;
1616 }
1617
1618 static bool pc_machine_get_sata(Object *obj, Error **errp)
1619 {
1620 PCMachineState *pcms = PC_MACHINE(obj);
1621
1622 return pcms->sata_enabled;
1623 }
1624
1625 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1626 {
1627 PCMachineState *pcms = PC_MACHINE(obj);
1628
1629 pcms->sata_enabled = value;
1630 }
1631
1632 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1633 {
1634 PCMachineState *pcms = PC_MACHINE(obj);
1635
1636 return pcms->hpet_enabled;
1637 }
1638
1639 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1640 {
1641 PCMachineState *pcms = PC_MACHINE(obj);
1642
1643 pcms->hpet_enabled = value;
1644 }
1645
1646 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1647 {
1648 PCMachineState *pcms = PC_MACHINE(obj);
1649
1650 return pcms->i8042_enabled;
1651 }
1652
1653 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1654 {
1655 PCMachineState *pcms = PC_MACHINE(obj);
1656
1657 pcms->i8042_enabled = value;
1658 }
1659
1660 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1661 {
1662 PCMachineState *pcms = PC_MACHINE(obj);
1663
1664 return pcms->default_bus_bypass_iommu;
1665 }
1666
1667 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1668 Error **errp)
1669 {
1670 PCMachineState *pcms = PC_MACHINE(obj);
1671
1672 pcms->default_bus_bypass_iommu = value;
1673 }
1674
1675 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1676 void *opaque, Error **errp)
1677 {
1678 PCMachineState *pcms = PC_MACHINE(obj);
1679 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1680
1681 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1682 }
1683
1684 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1685 void *opaque, Error **errp)
1686 {
1687 PCMachineState *pcms = PC_MACHINE(obj);
1688
1689 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1690 }
1691
1692 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1693 const char *name, void *opaque,
1694 Error **errp)
1695 {
1696 PCMachineState *pcms = PC_MACHINE(obj);
1697 uint64_t value = pcms->max_ram_below_4g;
1698
1699 visit_type_size(v, name, &value, errp);
1700 }
1701
1702 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1703 const char *name, void *opaque,
1704 Error **errp)
1705 {
1706 PCMachineState *pcms = PC_MACHINE(obj);
1707 uint64_t value;
1708
1709 if (!visit_type_size(v, name, &value, errp)) {
1710 return;
1711 }
1712 if (value > 4 * GiB) {
1713 error_setg(errp,
1714 "Machine option 'max-ram-below-4g=%"PRIu64
1715 "' expects size less than or equal to 4G", value);
1716 return;
1717 }
1718
1719 if (value < 1 * MiB) {
1720 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1721 "BIOS may not work with less than 1MiB", value);
1722 }
1723
1724 pcms->max_ram_below_4g = value;
1725 }
1726
1727 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1728 const char *name, void *opaque,
1729 Error **errp)
1730 {
1731 PCMachineState *pcms = PC_MACHINE(obj);
1732 uint64_t value = pcms->max_fw_size;
1733
1734 visit_type_size(v, name, &value, errp);
1735 }
1736
1737 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1738 const char *name, void *opaque,
1739 Error **errp)
1740 {
1741 PCMachineState *pcms = PC_MACHINE(obj);
1742 uint64_t value;
1743
1744 if (!visit_type_size(v, name, &value, errp)) {
1745 return;
1746 }
1747
1748 /*
1749 * We don't have a theoretically justifiable exact lower bound on the base
1750 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1751 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1752 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1753 * size.
1754 */
1755 if (value > 16 * MiB) {
1756 error_setg(errp,
1757 "User specified max allowed firmware size %" PRIu64 " is "
1758 "greater than 16MiB. If combined firmware size exceeds "
1759 "16MiB the system may not boot, or experience intermittent"
1760 "stability issues.",
1761 value);
1762 return;
1763 }
1764
1765 pcms->max_fw_size = value;
1766 }
1767
1768
1769 static void pc_machine_initfn(Object *obj)
1770 {
1771 PCMachineState *pcms = PC_MACHINE(obj);
1772 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1773
1774 #ifdef CONFIG_VMPORT
1775 pcms->vmport = ON_OFF_AUTO_AUTO;
1776 #else
1777 pcms->vmport = ON_OFF_AUTO_OFF;
1778 #endif /* CONFIG_VMPORT */
1779 pcms->max_ram_below_4g = 0; /* use default */
1780 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1781
1782 /* acpi build is enabled by default if machine supports it */
1783 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1784 pcms->smbus_enabled = true;
1785 pcms->sata_enabled = true;
1786 pcms->i8042_enabled = true;
1787 pcms->max_fw_size = 8 * MiB;
1788 #ifdef CONFIG_HPET
1789 pcms->hpet_enabled = true;
1790 #endif
1791 pcms->default_bus_bypass_iommu = false;
1792
1793 pc_system_flash_create(pcms);
1794 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1795 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1796 OBJECT(pcms->pcspk), "audiodev");
1797 cxl_machine_init(obj, &pcms->cxl_devices_state);
1798 }
1799
1800 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1801 {
1802 return 0;
1803 }
1804
1805 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1806 {
1807 CPUState *cs;
1808 X86CPU *cpu;
1809
1810 qemu_devices_reset(reason);
1811
1812 /* Reset APIC after devices have been reset to cancel
1813 * any changes that qemu_devices_reset() might have done.
1814 */
1815 CPU_FOREACH(cs) {
1816 cpu = X86_CPU(cs);
1817
1818 x86_cpu_after_reset(cpu);
1819 }
1820 }
1821
1822 static void pc_machine_wakeup(MachineState *machine)
1823 {
1824 cpu_synchronize_all_states();
1825 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1826 cpu_synchronize_all_post_reset();
1827 }
1828
1829 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1830 {
1831 X86IOMMUState *iommu = x86_iommu_get_default();
1832 IntelIOMMUState *intel_iommu;
1833
1834 if (iommu &&
1835 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1836 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1837 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1838 if (!intel_iommu->caching_mode) {
1839 error_setg(errp, "Device assignment is not allowed without "
1840 "enabling caching-mode=on for Intel IOMMU.");
1841 return false;
1842 }
1843 }
1844
1845 return true;
1846 }
1847
1848 static void pc_machine_class_init(ObjectClass *oc, void *data)
1849 {
1850 MachineClass *mc = MACHINE_CLASS(oc);
1851 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1852 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1853
1854 pcmc->pci_enabled = true;
1855 pcmc->has_acpi_build = true;
1856 pcmc->rsdp_in_ram = true;
1857 pcmc->smbios_defaults = true;
1858 pcmc->smbios_uuid_encoded = true;
1859 pcmc->gigabyte_align = true;
1860 pcmc->has_reserved_memory = true;
1861 pcmc->kvmclock_enabled = true;
1862 pcmc->enforce_aligned_dimm = true;
1863 pcmc->enforce_amd_1tb_hole = true;
1864 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1865 * to be used at the moment, 32K should be enough for a while. */
1866 pcmc->acpi_data_size = 0x20000 + 0x8000;
1867 pcmc->pvh_enabled = true;
1868 pcmc->kvmclock_create_always = true;
1869 pcmc->resizable_acpi_blob = true;
1870 assert(!mc->get_hotplug_handler);
1871 mc->get_hotplug_handler = pc_get_hotplug_handler;
1872 mc->hotplug_allowed = pc_hotplug_allowed;
1873 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1874 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1875 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1876 mc->auto_enable_numa_with_memhp = true;
1877 mc->auto_enable_numa_with_memdev = true;
1878 mc->has_hotpluggable_cpus = true;
1879 mc->default_boot_order = "cad";
1880 mc->block_default_type = IF_IDE;
1881 mc->max_cpus = 255;
1882 mc->reset = pc_machine_reset;
1883 mc->wakeup = pc_machine_wakeup;
1884 hc->pre_plug = pc_machine_device_pre_plug_cb;
1885 hc->plug = pc_machine_device_plug_cb;
1886 hc->unplug_request = pc_machine_device_unplug_request_cb;
1887 hc->unplug = pc_machine_device_unplug_cb;
1888 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1889 mc->nvdimm_supported = true;
1890 mc->smp_props.dies_supported = true;
1891 mc->default_ram_id = "pc.ram";
1892 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1893
1894 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1895 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1896 NULL, NULL);
1897 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1898 "Maximum ram below the 4G boundary (32bit boundary)");
1899
1900 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1901 pc_machine_get_vmport, pc_machine_set_vmport,
1902 NULL, NULL);
1903 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1904 "Enable vmport (pc & q35)");
1905
1906 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1907 pc_machine_get_smbus, pc_machine_set_smbus);
1908 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1909 "Enable/disable system management bus");
1910
1911 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1912 pc_machine_get_sata, pc_machine_set_sata);
1913 object_class_property_set_description(oc, PC_MACHINE_SATA,
1914 "Enable/disable Serial ATA bus");
1915
1916 object_class_property_add_bool(oc, "hpet",
1917 pc_machine_get_hpet, pc_machine_set_hpet);
1918 object_class_property_set_description(oc, "hpet",
1919 "Enable/disable high precision event timer emulation");
1920
1921 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1922 pc_machine_get_i8042, pc_machine_set_i8042);
1923
1924 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1925 pc_machine_get_default_bus_bypass_iommu,
1926 pc_machine_set_default_bus_bypass_iommu);
1927
1928 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1929 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1930 NULL, NULL);
1931 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1932 "Maximum combined firmware size");
1933
1934 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1935 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1936 NULL, NULL);
1937 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1938 "SMBIOS Entry Point type [32, 64]");
1939 }
1940
1941 static const TypeInfo pc_machine_info = {
1942 .name = TYPE_PC_MACHINE,
1943 .parent = TYPE_X86_MACHINE,
1944 .abstract = true,
1945 .instance_size = sizeof(PCMachineState),
1946 .instance_init = pc_machine_initfn,
1947 .class_size = sizeof(PCMachineClass),
1948 .class_init = pc_machine_class_init,
1949 .interfaces = (InterfaceInfo[]) {
1950 { TYPE_HOTPLUG_HANDLER },
1951 { }
1952 },
1953 };
1954
1955 static void pc_machine_register_types(void)
1956 {
1957 type_register_static(&pc_machine_info);
1958 }
1959
1960 type_init(pc_machine_register_types)
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