2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "hw/i386/vmport.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide/internal.h"
37 #include "hw/ide/isa.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/intc/ioapic.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-pmem-pci.h"
92 #include "hw/virtio/virtio-mem-pci.h"
93 #include "hw/i386/kvm/xen_overlay.h"
94 #include "hw/i386/kvm/xen_evtchn.h"
95 #include "hw/i386/kvm/xen_gnttab.h"
96 #include "hw/i386/kvm/xen_xenstore.h"
97 #include "hw/mem/memory-device.h"
98 #include "sysemu/replay.h"
99 #include "target/i386/cpu.h"
100 #include "e820_memory_layout.h"
103 #include CONFIG_DEVICES
105 #ifdef CONFIG_XEN_EMU
106 #include "hw/xen/xen-legacy-backend.h"
107 #include "hw/xen/xen-bus.h"
111 * Helper for setting model-id for CPU models that changed model-id
112 * depending on QEMU versions up to QEMU 2.4.
114 #define PC_CPU_MODEL_IDS(v) \
115 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
116 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
117 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
119 GlobalProperty pc_compat_8_0
[] = {
120 { "virtio-mem", "unplugged-inaccessible", "auto" },
122 const size_t pc_compat_8_0_len
= G_N_ELEMENTS(pc_compat_8_0
);
124 GlobalProperty pc_compat_7_2
[] = {
125 { "ICH9-LPC", "noreboot", "true" },
127 const size_t pc_compat_7_2_len
= G_N_ELEMENTS(pc_compat_7_2
);
129 GlobalProperty pc_compat_7_1
[] = {};
130 const size_t pc_compat_7_1_len
= G_N_ELEMENTS(pc_compat_7_1
);
132 GlobalProperty pc_compat_7_0
[] = {};
133 const size_t pc_compat_7_0_len
= G_N_ELEMENTS(pc_compat_7_0
);
135 GlobalProperty pc_compat_6_2
[] = {
136 { "virtio-mem", "unplugged-inaccessible", "off" },
138 const size_t pc_compat_6_2_len
= G_N_ELEMENTS(pc_compat_6_2
);
140 GlobalProperty pc_compat_6_1
[] = {
141 { TYPE_X86_CPU
, "hv-version-id-build", "0x1bbc" },
142 { TYPE_X86_CPU
, "hv-version-id-major", "0x0006" },
143 { TYPE_X86_CPU
, "hv-version-id-minor", "0x0001" },
144 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
146 const size_t pc_compat_6_1_len
= G_N_ELEMENTS(pc_compat_6_1
);
148 GlobalProperty pc_compat_6_0
[] = {
149 { "qemu64" "-" TYPE_X86_CPU
, "family", "6" },
150 { "qemu64" "-" TYPE_X86_CPU
, "model", "6" },
151 { "qemu64" "-" TYPE_X86_CPU
, "stepping", "3" },
152 { TYPE_X86_CPU
, "x-vendor-cpuid-only", "off" },
153 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE
, "off" },
154 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
156 const size_t pc_compat_6_0_len
= G_N_ELEMENTS(pc_compat_6_0
);
158 GlobalProperty pc_compat_5_2
[] = {
159 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
161 const size_t pc_compat_5_2_len
= G_N_ELEMENTS(pc_compat_5_2
);
163 GlobalProperty pc_compat_5_1
[] = {
164 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
165 { TYPE_X86_CPU
, "kvm-msi-ext-dest-id", "off" },
167 const size_t pc_compat_5_1_len
= G_N_ELEMENTS(pc_compat_5_1
);
169 GlobalProperty pc_compat_5_0
[] = {
171 const size_t pc_compat_5_0_len
= G_N_ELEMENTS(pc_compat_5_0
);
173 GlobalProperty pc_compat_4_2
[] = {
174 { "mch", "smbase-smram", "off" },
176 const size_t pc_compat_4_2_len
= G_N_ELEMENTS(pc_compat_4_2
);
178 GlobalProperty pc_compat_4_1
[] = {};
179 const size_t pc_compat_4_1_len
= G_N_ELEMENTS(pc_compat_4_1
);
181 GlobalProperty pc_compat_4_0
[] = {};
182 const size_t pc_compat_4_0_len
= G_N_ELEMENTS(pc_compat_4_0
);
184 GlobalProperty pc_compat_3_1
[] = {
185 { "intel-iommu", "dma-drain", "off" },
186 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "off" },
187 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "off" },
188 { "Opteron_G4" "-" TYPE_X86_CPU
, "npt", "off" },
189 { "Opteron_G4" "-" TYPE_X86_CPU
, "nrip-save", "off" },
190 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "off" },
191 { "Opteron_G5" "-" TYPE_X86_CPU
, "npt", "off" },
192 { "Opteron_G5" "-" TYPE_X86_CPU
, "nrip-save", "off" },
193 { "EPYC" "-" TYPE_X86_CPU
, "npt", "off" },
194 { "EPYC" "-" TYPE_X86_CPU
, "nrip-save", "off" },
195 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "npt", "off" },
196 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "nrip-save", "off" },
197 { "Skylake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
198 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
199 { "Skylake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
200 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
201 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
202 { "Icelake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
203 { "Icelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
204 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "stepping", "5" },
205 { TYPE_X86_CPU
, "x-intel-pt-auto-level", "off" },
207 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
209 GlobalProperty pc_compat_3_0
[] = {
210 { TYPE_X86_CPU
, "x-hv-synic-kvm-only", "on" },
211 { "Skylake-Server" "-" TYPE_X86_CPU
, "pku", "off" },
212 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "pku", "off" },
214 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
216 GlobalProperty pc_compat_2_12
[] = {
217 { TYPE_X86_CPU
, "legacy-cache", "on" },
218 { TYPE_X86_CPU
, "topoext", "off" },
219 { "EPYC-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
220 { "EPYC-IBPB-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
222 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
224 GlobalProperty pc_compat_2_11
[] = {
225 { TYPE_X86_CPU
, "x-migrate-smi-count", "off" },
226 { "Skylake-Server" "-" TYPE_X86_CPU
, "clflushopt", "off" },
228 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
230 GlobalProperty pc_compat_2_10
[] = {
231 { TYPE_X86_CPU
, "x-hv-max-vps", "0x40" },
232 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
233 { "q35-pcihost", "x-pci-hole64-fix", "off" },
235 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
237 GlobalProperty pc_compat_2_9
[] = {
238 { "mch", "extended-tseg-mbytes", "0" },
240 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
242 GlobalProperty pc_compat_2_8
[] = {
243 { TYPE_X86_CPU
, "tcg-cpuid", "off" },
244 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
245 { "ICH9-LPC", "x-smi-broadcast", "off" },
246 { TYPE_X86_CPU
, "vmware-cpuid-freq", "off" },
247 { "Haswell-" TYPE_X86_CPU
, "stepping", "1" },
249 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
251 GlobalProperty pc_compat_2_7
[] = {
252 { TYPE_X86_CPU
, "l3-cache", "off" },
253 { TYPE_X86_CPU
, "full-cpuid-auto-level", "off" },
254 { "Opteron_G3" "-" TYPE_X86_CPU
, "family", "15" },
255 { "Opteron_G3" "-" TYPE_X86_CPU
, "model", "6" },
256 { "Opteron_G3" "-" TYPE_X86_CPU
, "stepping", "1" },
257 { "isa-pcspk", "migrate", "off" },
259 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
261 GlobalProperty pc_compat_2_6
[] = {
262 { TYPE_X86_CPU
, "cpuid-0xb", "off" },
263 { "vmxnet3", "romfile", "" },
264 { TYPE_X86_CPU
, "fill-mtrr-mask", "off" },
265 { "apic-common", "legacy-instance-id", "on", }
267 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
269 GlobalProperty pc_compat_2_5
[] = {};
270 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
272 GlobalProperty pc_compat_2_4
[] = {
273 PC_CPU_MODEL_IDS("2.4.0")
274 { "Haswell-" TYPE_X86_CPU
, "abm", "off" },
275 { "Haswell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
276 { "Broadwell-" TYPE_X86_CPU
, "abm", "off" },
277 { "Broadwell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
278 { "host" "-" TYPE_X86_CPU
, "host-cache-info", "on" },
279 { TYPE_X86_CPU
, "check", "off" },
280 { "qemu64" "-" TYPE_X86_CPU
, "sse4a", "on" },
281 { "qemu64" "-" TYPE_X86_CPU
, "abm", "on" },
282 { "qemu64" "-" TYPE_X86_CPU
, "popcnt", "on" },
283 { "qemu32" "-" TYPE_X86_CPU
, "popcnt", "on" },
284 { "Opteron_G2" "-" TYPE_X86_CPU
, "rdtscp", "on" },
285 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "on" },
286 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "on" },
287 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "on", }
289 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
291 GlobalProperty pc_compat_2_3
[] = {
292 PC_CPU_MODEL_IDS("2.3.0")
293 { TYPE_X86_CPU
, "arat", "off" },
294 { "qemu64" "-" TYPE_X86_CPU
, "min-level", "4" },
295 { "kvm64" "-" TYPE_X86_CPU
, "min-level", "5" },
296 { "pentium3" "-" TYPE_X86_CPU
, "min-level", "2" },
297 { "n270" "-" TYPE_X86_CPU
, "min-level", "5" },
298 { "Conroe" "-" TYPE_X86_CPU
, "min-level", "4" },
299 { "Penryn" "-" TYPE_X86_CPU
, "min-level", "4" },
300 { "Nehalem" "-" TYPE_X86_CPU
, "min-level", "4" },
301 { "n270" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
302 { "Penryn" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
303 { "Conroe" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
304 { "Nehalem" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
305 { "Westmere" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
306 { "SandyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
307 { "IvyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
308 { "Haswell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
309 { "Haswell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
310 { "Broadwell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
311 { "Broadwell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
312 { TYPE_X86_CPU
, "kvm-no-smi-migration", "on" },
314 const size_t pc_compat_2_3_len
= G_N_ELEMENTS(pc_compat_2_3
);
316 GlobalProperty pc_compat_2_2
[] = {
317 PC_CPU_MODEL_IDS("2.2.0")
318 { "kvm64" "-" TYPE_X86_CPU
, "vme", "off" },
319 { "kvm32" "-" TYPE_X86_CPU
, "vme", "off" },
320 { "Conroe" "-" TYPE_X86_CPU
, "vme", "off" },
321 { "Penryn" "-" TYPE_X86_CPU
, "vme", "off" },
322 { "Nehalem" "-" TYPE_X86_CPU
, "vme", "off" },
323 { "Westmere" "-" TYPE_X86_CPU
, "vme", "off" },
324 { "SandyBridge" "-" TYPE_X86_CPU
, "vme", "off" },
325 { "Haswell" "-" TYPE_X86_CPU
, "vme", "off" },
326 { "Broadwell" "-" TYPE_X86_CPU
, "vme", "off" },
327 { "Opteron_G1" "-" TYPE_X86_CPU
, "vme", "off" },
328 { "Opteron_G2" "-" TYPE_X86_CPU
, "vme", "off" },
329 { "Opteron_G3" "-" TYPE_X86_CPU
, "vme", "off" },
330 { "Opteron_G4" "-" TYPE_X86_CPU
, "vme", "off" },
331 { "Opteron_G5" "-" TYPE_X86_CPU
, "vme", "off" },
332 { "Haswell" "-" TYPE_X86_CPU
, "f16c", "off" },
333 { "Haswell" "-" TYPE_X86_CPU
, "rdrand", "off" },
334 { "Broadwell" "-" TYPE_X86_CPU
, "f16c", "off" },
335 { "Broadwell" "-" TYPE_X86_CPU
, "rdrand", "off" },
337 const size_t pc_compat_2_2_len
= G_N_ELEMENTS(pc_compat_2_2
);
339 GlobalProperty pc_compat_2_1
[] = {
340 PC_CPU_MODEL_IDS("2.1.0")
341 { "coreduo" "-" TYPE_X86_CPU
, "vmx", "on" },
342 { "core2duo" "-" TYPE_X86_CPU
, "vmx", "on" },
344 const size_t pc_compat_2_1_len
= G_N_ELEMENTS(pc_compat_2_1
);
346 GlobalProperty pc_compat_2_0
[] = {
347 PC_CPU_MODEL_IDS("2.0.0")
348 { "virtio-scsi-pci", "any_layout", "off" },
349 { "PIIX4_PM", "memory-hotplug-support", "off" },
350 { "apic", "version", "0x11" },
351 { "nec-usb-xhci", "superspeed-ports-first", "off" },
352 { "nec-usb-xhci", "force-pcie-endcap", "on" },
353 { "pci-serial", "prog_if", "0" },
354 { "pci-serial-2x", "prog_if", "0" },
355 { "pci-serial-4x", "prog_if", "0" },
356 { "virtio-net-pci", "guest_announce", "off" },
357 { "ICH9-LPC", "memory-hotplug-support", "off" },
359 const size_t pc_compat_2_0_len
= G_N_ELEMENTS(pc_compat_2_0
);
361 GlobalProperty pc_compat_1_7
[] = {
362 PC_CPU_MODEL_IDS("1.7.0")
363 { TYPE_USB_DEVICE
, "msos-desc", "no" },
364 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE
, "off" },
365 { "hpet", HPET_INTCAP
, "4" },
367 const size_t pc_compat_1_7_len
= G_N_ELEMENTS(pc_compat_1_7
);
369 GlobalProperty pc_compat_1_6
[] = {
370 PC_CPU_MODEL_IDS("1.6.0")
371 { "e1000", "mitigation", "off" },
372 { "qemu64-" TYPE_X86_CPU
, "model", "2" },
373 { "qemu32-" TYPE_X86_CPU
, "model", "3" },
374 { "i440FX-pcihost", "short_root_bus", "1" },
375 { "q35-pcihost", "short_root_bus", "1" },
377 const size_t pc_compat_1_6_len
= G_N_ELEMENTS(pc_compat_1_6
);
379 GlobalProperty pc_compat_1_5
[] = {
380 PC_CPU_MODEL_IDS("1.5.0")
381 { "Conroe-" TYPE_X86_CPU
, "model", "2" },
382 { "Conroe-" TYPE_X86_CPU
, "min-level", "2" },
383 { "Penryn-" TYPE_X86_CPU
, "model", "2" },
384 { "Penryn-" TYPE_X86_CPU
, "min-level", "2" },
385 { "Nehalem-" TYPE_X86_CPU
, "model", "2" },
386 { "Nehalem-" TYPE_X86_CPU
, "min-level", "2" },
387 { "virtio-net-pci", "any_layout", "off" },
388 { TYPE_X86_CPU
, "pmu", "on" },
389 { "i440FX-pcihost", "short_root_bus", "0" },
390 { "q35-pcihost", "short_root_bus", "0" },
392 const size_t pc_compat_1_5_len
= G_N_ELEMENTS(pc_compat_1_5
);
394 GlobalProperty pc_compat_1_4
[] = {
395 PC_CPU_MODEL_IDS("1.4.0")
396 { "scsi-hd", "discard_granularity", "0" },
397 { "scsi-cd", "discard_granularity", "0" },
398 { "ide-hd", "discard_granularity", "0" },
399 { "ide-cd", "discard_granularity", "0" },
400 { "virtio-blk-pci", "discard_granularity", "0" },
401 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
402 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
403 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
404 { "e1000", "romfile", "pxe-e1000.rom" },
405 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
406 { "pcnet", "romfile", "pxe-pcnet.rom" },
407 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
408 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
409 { "486-" TYPE_X86_CPU
, "model", "0" },
410 { "n270" "-" TYPE_X86_CPU
, "movbe", "off" },
411 { "Westmere" "-" TYPE_X86_CPU
, "pclmulqdq", "off" },
413 const size_t pc_compat_1_4_len
= G_N_ELEMENTS(pc_compat_1_4
);
415 GSIState
*pc_gsi_create(qemu_irq
**irqs
, bool pci_enabled
)
419 s
= g_new0(GSIState
, 1);
420 if (kvm_ioapic_in_kernel()) {
421 kvm_pc_setup_irq_routing(pci_enabled
);
423 *irqs
= qemu_allocate_irqs(gsi_handler
, s
, IOAPIC_NUM_PINS
);
428 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
433 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
435 return 0xffffffffffffffffULL
;
438 /* MSDOS compatibility mode FPU exception support */
439 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
447 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
449 return 0xffffffffffffffffULL
;
452 /* PC cmos mappings */
454 #define REG_EQUIPMENT_BYTE 0x14
456 static void cmos_init_hd(MC146818RtcState
*s
, int type_ofs
, int info_ofs
,
457 int16_t cylinders
, int8_t heads
, int8_t sectors
)
459 mc146818rtc_set_cmos_data(s
, type_ofs
, 47);
460 mc146818rtc_set_cmos_data(s
, info_ofs
, cylinders
);
461 mc146818rtc_set_cmos_data(s
, info_ofs
+ 1, cylinders
>> 8);
462 mc146818rtc_set_cmos_data(s
, info_ofs
+ 2, heads
);
463 mc146818rtc_set_cmos_data(s
, info_ofs
+ 3, 0xff);
464 mc146818rtc_set_cmos_data(s
, info_ofs
+ 4, 0xff);
465 mc146818rtc_set_cmos_data(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
466 mc146818rtc_set_cmos_data(s
, info_ofs
+ 6, cylinders
);
467 mc146818rtc_set_cmos_data(s
, info_ofs
+ 7, cylinders
>> 8);
468 mc146818rtc_set_cmos_data(s
, info_ofs
+ 8, sectors
);
471 /* convert boot_device letter to something recognizable by the bios */
472 static int boot_device2nibble(char boot_device
)
474 switch(boot_device
) {
477 return 0x01; /* floppy boot */
479 return 0x02; /* hard drive boot */
481 return 0x03; /* CD-ROM boot */
483 return 0x04; /* Network boot */
488 static void set_boot_dev(MC146818RtcState
*s
, const char *boot_device
,
491 #define PC_MAX_BOOT_DEVICES 3
492 int nbds
, bds
[3] = { 0, };
495 nbds
= strlen(boot_device
);
496 if (nbds
> PC_MAX_BOOT_DEVICES
) {
497 error_setg(errp
, "Too many boot devices for PC");
500 for (i
= 0; i
< nbds
; i
++) {
501 bds
[i
] = boot_device2nibble(boot_device
[i
]);
503 error_setg(errp
, "Invalid boot device for PC: '%c'",
508 mc146818rtc_set_cmos_data(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
509 mc146818rtc_set_cmos_data(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
512 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
514 set_boot_dev(opaque
, boot_device
, errp
);
517 static void pc_cmos_init_floppy(MC146818RtcState
*rtc_state
, ISADevice
*floppy
)
520 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
521 FLOPPY_DRIVE_TYPE_NONE
};
525 for (i
= 0; i
< 2; i
++) {
526 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
529 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
530 cmos_get_fd_drive_type(fd_type
[1]);
531 mc146818rtc_set_cmos_data(rtc_state
, 0x10, val
);
533 val
= mc146818rtc_get_cmos_data(rtc_state
, REG_EQUIPMENT_BYTE
);
535 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
538 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
545 val
|= 0x01; /* 1 drive, ready for boot */
548 val
|= 0x41; /* 2 drives, ready for boot */
551 mc146818rtc_set_cmos_data(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
554 typedef struct pc_cmos_init_late_arg
{
555 MC146818RtcState
*rtc_state
;
557 } pc_cmos_init_late_arg
;
559 typedef struct check_fdc_state
{
564 static int check_fdc(Object
*obj
, void *opaque
)
566 CheckFdcState
*state
= opaque
;
569 Error
*local_err
= NULL
;
571 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
576 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
577 if (local_err
|| iobase
!= 0x3f0) {
578 error_free(local_err
);
583 state
->multiple
= true;
585 state
->floppy
= ISA_DEVICE(obj
);
590 static const char * const fdc_container_path
[] = {
591 "/unattached", "/peripheral", "/peripheral-anon"
595 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
598 static ISADevice
*pc_find_fdc0(void)
602 CheckFdcState state
= { 0 };
604 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
605 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
606 object_child_foreach(container
, check_fdc
, &state
);
609 if (state
.multiple
) {
610 warn_report("multiple floppy disk controllers with "
611 "iobase=0x3f0 have been found");
612 error_printf("the one being picked for CMOS setup might not reflect "
619 static void pc_cmos_init_late(void *opaque
)
621 pc_cmos_init_late_arg
*arg
= opaque
;
622 MC146818RtcState
*s
= arg
->rtc_state
;
624 int8_t heads
, sectors
;
629 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
630 &cylinders
, &heads
, §ors
) >= 0) {
631 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
634 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
635 &cylinders
, &heads
, §ors
) >= 0) {
636 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
639 mc146818rtc_set_cmos_data(s
, 0x12, val
);
642 for (i
= 0; i
< 4; i
++) {
643 /* NOTE: ide_get_geometry() returns the physical
644 geometry. It is always such that: 1 <= sects <= 63, 1
645 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
646 geometry can be different if a translation is done. */
647 if (arg
->idebus
[i
/ 2] &&
648 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
649 &cylinders
, &heads
, §ors
) >= 0) {
650 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
651 assert((trans
& ~3) == 0);
652 val
|= trans
<< (i
* 2);
655 mc146818rtc_set_cmos_data(s
, 0x39, val
);
657 pc_cmos_init_floppy(s
, pc_find_fdc0());
659 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
662 void pc_cmos_init(PCMachineState
*pcms
,
663 BusState
*idebus0
, BusState
*idebus1
,
667 static pc_cmos_init_late_arg arg
;
668 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
669 MC146818RtcState
*s
= MC146818_RTC(rtc
);
671 /* various important CMOS locations needed by PC/Bochs bios */
674 /* base memory (first MiB) */
675 val
= MIN(x86ms
->below_4g_mem_size
/ KiB
, 640);
676 mc146818rtc_set_cmos_data(s
, 0x15, val
);
677 mc146818rtc_set_cmos_data(s
, 0x16, val
>> 8);
678 /* extended memory (next 64MiB) */
679 if (x86ms
->below_4g_mem_size
> 1 * MiB
) {
680 val
= (x86ms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
686 mc146818rtc_set_cmos_data(s
, 0x17, val
);
687 mc146818rtc_set_cmos_data(s
, 0x18, val
>> 8);
688 mc146818rtc_set_cmos_data(s
, 0x30, val
);
689 mc146818rtc_set_cmos_data(s
, 0x31, val
>> 8);
690 /* memory between 16MiB and 4GiB */
691 if (x86ms
->below_4g_mem_size
> 16 * MiB
) {
692 val
= (x86ms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
698 mc146818rtc_set_cmos_data(s
, 0x34, val
);
699 mc146818rtc_set_cmos_data(s
, 0x35, val
>> 8);
700 /* memory above 4GiB */
701 val
= x86ms
->above_4g_mem_size
/ 65536;
702 mc146818rtc_set_cmos_data(s
, 0x5b, val
);
703 mc146818rtc_set_cmos_data(s
, 0x5c, val
>> 8);
704 mc146818rtc_set_cmos_data(s
, 0x5d, val
>> 16);
706 object_property_add_link(OBJECT(pcms
), "rtc_state",
708 (Object
**)&x86ms
->rtc
,
709 object_property_allow_set_link
,
710 OBJ_PROP_LINK_STRONG
);
711 object_property_set_link(OBJECT(pcms
), "rtc_state", OBJECT(s
),
714 set_boot_dev(s
, MACHINE(pcms
)->boot_config
.order
, &error_fatal
);
717 val
|= 0x02; /* FPU is there */
718 val
|= 0x04; /* PS/2 mouse installed */
719 mc146818rtc_set_cmos_data(s
, REG_EQUIPMENT_BYTE
, val
);
721 /* hard drives and FDC */
723 arg
.idebus
[0] = idebus0
;
724 arg
.idebus
[1] = idebus1
;
725 qemu_register_reset(pc_cmos_init_late
, &arg
);
728 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
730 X86CPU
*cpu
= opaque
;
732 /* XXX: send to all CPUs ? */
733 /* XXX: add logic to handle multiple A20 line sources */
734 x86_cpu_set_a20(cpu
, level
);
737 #define NE2000_NB_MAX 6
739 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
741 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
743 static void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
745 static int nb_ne2k
= 0;
747 if (nb_ne2k
== NE2000_NB_MAX
)
749 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
750 ne2000_irq
[nb_ne2k
], nd
);
754 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
756 X86CPU
*cpu
= opaque
;
759 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
764 void pc_machine_done(Notifier
*notifier
, void *data
)
766 PCMachineState
*pcms
= container_of(notifier
,
767 PCMachineState
, machine_done
);
768 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
770 cxl_hook_up_pxb_registers(pcms
->bus
, &pcms
->cxl_devices_state
,
773 if (pcms
->cxl_devices_state
.is_enabled
) {
774 cxl_fmws_link_targets(&pcms
->cxl_devices_state
, &error_fatal
);
777 /* set the number of CPUs */
778 x86_rtc_set_cpus_count(x86ms
->rtc
, x86ms
->boot_cpus
);
780 fw_cfg_add_extra_pci_roots(pcms
->bus
, x86ms
->fw_cfg
);
784 fw_cfg_build_smbios(MACHINE(pcms
), x86ms
->fw_cfg
);
785 fw_cfg_build_feature_control(MACHINE(pcms
), x86ms
->fw_cfg
);
786 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
787 fw_cfg_modify_i16(x86ms
->fw_cfg
, FW_CFG_NB_CPUS
, x86ms
->boot_cpus
);
791 void pc_guest_info_init(PCMachineState
*pcms
)
793 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
795 x86ms
->apic_xrupt_override
= true;
796 pcms
->machine_done
.notify
= pc_machine_done
;
797 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
800 /* setup pci memory address space mapping into system address space */
801 void pc_pci_as_mapping_init(MemoryRegion
*system_memory
,
802 MemoryRegion
*pci_address_space
)
804 /* Set to lower priority than RAM */
805 memory_region_add_subregion_overlap(system_memory
, 0x0,
806 pci_address_space
, -1);
809 void xen_load_linux(PCMachineState
*pcms
)
813 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
814 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
816 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
818 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
819 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, x86ms
->boot_cpus
);
822 x86_load_linux(x86ms
, fw_cfg
, pcmc
->acpi_data_size
,
824 for (i
= 0; i
< nb_option_roms
; i
++) {
825 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
826 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
827 !strcmp(option_rom
[i
].name
, "pvh.bin") ||
828 !strcmp(option_rom
[i
].name
, "multiboot.bin") ||
829 !strcmp(option_rom
[i
].name
, "multiboot_dma.bin"));
830 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
832 x86ms
->fw_cfg
= fw_cfg
;
835 #define PC_ROM_MIN_VGA 0xc0000
836 #define PC_ROM_MIN_OPTION 0xc8000
837 #define PC_ROM_MAX 0xe0000
838 #define PC_ROM_ALIGN 0x800
839 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
841 static hwaddr
pc_above_4g_end(PCMachineState
*pcms
)
843 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
845 if (pcms
->sgx_epc
.size
!= 0) {
846 return sgx_epc_above_4g_end(&pcms
->sgx_epc
);
849 return x86ms
->above_4g_mem_start
+ x86ms
->above_4g_mem_size
;
852 static void pc_get_device_memory_range(PCMachineState
*pcms
,
854 ram_addr_t
*device_mem_size
)
856 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
857 MachineState
*machine
= MACHINE(pcms
);
861 size
= machine
->maxram_size
- machine
->ram_size
;
862 addr
= ROUND_UP(pc_above_4g_end(pcms
), 1 * GiB
);
864 if (pcmc
->enforce_aligned_dimm
) {
865 /* size device region assuming 1G page max alignment per slot */
866 size
+= (1 * GiB
) * machine
->ram_slots
;
870 *device_mem_size
= size
;
873 static uint64_t pc_get_cxl_range_start(PCMachineState
*pcms
)
875 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
879 if (pcmc
->has_reserved_memory
) {
880 pc_get_device_memory_range(pcms
, &cxl_base
, &size
);
883 cxl_base
= pc_above_4g_end(pcms
);
889 static uint64_t pc_get_cxl_range_end(PCMachineState
*pcms
)
891 uint64_t start
= pc_get_cxl_range_start(pcms
) + MiB
;
893 if (pcms
->cxl_devices_state
.fixed_windows
) {
896 start
= ROUND_UP(start
, 256 * MiB
);
897 for (it
= pcms
->cxl_devices_state
.fixed_windows
; it
; it
= it
->next
) {
898 CXLFixedWindow
*fw
= it
->data
;
906 static hwaddr
pc_max_used_gpa(PCMachineState
*pcms
, uint64_t pci_hole64_size
)
908 X86CPU
*cpu
= X86_CPU(first_cpu
);
910 /* 32-bit systems don't have hole64 thus return max CPU address */
911 if (cpu
->phys_bits
<= 32) {
912 return ((hwaddr
)1 << cpu
->phys_bits
) - 1;
915 return pc_pci_hole64_start() + pci_hole64_size
- 1;
919 * AMD systems with an IOMMU have an additional hole close to the
920 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
921 * on kernel version, VFIO may or may not let you DMA map those ranges.
922 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
923 * with certain memory sizes. It's also wrong to use those IOVA ranges
924 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
925 * The ranges reserved for Hyper-Transport are:
927 * FD_0000_0000h - FF_FFFF_FFFFh
929 * The ranges represent the following:
931 * Base Address Top Address Use
933 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
934 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
935 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
936 * FD_F910_0000h FD_F91F_FFFFh System Management
937 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
938 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
939 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
940 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
941 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
942 * FE_2000_0000h FF_FFFF_FFFFh Reserved
944 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
945 * Table 3: Special Address Controls (GPA) for more information.
947 #define AMD_HT_START 0xfd00000000UL
948 #define AMD_HT_END 0xffffffffffUL
949 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
950 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
952 void pc_memory_init(PCMachineState
*pcms
,
953 MemoryRegion
*system_memory
,
954 MemoryRegion
*rom_memory
,
955 MemoryRegion
**ram_memory
,
956 uint64_t pci_hole64_size
)
959 MemoryRegion
*option_rom_mr
;
960 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
962 MachineState
*machine
= MACHINE(pcms
);
963 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
964 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
965 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
966 hwaddr maxphysaddr
, maxusedaddr
;
967 hwaddr cxl_base
, cxl_resv_end
= 0;
968 X86CPU
*cpu
= X86_CPU(first_cpu
);
970 assert(machine
->ram_size
== x86ms
->below_4g_mem_size
+
971 x86ms
->above_4g_mem_size
);
973 linux_boot
= (machine
->kernel_filename
!= NULL
);
976 * The HyperTransport range close to the 1T boundary is unique to AMD
977 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
978 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
979 * older machine types (<= 7.0) for compatibility purposes.
981 if (IS_AMD_CPU(&cpu
->env
) && pcmc
->enforce_amd_1tb_hole
) {
982 /* Bail out if max possible address does not cross HT range */
983 if (pc_max_used_gpa(pcms
, pci_hole64_size
) >= AMD_HT_START
) {
984 x86ms
->above_4g_mem_start
= AMD_ABOVE_1TB_START
;
988 * Advertise the HT region if address space covers the reserved
989 * region or if we relocate.
991 if (cpu
->phys_bits
>= 40) {
992 e820_add_entry(AMD_HT_START
, AMD_HT_SIZE
, E820_RESERVED
);
997 * phys-bits is required to be appropriately configured
998 * to make sure max used GPA is reachable.
1000 maxusedaddr
= pc_max_used_gpa(pcms
, pci_hole64_size
);
1001 maxphysaddr
= ((hwaddr
)1 << cpu
->phys_bits
) - 1;
1002 if (maxphysaddr
< maxusedaddr
) {
1003 error_report("Address space limit 0x%"PRIx64
" < 0x%"PRIx64
1004 " phys-bits too low (%u)",
1005 maxphysaddr
, maxusedaddr
, cpu
->phys_bits
);
1010 * Split single memory region and use aliases to address portions of it,
1011 * done for backwards compatibility with older qemus.
1013 *ram_memory
= machine
->ram
;
1014 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1015 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", machine
->ram
,
1016 0, x86ms
->below_4g_mem_size
);
1017 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1018 e820_add_entry(0, x86ms
->below_4g_mem_size
, E820_RAM
);
1019 if (x86ms
->above_4g_mem_size
> 0) {
1020 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1021 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g",
1023 x86ms
->below_4g_mem_size
,
1024 x86ms
->above_4g_mem_size
);
1025 memory_region_add_subregion(system_memory
, x86ms
->above_4g_mem_start
,
1027 e820_add_entry(x86ms
->above_4g_mem_start
, x86ms
->above_4g_mem_size
,
1031 if (pcms
->sgx_epc
.size
!= 0) {
1032 e820_add_entry(pcms
->sgx_epc
.base
, pcms
->sgx_epc
.size
, E820_RESERVED
);
1035 if (!pcmc
->has_reserved_memory
&&
1036 (machine
->ram_slots
||
1037 (machine
->maxram_size
> machine
->ram_size
))) {
1039 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1044 /* always allocate the device memory information */
1045 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1047 /* initialize device memory address space */
1048 if (pcmc
->has_reserved_memory
&&
1049 (machine
->ram_size
< machine
->maxram_size
)) {
1050 ram_addr_t device_mem_size
;
1052 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1053 error_report("unsupported amount of memory slots: %"PRIu64
,
1054 machine
->ram_slots
);
1058 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1059 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1060 error_report("maximum memory size must by aligned to multiple of "
1061 "%d bytes", TARGET_PAGE_SIZE
);
1065 pc_get_device_memory_range(pcms
, &machine
->device_memory
->base
, &device_mem_size
);
1067 if ((machine
->device_memory
->base
+ device_mem_size
) <
1069 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1070 machine
->maxram_size
);
1074 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1075 "device-memory", device_mem_size
);
1076 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1077 &machine
->device_memory
->mr
);
1080 if (pcms
->cxl_devices_state
.is_enabled
) {
1081 MemoryRegion
*mr
= &pcms
->cxl_devices_state
.host_mr
;
1082 hwaddr cxl_size
= MiB
;
1084 cxl_base
= pc_get_cxl_range_start(pcms
);
1085 memory_region_init(mr
, OBJECT(machine
), "cxl_host_reg", cxl_size
);
1086 memory_region_add_subregion(system_memory
, cxl_base
, mr
);
1087 cxl_resv_end
= cxl_base
+ cxl_size
;
1088 if (pcms
->cxl_devices_state
.fixed_windows
) {
1089 hwaddr cxl_fmw_base
;
1092 cxl_fmw_base
= ROUND_UP(cxl_base
+ cxl_size
, 256 * MiB
);
1093 for (it
= pcms
->cxl_devices_state
.fixed_windows
; it
; it
= it
->next
) {
1094 CXLFixedWindow
*fw
= it
->data
;
1096 fw
->base
= cxl_fmw_base
;
1097 memory_region_init_io(&fw
->mr
, OBJECT(machine
), &cfmws_ops
, fw
,
1098 "cxl-fixed-memory-region", fw
->size
);
1099 memory_region_add_subregion(system_memory
, fw
->base
, &fw
->mr
);
1100 cxl_fmw_base
+= fw
->size
;
1101 cxl_resv_end
= cxl_fmw_base
;
1106 /* Initialize PC system firmware */
1107 pc_system_firmware_init(pcms
, rom_memory
);
1109 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1110 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1112 if (pcmc
->pci_enabled
) {
1113 memory_region_set_readonly(option_rom_mr
, true);
1115 memory_region_add_subregion_overlap(rom_memory
,
1120 fw_cfg
= fw_cfg_arch_create(machine
,
1121 x86ms
->boot_cpus
, x86ms
->apic_id_limit
);
1125 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1126 uint64_t *val
= g_malloc(sizeof(*val
));
1127 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1128 uint64_t res_mem_end
= machine
->device_memory
->base
;
1130 if (!pcmc
->broken_reserved_end
) {
1131 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1134 if (pcms
->cxl_devices_state
.is_enabled
) {
1135 res_mem_end
= cxl_resv_end
;
1137 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1138 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1142 x86_load_linux(x86ms
, fw_cfg
, pcmc
->acpi_data_size
,
1146 for (i
= 0; i
< nb_option_roms
; i
++) {
1147 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1149 x86ms
->fw_cfg
= fw_cfg
;
1151 /* Init default IOAPIC address space */
1152 x86ms
->ioapic_as
= &address_space_memory
;
1154 /* Init ACPI memory hotplug IO base address */
1155 pcms
->memhp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
1159 * The 64bit pci hole starts after "above 4G RAM" and
1160 * potentially the space reserved for memory hotplug.
1162 uint64_t pc_pci_hole64_start(void)
1164 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1165 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1166 MachineState
*ms
= MACHINE(pcms
);
1167 uint64_t hole64_start
= 0;
1168 ram_addr_t size
= 0;
1170 if (pcms
->cxl_devices_state
.is_enabled
) {
1171 hole64_start
= pc_get_cxl_range_end(pcms
);
1172 } else if (pcmc
->has_reserved_memory
&& (ms
->ram_size
< ms
->maxram_size
)) {
1173 pc_get_device_memory_range(pcms
, &hole64_start
, &size
);
1174 if (!pcmc
->broken_reserved_end
) {
1175 hole64_start
+= size
;
1178 hole64_start
= pc_above_4g_end(pcms
);
1181 return ROUND_UP(hole64_start
, 1 * GiB
);
1184 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1186 DeviceState
*dev
= NULL
;
1188 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1190 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1191 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1192 } else if (isa_bus
) {
1193 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1194 dev
= isadev
? DEVICE(isadev
) : NULL
;
1196 rom_reset_order_override();
1200 static const MemoryRegionOps ioport80_io_ops
= {
1201 .write
= ioport80_write
,
1202 .read
= ioport80_read
,
1203 .endianness
= DEVICE_NATIVE_ENDIAN
,
1205 .min_access_size
= 1,
1206 .max_access_size
= 1,
1210 static const MemoryRegionOps ioportF0_io_ops
= {
1211 .write
= ioportF0_write
,
1212 .read
= ioportF0_read
,
1213 .endianness
= DEVICE_NATIVE_ENDIAN
,
1215 .min_access_size
= 1,
1216 .max_access_size
= 1,
1220 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
,
1221 bool create_i8042
, bool no_vmport
)
1224 DriveInfo
*fd
[MAX_FD
];
1226 ISADevice
*fdc
, *i8042
, *port92
, *vmmouse
;
1228 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1229 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1231 for (i
= 0; i
< MAX_FD
; i
++) {
1232 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1233 create_fdctrl
|= !!fd
[i
];
1235 if (create_fdctrl
) {
1236 fdc
= isa_new(TYPE_ISA_FDC
);
1238 isa_realize_and_unref(fdc
, isa_bus
, &error_fatal
);
1239 isa_fdc_init_drives(fdc
, fd
);
1243 if (!create_i8042
) {
1247 i8042
= isa_create_simple(isa_bus
, TYPE_I8042
);
1249 isa_create_simple(isa_bus
, TYPE_VMPORT
);
1250 vmmouse
= isa_try_new("vmmouse");
1255 object_property_set_link(OBJECT(vmmouse
), TYPE_I8042
, OBJECT(i8042
),
1257 isa_realize_and_unref(vmmouse
, isa_bus
, &error_fatal
);
1259 port92
= isa_create_simple(isa_bus
, TYPE_PORT92
);
1261 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1262 i8042_setup_a20_line(i8042
, a20_line
[0]);
1263 qdev_connect_gpio_out_named(DEVICE(port92
),
1264 PORT92_A20_LINE
, 0, a20_line
[1]);
1268 void pc_basic_device_init(struct PCMachineState
*pcms
,
1269 ISABus
*isa_bus
, qemu_irq
*gsi
,
1270 ISADevice
**rtc_state
,
1275 DeviceState
*hpet
= NULL
;
1276 int pit_isa_irq
= 0;
1277 qemu_irq pit_alt_irq
= NULL
;
1278 qemu_irq rtc_irq
= NULL
;
1279 ISADevice
*pit
= NULL
;
1280 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1281 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1282 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
1284 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1285 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1287 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1288 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1291 * Check if an HPET shall be created.
1293 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1294 * when the HPET wants to take over. Thus we have to disable the latter.
1296 if (pcms
->hpet_enabled
&& (!kvm_irqchip_in_kernel() ||
1297 kvm_has_pit_state2())) {
1298 hpet
= qdev_try_new(TYPE_HPET
);
1300 error_report("couldn't create HPET device");
1304 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1305 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1308 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1311 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1313 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet
), &error_fatal
);
1314 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1316 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1317 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1320 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1321 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1323 *rtc_state
= ISA_DEVICE(mc146818_rtc_init(isa_bus
, 2000, rtc_irq
));
1325 #ifdef CONFIG_XEN_EMU
1326 if (xen_mode
== XEN_EMULATE
) {
1327 xen_evtchn_connect_gsis(gsi
);
1329 pci_create_simple(pcms
->bus
, -1, "xen-platform");
1336 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1338 if (!xen_enabled() &&
1339 (x86ms
->pit
== ON_OFF_AUTO_AUTO
|| x86ms
->pit
== ON_OFF_AUTO_ON
)) {
1340 if (kvm_pit_in_kernel()) {
1341 pit
= kvm_pit_init(isa_bus
, 0x40);
1343 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1346 /* connect PIT to output control line of the HPET */
1347 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1349 pcspk_init(pcms
->pcspk
, isa_bus
, pit
);
1353 pc_superio_init(isa_bus
, create_fdctrl
, pcms
->i8042_enabled
,
1354 pcms
->vmport
!= ON_OFF_AUTO_ON
);
1357 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
1361 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
1362 for (i
= 0; i
< nb_nics
; i
++) {
1363 NICInfo
*nd
= &nd_table
[i
];
1364 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
1366 if (g_str_equal(model
, "ne2k_isa")) {
1367 pc_init_ne2k_isa(isa_bus
, nd
);
1369 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
1372 rom_reset_order_override();
1375 void pc_i8259_create(ISABus
*isa_bus
, qemu_irq
*i8259_irqs
)
1379 if (kvm_pic_in_kernel()) {
1380 i8259
= kvm_i8259_init(isa_bus
);
1381 } else if (xen_enabled()) {
1382 i8259
= xen_interrupt_controller_init();
1384 i8259
= i8259_init(isa_bus
, x86_allocate_cpu_irq());
1387 for (size_t i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1388 i8259_irqs
[i
] = i8259
[i
];
1394 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
1397 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1398 const X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1399 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1400 const MachineState
*ms
= MACHINE(hotplug_dev
);
1401 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1402 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
1403 Error
*local_err
= NULL
;
1406 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1407 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1408 * addition to cover this case.
1410 if (!x86ms
->acpi_dev
|| !x86_machine_is_acpi_enabled(x86ms
)) {
1412 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1416 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
1417 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1421 hotplug_handler_pre_plug(x86ms
->acpi_dev
, dev
, &local_err
);
1423 error_propagate(errp
, local_err
);
1427 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
1428 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
1431 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
1432 DeviceState
*dev
, Error
**errp
)
1434 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1435 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1436 MachineState
*ms
= MACHINE(hotplug_dev
);
1437 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
1439 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
));
1442 nvdimm_plug(ms
->nvdimms_state
);
1445 hotplug_handler_plug(x86ms
->acpi_dev
, dev
, &error_abort
);
1448 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
1449 DeviceState
*dev
, Error
**errp
)
1451 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1454 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1455 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1456 * addition to cover this case.
1458 if (!x86ms
->acpi_dev
|| !x86_machine_is_acpi_enabled(x86ms
)) {
1460 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1464 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
1465 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
1469 hotplug_handler_unplug_request(x86ms
->acpi_dev
, dev
,
1473 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
1474 DeviceState
*dev
, Error
**errp
)
1476 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1477 X86MachineState
*x86ms
= X86_MACHINE(hotplug_dev
);
1478 Error
*local_err
= NULL
;
1480 hotplug_handler_unplug(x86ms
->acpi_dev
, dev
, &local_err
);
1485 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
1486 qdev_unrealize(dev
);
1488 error_propagate(errp
, local_err
);
1491 static void pc_virtio_md_pci_pre_plug(HotplugHandler
*hotplug_dev
,
1492 DeviceState
*dev
, Error
**errp
)
1494 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
1495 Error
*local_err
= NULL
;
1497 if (!hotplug_dev2
&& dev
->hotplugged
) {
1499 * Without a bus hotplug handler, we cannot control the plug/unplug
1500 * order. We should never reach this point when hotplugging on x86,
1501 * however, better add a safety net.
1503 error_setg(errp
, "hotplug of virtio based memory devices not supported"
1508 * First, see if we can plug this memory device at all. If that
1509 * succeeds, branch of to the actual hotplug handler.
1511 memory_device_pre_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
), NULL
,
1513 if (!local_err
&& hotplug_dev2
) {
1514 hotplug_handler_pre_plug(hotplug_dev2
, dev
, &local_err
);
1516 error_propagate(errp
, local_err
);
1519 static void pc_virtio_md_pci_plug(HotplugHandler
*hotplug_dev
,
1520 DeviceState
*dev
, Error
**errp
)
1522 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
1523 Error
*local_err
= NULL
;
1526 * Plug the memory device first and then branch off to the actual
1527 * hotplug handler. If that one fails, we can easily undo the memory
1530 memory_device_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
1532 hotplug_handler_plug(hotplug_dev2
, dev
, &local_err
);
1534 memory_device_unplug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
1537 error_propagate(errp
, local_err
);
1540 static void pc_virtio_md_pci_unplug_request(HotplugHandler
*hotplug_dev
,
1541 DeviceState
*dev
, Error
**errp
)
1543 /* We don't support hot unplug of virtio based memory devices */
1544 error_setg(errp
, "virtio based memory devices cannot be unplugged.");
1547 static void pc_virtio_md_pci_unplug(HotplugHandler
*hotplug_dev
,
1548 DeviceState
*dev
, Error
**errp
)
1550 /* We don't support hot unplug of virtio based memory devices */
1553 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
1554 DeviceState
*dev
, Error
**errp
)
1556 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1557 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
1558 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1559 x86_cpu_pre_plug(hotplug_dev
, dev
, errp
);
1560 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
) ||
1561 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
1562 pc_virtio_md_pci_pre_plug(hotplug_dev
, dev
, errp
);
1563 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
1564 /* Declare the APIC range as the reserved MSI region */
1565 char *resv_prop_str
= g_strdup_printf("0xfee00000:0xfeefffff:%d",
1566 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
1568 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
1569 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
1570 resv_prop_str
, errp
);
1571 g_free(resv_prop_str
);
1574 if (object_dynamic_cast(OBJECT(dev
), TYPE_X86_IOMMU_DEVICE
) ||
1575 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
1576 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1579 error_setg(errp
, "QEMU does not support multiple vIOMMUs "
1587 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1588 DeviceState
*dev
, Error
**errp
)
1590 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1591 pc_memory_plug(hotplug_dev
, dev
, errp
);
1592 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1593 x86_cpu_plug(hotplug_dev
, dev
, errp
);
1594 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
) ||
1595 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
1596 pc_virtio_md_pci_plug(hotplug_dev
, dev
, errp
);
1600 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
1601 DeviceState
*dev
, Error
**errp
)
1603 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1604 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
1605 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1606 x86_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
1607 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
) ||
1608 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
1609 pc_virtio_md_pci_unplug_request(hotplug_dev
, dev
, errp
);
1611 error_setg(errp
, "acpi: device unplug request for not supported device"
1612 " type: %s", object_get_typename(OBJECT(dev
)));
1616 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
1617 DeviceState
*dev
, Error
**errp
)
1619 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1620 pc_memory_unplug(hotplug_dev
, dev
, errp
);
1621 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1622 x86_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
1623 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
) ||
1624 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
1625 pc_virtio_md_pci_unplug(hotplug_dev
, dev
, errp
);
1627 error_setg(errp
, "acpi: device unplug for not supported device"
1628 " type: %s", object_get_typename(OBJECT(dev
)));
1632 static HotplugHandler
*pc_get_hotplug_handler(MachineState
*machine
,
1635 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
1636 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
) ||
1637 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
) ||
1638 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
) ||
1639 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
) ||
1640 object_dynamic_cast(OBJECT(dev
), TYPE_X86_IOMMU_DEVICE
)) {
1641 return HOTPLUG_HANDLER(machine
);
1648 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
1649 const char *name
, void *opaque
,
1652 MachineState
*ms
= MACHINE(obj
);
1655 if (ms
->device_memory
) {
1656 value
= memory_region_size(&ms
->device_memory
->mr
);
1659 visit_type_int(v
, name
, &value
, errp
);
1662 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
1663 void *opaque
, Error
**errp
)
1665 PCMachineState
*pcms
= PC_MACHINE(obj
);
1666 OnOffAuto vmport
= pcms
->vmport
;
1668 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
1671 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
1672 void *opaque
, Error
**errp
)
1674 PCMachineState
*pcms
= PC_MACHINE(obj
);
1676 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
1679 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
1681 PCMachineState
*pcms
= PC_MACHINE(obj
);
1683 return pcms
->smbus_enabled
;
1686 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
1688 PCMachineState
*pcms
= PC_MACHINE(obj
);
1690 pcms
->smbus_enabled
= value
;
1693 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
1695 PCMachineState
*pcms
= PC_MACHINE(obj
);
1697 return pcms
->sata_enabled
;
1700 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
1702 PCMachineState
*pcms
= PC_MACHINE(obj
);
1704 pcms
->sata_enabled
= value
;
1707 static bool pc_machine_get_hpet(Object
*obj
, Error
**errp
)
1709 PCMachineState
*pcms
= PC_MACHINE(obj
);
1711 return pcms
->hpet_enabled
;
1714 static void pc_machine_set_hpet(Object
*obj
, bool value
, Error
**errp
)
1716 PCMachineState
*pcms
= PC_MACHINE(obj
);
1718 pcms
->hpet_enabled
= value
;
1721 static bool pc_machine_get_i8042(Object
*obj
, Error
**errp
)
1723 PCMachineState
*pcms
= PC_MACHINE(obj
);
1725 return pcms
->i8042_enabled
;
1728 static void pc_machine_set_i8042(Object
*obj
, bool value
, Error
**errp
)
1730 PCMachineState
*pcms
= PC_MACHINE(obj
);
1732 pcms
->i8042_enabled
= value
;
1735 static bool pc_machine_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
1737 PCMachineState
*pcms
= PC_MACHINE(obj
);
1739 return pcms
->default_bus_bypass_iommu
;
1742 static void pc_machine_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
1745 PCMachineState
*pcms
= PC_MACHINE(obj
);
1747 pcms
->default_bus_bypass_iommu
= value
;
1750 static void pc_machine_get_smbios_ep(Object
*obj
, Visitor
*v
, const char *name
,
1751 void *opaque
, Error
**errp
)
1753 PCMachineState
*pcms
= PC_MACHINE(obj
);
1754 SmbiosEntryPointType smbios_entry_point_type
= pcms
->smbios_entry_point_type
;
1756 visit_type_SmbiosEntryPointType(v
, name
, &smbios_entry_point_type
, errp
);
1759 static void pc_machine_set_smbios_ep(Object
*obj
, Visitor
*v
, const char *name
,
1760 void *opaque
, Error
**errp
)
1762 PCMachineState
*pcms
= PC_MACHINE(obj
);
1764 visit_type_SmbiosEntryPointType(v
, name
, &pcms
->smbios_entry_point_type
, errp
);
1767 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1768 const char *name
, void *opaque
,
1771 PCMachineState
*pcms
= PC_MACHINE(obj
);
1772 uint64_t value
= pcms
->max_ram_below_4g
;
1774 visit_type_size(v
, name
, &value
, errp
);
1777 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1778 const char *name
, void *opaque
,
1781 PCMachineState
*pcms
= PC_MACHINE(obj
);
1784 if (!visit_type_size(v
, name
, &value
, errp
)) {
1787 if (value
> 4 * GiB
) {
1789 "Machine option 'max-ram-below-4g=%"PRIu64
1790 "' expects size less than or equal to 4G", value
);
1794 if (value
< 1 * MiB
) {
1795 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
1796 "BIOS may not work with less than 1MiB", value
);
1799 pcms
->max_ram_below_4g
= value
;
1802 static void pc_machine_get_max_fw_size(Object
*obj
, Visitor
*v
,
1803 const char *name
, void *opaque
,
1806 PCMachineState
*pcms
= PC_MACHINE(obj
);
1807 uint64_t value
= pcms
->max_fw_size
;
1809 visit_type_size(v
, name
, &value
, errp
);
1812 static void pc_machine_set_max_fw_size(Object
*obj
, Visitor
*v
,
1813 const char *name
, void *opaque
,
1816 PCMachineState
*pcms
= PC_MACHINE(obj
);
1819 if (!visit_type_size(v
, name
, &value
, errp
)) {
1824 * We don't have a theoretically justifiable exact lower bound on the base
1825 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1826 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1827 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1830 if (value
> 16 * MiB
) {
1832 "User specified max allowed firmware size %" PRIu64
" is "
1833 "greater than 16MiB. If combined firwmare size exceeds "
1834 "16MiB the system may not boot, or experience intermittent"
1835 "stability issues.",
1840 pcms
->max_fw_size
= value
;
1844 static void pc_machine_initfn(Object
*obj
)
1846 PCMachineState
*pcms
= PC_MACHINE(obj
);
1848 #ifdef CONFIG_VMPORT
1849 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
1851 pcms
->vmport
= ON_OFF_AUTO_OFF
;
1852 #endif /* CONFIG_VMPORT */
1853 pcms
->max_ram_below_4g
= 0; /* use default */
1854 pcms
->smbios_entry_point_type
= SMBIOS_ENTRY_POINT_TYPE_32
;
1856 /* acpi build is enabled by default if machine supports it */
1857 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
1858 pcms
->smbus_enabled
= true;
1859 pcms
->sata_enabled
= true;
1860 pcms
->i8042_enabled
= true;
1861 pcms
->max_fw_size
= 8 * MiB
;
1863 pcms
->hpet_enabled
= true;
1865 pcms
->default_bus_bypass_iommu
= false;
1867 pc_system_flash_create(pcms
);
1868 pcms
->pcspk
= isa_new(TYPE_PC_SPEAKER
);
1869 object_property_add_alias(OBJECT(pcms
), "pcspk-audiodev",
1870 OBJECT(pcms
->pcspk
), "audiodev");
1871 cxl_machine_init(obj
, &pcms
->cxl_devices_state
);
1874 int pc_machine_kvm_type(MachineState
*machine
, const char *kvm_type
)
1876 #ifdef CONFIG_XEN_EMU
1877 if (xen_mode
== XEN_EMULATE
) {
1878 xen_overlay_create();
1879 xen_evtchn_create();
1880 xen_gnttab_create();
1881 xen_xenstore_create();
1887 static void pc_machine_reset(MachineState
*machine
, ShutdownCause reason
)
1892 qemu_devices_reset(reason
);
1894 /* Reset APIC after devices have been reset to cancel
1895 * any changes that qemu_devices_reset() might have done.
1900 x86_cpu_after_reset(cpu
);
1904 static void pc_machine_wakeup(MachineState
*machine
)
1906 cpu_synchronize_all_states();
1907 pc_machine_reset(machine
, SHUTDOWN_CAUSE_NONE
);
1908 cpu_synchronize_all_post_reset();
1911 static bool pc_hotplug_allowed(MachineState
*ms
, DeviceState
*dev
, Error
**errp
)
1913 X86IOMMUState
*iommu
= x86_iommu_get_default();
1914 IntelIOMMUState
*intel_iommu
;
1917 object_dynamic_cast((Object
*)iommu
, TYPE_INTEL_IOMMU_DEVICE
) &&
1918 object_dynamic_cast((Object
*)dev
, "vfio-pci")) {
1919 intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
1920 if (!intel_iommu
->caching_mode
) {
1921 error_setg(errp
, "Device assignment is not allowed without "
1922 "enabling caching-mode=on for Intel IOMMU.");
1930 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
1932 MachineClass
*mc
= MACHINE_CLASS(oc
);
1933 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
1934 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1936 pcmc
->pci_enabled
= true;
1937 pcmc
->has_acpi_build
= true;
1938 pcmc
->rsdp_in_ram
= true;
1939 pcmc
->smbios_defaults
= true;
1940 pcmc
->smbios_uuid_encoded
= true;
1941 pcmc
->gigabyte_align
= true;
1942 pcmc
->has_reserved_memory
= true;
1943 pcmc
->kvmclock_enabled
= true;
1944 pcmc
->enforce_aligned_dimm
= true;
1945 pcmc
->enforce_amd_1tb_hole
= true;
1946 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1947 * to be used at the moment, 32K should be enough for a while. */
1948 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
1949 pcmc
->pvh_enabled
= true;
1950 pcmc
->kvmclock_create_always
= true;
1951 pcmc
->resizable_acpi_blob
= true;
1952 assert(!mc
->get_hotplug_handler
);
1953 mc
->get_hotplug_handler
= pc_get_hotplug_handler
;
1954 mc
->hotplug_allowed
= pc_hotplug_allowed
;
1955 mc
->cpu_index_to_instance_props
= x86_cpu_index_to_props
;
1956 mc
->get_default_cpu_node_id
= x86_get_default_cpu_node_id
;
1957 mc
->possible_cpu_arch_ids
= x86_possible_cpu_arch_ids
;
1958 mc
->auto_enable_numa_with_memhp
= true;
1959 mc
->auto_enable_numa_with_memdev
= true;
1960 mc
->has_hotpluggable_cpus
= true;
1961 mc
->default_boot_order
= "cad";
1962 mc
->block_default_type
= IF_IDE
;
1964 mc
->reset
= pc_machine_reset
;
1965 mc
->wakeup
= pc_machine_wakeup
;
1966 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
1967 hc
->plug
= pc_machine_device_plug_cb
;
1968 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
1969 hc
->unplug
= pc_machine_device_unplug_cb
;
1970 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
1971 mc
->nvdimm_supported
= true;
1972 mc
->smp_props
.dies_supported
= true;
1973 mc
->default_ram_id
= "pc.ram";
1975 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
1976 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
1978 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
1979 "Maximum ram below the 4G boundary (32bit boundary)");
1981 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
1982 pc_machine_get_device_memory_region_size
, NULL
,
1985 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
1986 pc_machine_get_vmport
, pc_machine_set_vmport
,
1988 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
1989 "Enable vmport (pc & q35)");
1991 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
1992 pc_machine_get_smbus
, pc_machine_set_smbus
);
1993 object_class_property_set_description(oc
, PC_MACHINE_SMBUS
,
1994 "Enable/disable system management bus");
1996 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
1997 pc_machine_get_sata
, pc_machine_set_sata
);
1998 object_class_property_set_description(oc
, PC_MACHINE_SATA
,
1999 "Enable/disable Serial ATA bus");
2001 object_class_property_add_bool(oc
, "hpet",
2002 pc_machine_get_hpet
, pc_machine_set_hpet
);
2003 object_class_property_set_description(oc
, "hpet",
2004 "Enable/disable high precision event timer emulation");
2006 object_class_property_add_bool(oc
, PC_MACHINE_I8042
,
2007 pc_machine_get_i8042
, pc_machine_set_i8042
);
2009 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
2010 pc_machine_get_default_bus_bypass_iommu
,
2011 pc_machine_set_default_bus_bypass_iommu
);
2013 object_class_property_add(oc
, PC_MACHINE_MAX_FW_SIZE
, "size",
2014 pc_machine_get_max_fw_size
, pc_machine_set_max_fw_size
,
2016 object_class_property_set_description(oc
, PC_MACHINE_MAX_FW_SIZE
,
2017 "Maximum combined firmware size");
2019 object_class_property_add(oc
, PC_MACHINE_SMBIOS_EP
, "str",
2020 pc_machine_get_smbios_ep
, pc_machine_set_smbios_ep
,
2022 object_class_property_set_description(oc
, PC_MACHINE_SMBIOS_EP
,
2023 "SMBIOS Entry Point type [32, 64]");
2026 static const TypeInfo pc_machine_info
= {
2027 .name
= TYPE_PC_MACHINE
,
2028 .parent
= TYPE_X86_MACHINE
,
2030 .instance_size
= sizeof(PCMachineState
),
2031 .instance_init
= pc_machine_initfn
,
2032 .class_size
= sizeof(PCMachineClass
),
2033 .class_init
= pc_machine_class_init
,
2034 .interfaces
= (InterfaceInfo
[]) {
2035 { TYPE_HOTPLUG_HANDLER
},
2040 static void pc_machine_register_types(void)
2042 type_register_static(&pc_machine_info
);
2045 type_init(pc_machine_register_types
)