2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/cpu/icc_bus.h"
57 #include "hw/boards.h"
58 #include "hw/pci/pci_host.h"
59 #include "acpi-build.h"
61 /* debug PC/ISA interrupts */
65 #define DPRINTF(fmt, ...) \
66 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
68 #define DPRINTF(fmt, ...)
71 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
72 #define ACPI_DATA_SIZE 0x10000
73 #define BIOS_CFG_IOPORT 0x510
74 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
75 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
76 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
77 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
78 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
80 #define E820_NR_ENTRIES 16
86 } QEMU_PACKED
__attribute((__aligned__(4)));
90 struct e820_entry entry
[E820_NR_ENTRIES
];
91 } QEMU_PACKED
__attribute((__aligned__(4)));
93 static struct e820_table e820_table
;
94 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
96 void gsi_handler(void *opaque
, int n
, int level
)
100 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
101 if (n
< ISA_NUM_IRQS
) {
102 qemu_set_irq(s
->i8259_irq
[n
], level
);
104 qemu_set_irq(s
->ioapic_irq
[n
], level
);
107 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
112 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
114 return 0xffffffffffffffffULL
;
117 /* MSDOS compatibility mode FPU exception support */
118 static qemu_irq ferr_irq
;
120 void pc_register_ferr_irq(qemu_irq irq
)
125 /* XXX: add IGNNE support */
126 void cpu_set_ferr(CPUX86State
*s
)
128 qemu_irq_raise(ferr_irq
);
131 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
134 qemu_irq_lower(ferr_irq
);
137 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
139 return 0xffffffffffffffffULL
;
143 uint64_t cpu_get_tsc(CPUX86State
*env
)
145 return cpu_get_ticks();
150 static cpu_set_smm_t smm_set
;
151 static void *smm_arg
;
153 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
155 assert(smm_set
== NULL
);
156 assert(smm_arg
== NULL
);
161 void cpu_smm_update(CPUX86State
*env
)
163 if (smm_set
&& smm_arg
&& CPU(x86_env_get_cpu(env
)) == first_cpu
) {
164 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
170 int cpu_get_pic_interrupt(CPUX86State
*env
)
174 intno
= apic_get_interrupt(env
->apic_state
);
178 /* read the irq from the PIC */
179 if (!apic_accept_pic_intr(env
->apic_state
)) {
183 intno
= pic_read_irq(isa_pic
);
187 static void pic_irq_request(void *opaque
, int irq
, int level
)
189 CPUState
*cs
= first_cpu
;
190 X86CPU
*cpu
= X86_CPU(cs
);
191 CPUX86State
*env
= &cpu
->env
;
193 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
194 if (env
->apic_state
) {
198 if (apic_accept_pic_intr(env
->apic_state
)) {
199 apic_deliver_pic_intr(env
->apic_state
, level
);
204 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
206 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
211 /* PC cmos mappings */
213 #define REG_EQUIPMENT_BYTE 0x14
215 static int cmos_get_fd_drive_type(FDriveType fd0
)
221 /* 1.44 Mb 3"5 drive */
225 /* 2.88 Mb 3"5 drive */
229 /* 1.2 Mb 5"5 drive */
232 case FDRIVE_DRV_NONE
:
240 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
241 int16_t cylinders
, int8_t heads
, int8_t sectors
)
243 rtc_set_memory(s
, type_ofs
, 47);
244 rtc_set_memory(s
, info_ofs
, cylinders
);
245 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
246 rtc_set_memory(s
, info_ofs
+ 2, heads
);
247 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
248 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
249 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
250 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
251 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
252 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
255 /* convert boot_device letter to something recognizable by the bios */
256 static int boot_device2nibble(char boot_device
)
258 switch(boot_device
) {
261 return 0x01; /* floppy boot */
263 return 0x02; /* hard drive boot */
265 return 0x03; /* CD-ROM boot */
267 return 0x04; /* Network boot */
272 static int set_boot_dev(ISADevice
*s
, const char *boot_device
)
274 #define PC_MAX_BOOT_DEVICES 3
275 int nbds
, bds
[3] = { 0, };
278 nbds
= strlen(boot_device
);
279 if (nbds
> PC_MAX_BOOT_DEVICES
) {
280 error_report("Too many boot devices for PC");
283 for (i
= 0; i
< nbds
; i
++) {
284 bds
[i
] = boot_device2nibble(boot_device
[i
]);
286 error_report("Invalid boot device for PC: '%c'",
291 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
292 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
296 static int pc_boot_set(void *opaque
, const char *boot_device
)
298 return set_boot_dev(opaque
, boot_device
);
301 typedef struct pc_cmos_init_late_arg
{
302 ISADevice
*rtc_state
;
304 } pc_cmos_init_late_arg
;
306 static void pc_cmos_init_late(void *opaque
)
308 pc_cmos_init_late_arg
*arg
= opaque
;
309 ISADevice
*s
= arg
->rtc_state
;
311 int8_t heads
, sectors
;
316 if (ide_get_geometry(arg
->idebus
[0], 0,
317 &cylinders
, &heads
, §ors
) >= 0) {
318 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
321 if (ide_get_geometry(arg
->idebus
[0], 1,
322 &cylinders
, &heads
, §ors
) >= 0) {
323 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
326 rtc_set_memory(s
, 0x12, val
);
329 for (i
= 0; i
< 4; i
++) {
330 /* NOTE: ide_get_geometry() returns the physical
331 geometry. It is always such that: 1 <= sects <= 63, 1
332 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
333 geometry can be different if a translation is done. */
334 if (ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
335 &cylinders
, &heads
, §ors
) >= 0) {
336 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
337 assert((trans
& ~3) == 0);
338 val
|= trans
<< (i
* 2);
341 rtc_set_memory(s
, 0x39, val
);
343 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
346 typedef struct RTCCPUHotplugArg
{
347 Notifier cpu_added_notifier
;
348 ISADevice
*rtc_state
;
351 static void rtc_notify_cpu_added(Notifier
*notifier
, void *data
)
353 RTCCPUHotplugArg
*arg
= container_of(notifier
, RTCCPUHotplugArg
,
355 ISADevice
*s
= arg
->rtc_state
;
357 /* increment the number of CPUs */
358 rtc_set_memory(s
, 0x5f, rtc_get_memory(s
, 0x5f) + 1);
361 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
362 const char *boot_device
,
363 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
367 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
368 static pc_cmos_init_late_arg arg
;
369 static RTCCPUHotplugArg cpu_hotplug_cb
;
371 /* various important CMOS locations needed by PC/Bochs bios */
374 /* base memory (first MiB) */
375 val
= MIN(ram_size
/ 1024, 640);
376 rtc_set_memory(s
, 0x15, val
);
377 rtc_set_memory(s
, 0x16, val
>> 8);
378 /* extended memory (next 64MiB) */
379 if (ram_size
> 1024 * 1024) {
380 val
= (ram_size
- 1024 * 1024) / 1024;
386 rtc_set_memory(s
, 0x17, val
);
387 rtc_set_memory(s
, 0x18, val
>> 8);
388 rtc_set_memory(s
, 0x30, val
);
389 rtc_set_memory(s
, 0x31, val
>> 8);
390 /* memory between 16MiB and 4GiB */
391 if (ram_size
> 16 * 1024 * 1024) {
392 val
= (ram_size
- 16 * 1024 * 1024) / 65536;
398 rtc_set_memory(s
, 0x34, val
);
399 rtc_set_memory(s
, 0x35, val
>> 8);
400 /* memory above 4GiB */
401 val
= above_4g_mem_size
/ 65536;
402 rtc_set_memory(s
, 0x5b, val
);
403 rtc_set_memory(s
, 0x5c, val
>> 8);
404 rtc_set_memory(s
, 0x5d, val
>> 16);
406 /* set the number of CPU */
407 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
408 /* init CPU hotplug notifier */
409 cpu_hotplug_cb
.rtc_state
= s
;
410 cpu_hotplug_cb
.cpu_added_notifier
.notify
= rtc_notify_cpu_added
;
411 qemu_register_cpu_added_notifier(&cpu_hotplug_cb
.cpu_added_notifier
);
413 if (set_boot_dev(s
, boot_device
)) {
419 for (i
= 0; i
< 2; i
++) {
420 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
423 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
424 cmos_get_fd_drive_type(fd_type
[1]);
425 rtc_set_memory(s
, 0x10, val
);
429 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
432 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
439 val
|= 0x01; /* 1 drive, ready for boot */
442 val
|= 0x41; /* 2 drives, ready for boot */
445 val
|= 0x02; /* FPU is there */
446 val
|= 0x04; /* PS/2 mouse installed */
447 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
451 arg
.idebus
[0] = idebus0
;
452 arg
.idebus
[1] = idebus1
;
453 qemu_register_reset(pc_cmos_init_late
, &arg
);
456 #define TYPE_PORT92 "port92"
457 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
459 /* port 92 stuff: could be split off */
460 typedef struct Port92State
{
461 ISADevice parent_obj
;
468 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
471 Port92State
*s
= opaque
;
473 DPRINTF("port92: write 0x%02x\n", val
);
475 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
477 qemu_system_reset_request();
481 static uint64_t port92_read(void *opaque
, hwaddr addr
,
484 Port92State
*s
= opaque
;
488 DPRINTF("port92: read 0x%02x\n", ret
);
492 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
494 Port92State
*s
= PORT92(dev
);
496 s
->a20_out
= a20_out
;
499 static const VMStateDescription vmstate_port92_isa
= {
502 .minimum_version_id
= 1,
503 .minimum_version_id_old
= 1,
504 .fields
= (VMStateField
[]) {
505 VMSTATE_UINT8(outport
, Port92State
),
506 VMSTATE_END_OF_LIST()
510 static void port92_reset(DeviceState
*d
)
512 Port92State
*s
= PORT92(d
);
517 static const MemoryRegionOps port92_ops
= {
519 .write
= port92_write
,
521 .min_access_size
= 1,
522 .max_access_size
= 1,
524 .endianness
= DEVICE_LITTLE_ENDIAN
,
527 static void port92_initfn(Object
*obj
)
529 Port92State
*s
= PORT92(obj
);
531 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
536 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
538 ISADevice
*isadev
= ISA_DEVICE(dev
);
539 Port92State
*s
= PORT92(dev
);
541 isa_register_ioport(isadev
, &s
->io
, 0x92);
544 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
546 DeviceClass
*dc
= DEVICE_CLASS(klass
);
549 dc
->realize
= port92_realizefn
;
550 dc
->reset
= port92_reset
;
551 dc
->vmsd
= &vmstate_port92_isa
;
554 static const TypeInfo port92_info
= {
556 .parent
= TYPE_ISA_DEVICE
,
557 .instance_size
= sizeof(Port92State
),
558 .instance_init
= port92_initfn
,
559 .class_init
= port92_class_initfn
,
562 static void port92_register_types(void)
564 type_register_static(&port92_info
);
567 type_init(port92_register_types
)
569 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
571 X86CPU
*cpu
= opaque
;
573 /* XXX: send to all CPUs ? */
574 /* XXX: add logic to handle multiple A20 line sources */
575 x86_cpu_set_a20(cpu
, level
);
578 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
580 int index
= le32_to_cpu(e820_table
.count
);
581 struct e820_entry
*entry
;
583 if (index
>= E820_NR_ENTRIES
)
585 entry
= &e820_table
.entry
[index
++];
587 entry
->address
= cpu_to_le64(address
);
588 entry
->length
= cpu_to_le64(length
);
589 entry
->type
= cpu_to_le32(type
);
591 e820_table
.count
= cpu_to_le32(index
);
595 /* Calculates the limit to CPU APIC ID values
597 * This function returns the limit for the APIC ID value, so that all
598 * CPU APIC IDs are < pc_apic_id_limit().
600 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
602 static unsigned int pc_apic_id_limit(unsigned int max_cpus
)
604 return x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
607 static FWCfgState
*bochs_bios_init(void)
610 uint8_t *smbios_table
;
612 uint64_t *numa_fw_cfg
;
614 unsigned int apic_id_limit
= pc_apic_id_limit(max_cpus
);
616 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
617 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
619 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
620 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
621 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
622 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
625 * So, this means we must not use max_cpus, here, but the maximum possible
626 * APIC ID value, plus one.
628 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
629 * the APIC ID, not the "CPU index"
631 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)apic_id_limit
);
632 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
633 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
634 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
635 acpi_tables
, acpi_tables_len
);
636 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
638 smbios_table
= smbios_get_table(&smbios_len
);
640 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
641 smbios_table
, smbios_len
);
642 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
643 &e820_table
, sizeof(e820_table
));
645 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
646 /* allocate memory for the NUMA channel: one (64bit) word for the number
647 * of nodes, one word for each VCPU->node and one word for each node to
648 * hold the amount of memory.
650 numa_fw_cfg
= g_new0(uint64_t, 1 + apic_id_limit
+ nb_numa_nodes
);
651 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
652 for (i
= 0; i
< max_cpus
; i
++) {
653 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
654 assert(apic_id
< apic_id_limit
);
655 for (j
= 0; j
< nb_numa_nodes
; j
++) {
656 if (test_bit(i
, node_cpumask
[j
])) {
657 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(j
);
662 for (i
= 0; i
< nb_numa_nodes
; i
++) {
663 numa_fw_cfg
[apic_id_limit
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
665 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
666 (1 + apic_id_limit
+ nb_numa_nodes
) *
667 sizeof(*numa_fw_cfg
));
672 static long get_file_size(FILE *f
)
676 /* XXX: on Unix systems, using fstat() probably makes more sense */
679 fseek(f
, 0, SEEK_END
);
681 fseek(f
, where
, SEEK_SET
);
686 static void load_linux(FWCfgState
*fw_cfg
,
687 const char *kernel_filename
,
688 const char *initrd_filename
,
689 const char *kernel_cmdline
,
693 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
695 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
696 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
700 /* Align to 16 bytes as a paranoia measure */
701 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
703 /* load the kernel header */
704 f
= fopen(kernel_filename
, "rb");
705 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
706 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
707 MIN(ARRAY_SIZE(header
), kernel_size
)) {
708 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
709 kernel_filename
, strerror(errno
));
713 /* kernel protocol version */
715 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
717 if (ldl_p(header
+0x202) == 0x53726448) {
718 protocol
= lduw_p(header
+0x206);
720 /* This looks like a multiboot kernel. If it is, let's stop
721 treating it like a Linux kernel. */
722 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
723 kernel_cmdline
, kernel_size
, header
)) {
729 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
732 cmdline_addr
= 0x9a000 - cmdline_size
;
734 } else if (protocol
< 0x202) {
735 /* High but ancient kernel */
737 cmdline_addr
= 0x9a000 - cmdline_size
;
738 prot_addr
= 0x100000;
740 /* High and recent kernel */
742 cmdline_addr
= 0x20000;
743 prot_addr
= 0x100000;
748 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
749 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
750 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
756 /* highest address for loading the initrd */
757 if (protocol
>= 0x203) {
758 initrd_max
= ldl_p(header
+0x22c);
760 initrd_max
= 0x37ffffff;
763 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
764 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
766 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
767 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
768 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
770 if (protocol
>= 0x202) {
771 stl_p(header
+0x228, cmdline_addr
);
773 stw_p(header
+0x20, 0xA33F);
774 stw_p(header
+0x22, cmdline_addr
-real_addr
);
777 /* handle vga= parameter */
778 vmode
= strstr(kernel_cmdline
, "vga=");
780 unsigned int video_mode
;
783 if (!strncmp(vmode
, "normal", 6)) {
785 } else if (!strncmp(vmode
, "ext", 3)) {
787 } else if (!strncmp(vmode
, "ask", 3)) {
790 video_mode
= strtol(vmode
, NULL
, 0);
792 stw_p(header
+0x1fa, video_mode
);
796 /* High nybble = B reserved for QEMU; low nybble is revision number.
797 If this code is substantially changed, you may want to consider
798 incrementing the revision. */
799 if (protocol
>= 0x200) {
800 header
[0x210] = 0xB0;
803 if (protocol
>= 0x201) {
804 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
805 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
809 if (initrd_filename
) {
810 if (protocol
< 0x200) {
811 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
815 initrd_size
= get_image_size(initrd_filename
);
816 if (initrd_size
< 0) {
817 fprintf(stderr
, "qemu: error reading initrd %s\n",
822 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
824 initrd_data
= g_malloc(initrd_size
);
825 load_image(initrd_filename
, initrd_data
);
827 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
828 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
829 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
831 stl_p(header
+0x218, initrd_addr
);
832 stl_p(header
+0x21c, initrd_size
);
835 /* load kernel and setup */
836 setup_size
= header
[0x1f1];
837 if (setup_size
== 0) {
840 setup_size
= (setup_size
+1)*512;
841 kernel_size
-= setup_size
;
843 setup
= g_malloc(setup_size
);
844 kernel
= g_malloc(kernel_size
);
845 fseek(f
, 0, SEEK_SET
);
846 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
847 fprintf(stderr
, "fread() failed\n");
850 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
851 fprintf(stderr
, "fread() failed\n");
855 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
857 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
858 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
859 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
861 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
862 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
863 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
865 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
866 option_rom
[nb_option_roms
].bootindex
= 0;
870 #define NE2000_NB_MAX 6
872 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
874 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
876 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
877 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
879 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
881 static int nb_ne2k
= 0;
883 if (nb_ne2k
== NE2000_NB_MAX
)
885 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
886 ne2000_irq
[nb_ne2k
], nd
);
890 DeviceState
*cpu_get_current_apic(void)
893 X86CPU
*cpu
= X86_CPU(current_cpu
);
894 return cpu
->env
.apic_state
;
900 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
902 X86CPU
*cpu
= opaque
;
905 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
909 static X86CPU
*pc_new_cpu(const char *cpu_model
, int64_t apic_id
,
910 DeviceState
*icc_bridge
, Error
**errp
)
913 Error
*local_err
= NULL
;
915 cpu
= cpu_x86_create(cpu_model
, icc_bridge
, &local_err
);
916 if (local_err
!= NULL
) {
917 error_propagate(errp
, local_err
);
921 object_property_set_int(OBJECT(cpu
), apic_id
, "apic-id", &local_err
);
922 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
925 error_propagate(errp
, local_err
);
926 object_unref(OBJECT(cpu
));
932 static const char *current_cpu_model
;
934 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
936 DeviceState
*icc_bridge
;
937 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
940 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
944 if (cpu_exists(apic_id
)) {
945 error_setg(errp
, "Unable to add CPU: %" PRIi64
946 ", it already exists", id
);
950 if (id
>= max_cpus
) {
951 error_setg(errp
, "Unable to add CPU: %" PRIi64
952 ", max allowed: %d", id
, max_cpus
- 1);
956 icc_bridge
= DEVICE(object_resolve_path_type("icc-bridge",
957 TYPE_ICC_BRIDGE
, NULL
));
958 pc_new_cpu(current_cpu_model
, apic_id
, icc_bridge
, errp
);
961 void pc_cpus_init(const char *cpu_model
, DeviceState
*icc_bridge
)
968 if (cpu_model
== NULL
) {
970 cpu_model
= "qemu64";
972 cpu_model
= "qemu32";
975 current_cpu_model
= cpu_model
;
977 for (i
= 0; i
< smp_cpus
; i
++) {
978 cpu
= pc_new_cpu(cpu_model
, x86_cpu_apic_id_from_index(i
),
981 error_report("%s", error_get_pretty(error
));
987 /* map APIC MMIO area if CPU has APIC */
988 if (cpu
&& cpu
->env
.apic_state
) {
989 /* XXX: what if the base changes? */
990 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge
), 0,
991 APIC_DEFAULT_ADDRESS
, 0x1000);
995 /* pci-info ROM file. Little endian format */
996 typedef struct PcRomPciInfo
{
1003 static void pc_fw_cfg_guest_info(PcGuestInfo
*guest_info
)
1007 bool ambiguous
= false;
1009 if (!guest_info
->has_pci_info
|| !guest_info
->fw_cfg
) {
1012 pci_info
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1013 g_assert(!ambiguous
);
1018 info
= g_malloc(sizeof *info
);
1019 info
->w32_min
= cpu_to_le64(object_property_get_int(pci_info
,
1020 PCI_HOST_PROP_PCI_HOLE_START
, NULL
));
1021 info
->w32_max
= cpu_to_le64(object_property_get_int(pci_info
,
1022 PCI_HOST_PROP_PCI_HOLE_END
, NULL
));
1023 info
->w64_min
= cpu_to_le64(object_property_get_int(pci_info
,
1024 PCI_HOST_PROP_PCI_HOLE64_START
, NULL
));
1025 info
->w64_max
= cpu_to_le64(object_property_get_int(pci_info
,
1026 PCI_HOST_PROP_PCI_HOLE64_END
, NULL
));
1027 /* Pass PCI hole info to guest via a side channel.
1028 * Required so guest PCI enumeration does the right thing. */
1029 fw_cfg_add_file(guest_info
->fw_cfg
, "etc/pci-info", info
, sizeof *info
);
1032 typedef struct PcGuestInfoState
{
1034 Notifier machine_done
;
1038 void pc_guest_info_machine_done(Notifier
*notifier
, void *data
)
1040 PcGuestInfoState
*guest_info_state
= container_of(notifier
,
1043 pc_fw_cfg_guest_info(&guest_info_state
->info
);
1044 acpi_setup(&guest_info_state
->info
);
1047 PcGuestInfo
*pc_guest_info_init(ram_addr_t below_4g_mem_size
,
1048 ram_addr_t above_4g_mem_size
)
1050 PcGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1051 PcGuestInfo
*guest_info
= &guest_info_state
->info
;
1054 guest_info
->ram_size
= below_4g_mem_size
+ above_4g_mem_size
;
1055 guest_info
->apic_id_limit
= pc_apic_id_limit(max_cpus
);
1056 guest_info
->apic_xrupt_override
= kvm_allows_irq0_override();
1057 guest_info
->numa_nodes
= nb_numa_nodes
;
1058 guest_info
->node_mem
= g_memdup(node_mem
, guest_info
->numa_nodes
*
1059 sizeof *guest_info
->node_mem
);
1060 guest_info
->node_cpu
= g_malloc0(guest_info
->apic_id_limit
*
1061 sizeof *guest_info
->node_cpu
);
1063 for (i
= 0; i
< max_cpus
; i
++) {
1064 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
1065 assert(apic_id
< guest_info
->apic_id_limit
);
1066 for (j
= 0; j
< nb_numa_nodes
; j
++) {
1067 if (test_bit(i
, node_cpumask
[j
])) {
1068 guest_info
->node_cpu
[apic_id
] = j
;
1074 guest_info_state
->machine_done
.notify
= pc_guest_info_machine_done
;
1075 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1079 void pc_init_pci64_hole(PcPciInfo
*pci_info
, uint64_t pci_hole64_start
,
1080 uint64_t pci_hole64_size
)
1082 if ((sizeof(hwaddr
) == 4) || (!pci_hole64_size
)) {
1086 * BIOS does not set MTRR entries for the 64 bit window, so no need to
1087 * align address to power of two. Align address at 1G, this makes sure
1088 * it can be exactly covered with a PAT entry even when using huge
1091 pci_info
->w64
.begin
= ROUND_UP(pci_hole64_start
, 0x1ULL
<< 30);
1092 pci_info
->w64
.end
= pci_info
->w64
.begin
+ pci_hole64_size
;
1093 assert(pci_info
->w64
.begin
<= pci_info
->w64
.end
);
1096 void pc_acpi_init(const char *default_dsdt
)
1100 if (acpi_tables
!= NULL
) {
1101 /* manually set via -acpitable, leave it alone */
1105 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1106 if (filename
== NULL
) {
1107 fprintf(stderr
, "WARNING: failed to find %s\n", default_dsdt
);
1113 arg
= g_strdup_printf("file=%s", filename
);
1115 /* creates a deep copy of "arg" */
1116 opts
= qemu_opts_parse(qemu_find_opts("acpi"), arg
, 0);
1117 g_assert(opts
!= NULL
);
1119 acpi_table_add_builtin(opts
, &err
);
1121 error_report("WARNING: failed to load %s: %s", filename
,
1122 error_get_pretty(err
));
1130 FWCfgState
*pc_memory_init(MemoryRegion
*system_memory
,
1131 const char *kernel_filename
,
1132 const char *kernel_cmdline
,
1133 const char *initrd_filename
,
1134 ram_addr_t below_4g_mem_size
,
1135 ram_addr_t above_4g_mem_size
,
1136 MemoryRegion
*rom_memory
,
1137 MemoryRegion
**ram_memory
,
1138 PcGuestInfo
*guest_info
)
1141 MemoryRegion
*ram
, *option_rom_mr
;
1142 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1145 linux_boot
= (kernel_filename
!= NULL
);
1147 /* Allocate RAM. We allocate it as a single memory region and use
1148 * aliases to address portions of it, mostly for backwards compatibility
1149 * with older qemus that used qemu_ram_alloc().
1151 ram
= g_malloc(sizeof(*ram
));
1152 memory_region_init_ram(ram
, NULL
, "pc.ram",
1153 below_4g_mem_size
+ above_4g_mem_size
);
1154 vmstate_register_ram_global(ram
);
1156 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1157 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1158 0, below_4g_mem_size
);
1159 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1162 * Ideally we should do that too, but that would ruin the e820
1163 * reservations added by seabios before initializing fw_cfg.
1165 e820_add_entry(0, below_4g_mem_size
, E820_RAM
);
1167 if (above_4g_mem_size
> 0) {
1168 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1169 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1170 below_4g_mem_size
, above_4g_mem_size
);
1171 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1173 e820_add_entry(0x100000000ULL
, above_4g_mem_size
, E820_RAM
);
1177 /* Initialize PC system firmware */
1178 pc_system_firmware_init(rom_memory
, guest_info
->isapc_ram_fw
);
1180 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1181 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
);
1182 vmstate_register_ram_global(option_rom_mr
);
1183 memory_region_add_subregion_overlap(rom_memory
,
1188 fw_cfg
= bochs_bios_init();
1192 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
1195 for (i
= 0; i
< nb_option_roms
; i
++) {
1196 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1198 guest_info
->fw_cfg
= fw_cfg
;
1202 qemu_irq
*pc_allocate_cpu_irq(void)
1204 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1207 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1209 DeviceState
*dev
= NULL
;
1212 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1213 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1214 } else if (isa_bus
) {
1215 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1216 dev
= isadev
? DEVICE(isadev
) : NULL
;
1221 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1223 CPUState
*cpu
= current_cpu
;
1230 static const MemoryRegionOps ioport80_io_ops
= {
1231 .write
= ioport80_write
,
1232 .read
= ioport80_read
,
1233 .endianness
= DEVICE_NATIVE_ENDIAN
,
1235 .min_access_size
= 1,
1236 .max_access_size
= 1,
1240 static const MemoryRegionOps ioportF0_io_ops
= {
1241 .write
= ioportF0_write
,
1242 .read
= ioportF0_read
,
1243 .endianness
= DEVICE_NATIVE_ENDIAN
,
1245 .min_access_size
= 1,
1246 .max_access_size
= 1,
1250 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1251 ISADevice
**rtc_state
,
1256 DriveInfo
*fd
[MAX_FD
];
1257 DeviceState
*hpet
= NULL
;
1258 int pit_isa_irq
= 0;
1259 qemu_irq pit_alt_irq
= NULL
;
1260 qemu_irq rtc_irq
= NULL
;
1262 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1263 qemu_irq
*cpu_exit_irq
;
1264 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1265 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1267 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1268 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1270 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1271 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1274 * Check if an HPET shall be created.
1276 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1277 * when the HPET wants to take over. Thus we have to disable the latter.
1279 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1280 hpet
= sysbus_try_create_simple("hpet", HPET_BASE
, NULL
);
1283 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1284 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1287 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1288 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1291 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1293 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1295 if (!xen_enabled()) {
1296 if (kvm_irqchip_in_kernel()) {
1297 pit
= kvm_pit_init(isa_bus
, 0x40);
1299 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1302 /* connect PIT to output control line of the HPET */
1303 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1305 pcspk_init(isa_bus
, pit
);
1308 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1309 if (serial_hds
[i
]) {
1310 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1314 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1315 if (parallel_hds
[i
]) {
1316 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1320 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1321 i8042
= isa_create_simple(isa_bus
, "i8042");
1322 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1324 vmport_init(isa_bus
);
1325 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1330 DeviceState
*dev
= DEVICE(vmmouse
);
1331 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1332 qdev_init_nofail(dev
);
1334 port92
= isa_create_simple(isa_bus
, "port92");
1335 port92_init(port92
, &a20_line
[1]);
1337 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1338 DMA_init(0, cpu_exit_irq
);
1340 for(i
= 0; i
< MAX_FD
; i
++) {
1341 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1343 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1346 void pc_nic_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1350 for (i
= 0; i
< nb_nics
; i
++) {
1351 NICInfo
*nd
= &nd_table
[i
];
1353 if (!pci_bus
|| (nd
->model
&& strcmp(nd
->model
, "ne2k_isa") == 0)) {
1354 pc_init_ne2k_isa(isa_bus
, nd
);
1356 pci_nic_init_nofail(nd
, pci_bus
, "e1000", NULL
);
1361 void pc_pci_device_init(PCIBus
*pci_bus
)
1366 max_bus
= drive_get_max_bus(IF_SCSI
);
1367 for (bus
= 0; bus
<= max_bus
; bus
++) {
1368 pci_create_simple(pci_bus
, -1, "lsi53c895a");
1372 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1378 if (kvm_irqchip_in_kernel()) {
1379 dev
= qdev_create(NULL
, "kvm-ioapic");
1381 dev
= qdev_create(NULL
, "ioapic");
1384 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1385 "ioapic", OBJECT(dev
), NULL
);
1387 qdev_init_nofail(dev
);
1388 d
= SYS_BUS_DEVICE(dev
);
1389 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1391 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1392 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);