2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
46 #include "hw/cpu/icc_bus.h"
48 /* ICH9 AHCI has 6 ports */
49 #define MAX_SATA_PORTS 6
51 static bool has_pci_info
;
52 static bool has_acpi_build
= true;
53 static bool smbios_type1_defaults
= true;
54 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
55 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
58 static bool gigabyte_align
= true;
60 /* PC hardware initialisation */
61 static void pc_q35_init(QEMUMachineInitArgs
*args
)
63 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
68 BusState
*idebus
[MAX_SATA_PORTS
];
71 MemoryRegion
*pci_memory
;
72 MemoryRegion
*rom_memory
;
73 MemoryRegion
*ram_memory
;
81 ICH9LPCState
*ich9_lpc
;
83 DeviceState
*icc_bridge
;
84 PcGuestInfo
*guest_info
;
86 if (xen_enabled() && xen_hvm_init(&ram_memory
) != 0) {
87 fprintf(stderr
, "xen hardware virtual machine initialisation failed\n");
91 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
92 object_property_add_child(qdev_get_machine(), "icc-bridge",
93 OBJECT(icc_bridge
), NULL
);
95 pc_cpus_init(args
->cpu_model
, icc_bridge
);
96 pc_acpi_init("q35-acpi-dsdt.aml");
100 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
101 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
102 * also known as MMCFG).
103 * If it doesn't, we need to split it in chunks below and above 4G.
104 * In any case, try to make sure that guest addresses aligned at
105 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
106 * For old machine types, use whatever split we used historically to avoid
107 * breaking migration.
109 if (args
->ram_size
>= 0xb0000000) {
110 ram_addr_t lowmem
= gigabyte_align
? 0x80000000 : 0xb0000000;
111 above_4g_mem_size
= args
->ram_size
- lowmem
;
112 below_4g_mem_size
= lowmem
;
114 above_4g_mem_size
= 0;
115 below_4g_mem_size
= args
->ram_size
;
120 pci_memory
= g_new(MemoryRegion
, 1);
121 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
122 rom_memory
= pci_memory
;
125 rom_memory
= get_system_memory();
128 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
129 guest_info
->has_pci_info
= has_pci_info
;
130 guest_info
->isapc_ram_fw
= false;
131 guest_info
->has_acpi_build
= has_acpi_build
;
133 if (smbios_type1_defaults
) {
134 /* These values are guest ABI, do not change */
135 smbios_set_type1_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
136 args
->machine
->name
);
139 /* allocate ram and load rom/bios */
140 if (!xen_enabled()) {
141 pc_memory_init(get_system_memory(),
142 args
->kernel_filename
, args
->kernel_cmdline
,
143 args
->initrd_filename
,
144 below_4g_mem_size
, above_4g_mem_size
,
145 rom_memory
, &ram_memory
, guest_info
);
149 gsi_state
= g_malloc0(sizeof(*gsi_state
));
150 if (kvm_irqchip_in_kernel()) {
151 kvm_pc_setup_irq_routing(pci_enabled
);
152 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
155 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
158 /* create pci host bus */
159 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
161 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
162 q35_host
->mch
.ram_memory
= ram_memory
;
163 q35_host
->mch
.pci_address_space
= pci_memory
;
164 q35_host
->mch
.system_memory
= get_system_memory();
165 q35_host
->mch
.address_space_io
= get_system_io();
166 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
167 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
168 q35_host
->mch
.guest_info
= guest_info
;
170 qdev_init_nofail(DEVICE(q35_host
));
171 phb
= PCI_HOST_BRIDGE(q35_host
);
174 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
175 ICH9_LPC_FUNC
), true,
176 TYPE_ICH9_LPC_DEVICE
);
177 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
179 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
180 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
182 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
183 isa_bus
= ich9_lpc
->isa_bus
;
186 isa_bus_irqs(isa_bus
, gsi
);
188 if (kvm_irqchip_in_kernel()) {
189 i8259
= kvm_i8259_init(isa_bus
);
190 } else if (xen_enabled()) {
191 i8259
= xen_interrupt_controller_init();
193 cpu_irq
= pc_allocate_cpu_irq();
194 i8259
= i8259_init(isa_bus
, cpu_irq
[0]);
197 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
198 gsi_state
->i8259_irq
[i
] = i8259
[i
];
201 ioapic_init_gsi(gsi_state
, NULL
);
203 qdev_init_nofail(icc_bridge
);
205 pc_register_ferr_irq(gsi
[13]);
207 /* init basic PC hardware */
208 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, &floppy
, false, 0xff0104);
210 /* connect pm stuff to lpc */
211 ich9_lpc_pm_init(lpc
);
213 /* ahci and SATA device, for q35 1 ahci controller is built-in */
214 ahci
= pci_create_simple_multifunction(host_bus
,
215 PCI_DEVFN(ICH9_SATA1_DEV
,
218 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
219 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
221 if (usb_enabled(false)) {
222 /* Should we create 6 UHCI according to ich9 spec? */
223 ehci_create_ich9_with_companions(host_bus
, 0x1d);
226 /* TODO: Populate SPD eeprom data. */
227 smbus_eeprom_init(ich9_smb_init(host_bus
,
228 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
232 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, args
->boot_order
,
233 floppy
, idebus
[0], idebus
[1], rtc_state
);
235 /* the rest devices to which pci devfn is automatically assigned */
236 pc_vga_init(isa_bus
, host_bus
);
237 pc_nic_init(isa_bus
, host_bus
);
239 pc_pci_device_init(host_bus
);
243 static void pc_compat_1_7(QEMUMachineInitArgs
*args
)
245 smbios_type1_defaults
= false;
246 gigabyte_align
= false;
247 option_rom_has_mr
= true;
250 static void pc_compat_1_6(QEMUMachineInitArgs
*args
)
253 has_pci_info
= false;
254 rom_file_has_mr
= false;
255 has_acpi_build
= false;
258 static void pc_compat_1_5(QEMUMachineInitArgs
*args
)
263 static void pc_compat_1_4(QEMUMachineInitArgs
*args
)
266 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
267 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX
, 0, CPUID_EXT_PCLMULQDQ
);
270 static void pc_q35_init_1_7(QEMUMachineInitArgs
*args
)
276 static void pc_q35_init_1_6(QEMUMachineInitArgs
*args
)
282 static void pc_q35_init_1_5(QEMUMachineInitArgs
*args
)
288 static void pc_q35_init_1_4(QEMUMachineInitArgs
*args
)
294 #define PC_Q35_MACHINE_OPTIONS \
295 PC_DEFAULT_MACHINE_OPTIONS, \
296 .desc = "Standard PC (Q35 + ICH9, 2009)", \
297 .hot_add_cpu = pc_hot_add_cpu
299 #define PC_Q35_2_0_MACHINE_OPTIONS \
300 PC_Q35_MACHINE_OPTIONS, \
301 .default_machine_opts = "firmware=bios-256k.bin"
303 static QEMUMachine pc_q35_machine_v2_0
= {
304 PC_Q35_2_0_MACHINE_OPTIONS
,
305 .name
= "pc-q35-2.0",
310 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
312 static QEMUMachine pc_q35_machine_v1_7
= {
313 PC_Q35_1_7_MACHINE_OPTIONS
,
314 .name
= "pc-q35-1.7",
315 .init
= pc_q35_init_1_7
,
316 .compat_props
= (GlobalProperty
[]) {
318 { /* end of list */ }
322 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
324 static QEMUMachine pc_q35_machine_v1_6
= {
325 PC_Q35_1_6_MACHINE_OPTIONS
,
326 .name
= "pc-q35-1.6",
327 .init
= pc_q35_init_1_6
,
328 .compat_props
= (GlobalProperty
[]) {
330 { /* end of list */ }
334 static QEMUMachine pc_q35_machine_v1_5
= {
335 PC_Q35_1_6_MACHINE_OPTIONS
,
336 .name
= "pc-q35-1.5",
337 .init
= pc_q35_init_1_5
,
338 .compat_props
= (GlobalProperty
[]) {
340 { /* end of list */ }
344 #define PC_Q35_1_4_MACHINE_OPTIONS \
345 PC_Q35_1_6_MACHINE_OPTIONS, \
348 static QEMUMachine pc_q35_machine_v1_4
= {
349 PC_Q35_1_4_MACHINE_OPTIONS
,
350 .name
= "pc-q35-1.4",
351 .init
= pc_q35_init_1_4
,
352 .compat_props
= (GlobalProperty
[]) {
354 { /* end of list */ }
358 static void pc_q35_machine_init(void)
360 qemu_register_machine(&pc_q35_machine_v2_0
);
361 qemu_register_machine(&pc_q35_machine_v1_7
);
362 qemu_register_machine(&pc_q35_machine_v1_6
);
363 qemu_register_machine(&pc_q35_machine_v1_5
);
364 qemu_register_machine(&pc_q35_machine_v1_4
);
367 machine_init(pc_q35_machine_init
);