hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "hw/hw.h"
  33 #include "hw/loader.h"
  34 #include "sysemu/arch_init.h"
  35 #include "hw/i2c/smbus.h"
  36 #include "hw/boards.h"
  37 #include "hw/timer/mc146818rtc.h"
  38 #include "hw/xen/xen.h"
  39 #include "sysemu/kvm.h"
  40 #include "kvm_i386.h"
  41 #include "hw/kvm/clock.h"
  42 #include "hw/pci-host/q35.h"
  43 #include "exec/address-spaces.h"
  44 #include "hw/i386/pc.h"
  45 #include "hw/i386/ich9.h"
  46 #include "hw/i386/amd_iommu.h"
  47 #include "hw/i386/intel_iommu.h"
  48 #include "hw/smbios/smbios.h"
  49 #include "hw/ide/pci.h"
  50 #include "hw/ide/ahci.h"
  51 #include "hw/usb.h"
  52 #include "qapi/error.h"
  53 #include "qemu/error-report.h"
  54 #include "sysemu/numa.h"
  55
  56 /* ICH9 AHCI has 6 ports */
  57 #define MAX_SATA_PORTS     6
  58
  59 /* PC hardware initialisation */
  60 static void pc_q35_init(MachineState *machine)
  61 {
  62     PCMachineState *pcms = PC_MACHINE(machine);
  63     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  64     Q35PCIHost *q35_host;
  65     PCIHostState *phb;
  66     PCIBus *host_bus;
  67     PCIDevice *lpc;
  68     DeviceState *lpc_dev;
  69     BusState *idebus[MAX_SATA_PORTS];
  70     ISADevice *rtc_state;
  71     MemoryRegion *system_io = get_system_io();
  72     MemoryRegion *pci_memory;
  73     MemoryRegion *rom_memory;
  74     MemoryRegion *ram_memory;
  75     GSIState *gsi_state;
  76     ISABus *isa_bus;
  77     qemu_irq *i8259;
  78     int i;
  79     ICH9LPCState *ich9_lpc;
  80     PCIDevice *ahci;
  81     ram_addr_t lowmem;
  82     DriveInfo *hd[MAX_SATA_PORTS];
  83     MachineClass *mc = MACHINE_GET_CLASS(machine);
  84
  85     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  86      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  87      * also known as MMCFG).
  88      * If it doesn't, we need to split it in chunks below and above 4G.
  89      * In any case, try to make sure that guest addresses aligned at
  90      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  91      */
  92     if (machine->ram_size >= 0xb0000000) {
  93         lowmem = 0x80000000;
  94     } else {
  95         lowmem = 0xb0000000;
  96     }
  97
  98     /* Handle the machine opt max-ram-below-4g.  It is basically doing
  99      * min(qemu limit, user limit).
 100      */
 101     if (!pcms->max_ram_below_4g) {
 102         pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
 103     }
 104     if (lowmem > pcms->max_ram_below_4g) {
 105         lowmem = pcms->max_ram_below_4g;
 106         if (machine->ram_size - lowmem > lowmem &&
 107             lowmem & ((1ULL << 30) - 1)) {
 108             warn_report("There is possibly poor performance as the ram size "
 109                         " (0x%" PRIx64 ") is more then twice the size of"
 110                         " max-ram-below-4g (%"PRIu64") and"
 111                         " max-ram-below-4g is not a multiple of 1G.",
 112                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 113         }
 114     }
 115
 116     if (machine->ram_size >= lowmem) {
 117         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 118         pcms->below_4g_mem_size = lowmem;
 119     } else {
 120         pcms->above_4g_mem_size = 0;
 121         pcms->below_4g_mem_size = machine->ram_size;
 122     }
 123
 124     if (xen_enabled()) {
 125         xen_hvm_init(pcms, &ram_memory);
 126     }
 127
 128     pc_cpus_init(pcms);
 129
 130     kvmclock_create();
 131
 132     /* pci enabled */
 133     if (pcmc->pci_enabled) {
 134         pci_memory = g_new(MemoryRegion, 1);
 135         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 136         rom_memory = pci_memory;
 137     } else {
 138         pci_memory = NULL;
 139         rom_memory = get_system_memory();
 140     }
 141
 142     pc_guest_info_init(pcms);
 143
 144     if (pcmc->smbios_defaults) {
 145         /* These values are guest ABI, do not change */
 146         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 147                             mc->name, pcmc->smbios_legacy_mode,
 148                             pcmc->smbios_uuid_encoded,
 149                             SMBIOS_ENTRY_POINT_21);
 150     }
 151
 152     /* allocate ram and load rom/bios */
 153     if (!xen_enabled()) {
 154         pc_memory_init(pcms, get_system_memory(),
 155                        rom_memory, &ram_memory);
 156     }
 157
 158     /* irq lines */
 159     gsi_state = g_malloc0(sizeof(*gsi_state));
 160     if (kvm_ioapic_in_kernel()) {
 161         kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 162         pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 163                                        GSI_NUM_PINS);
 164     } else {
 165         pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 166     }
 167
 168     /* create pci host bus */
 169     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 170
 171     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 172     object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 173                              MCH_HOST_PROP_RAM_MEM, NULL);
 174     object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 175                              MCH_HOST_PROP_PCI_MEM, NULL);
 176     object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 177                              MCH_HOST_PROP_SYSTEM_MEM, NULL);
 178     object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 179                              MCH_HOST_PROP_IO_MEM, NULL);
 180     object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
 181                             PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 182     object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
 183                             PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 184     /* pci */
 185     qdev_init_nofail(DEVICE(q35_host));
 186     phb = PCI_HOST_BRIDGE(q35_host);
 187     host_bus = phb->bus;
 188     /* create ISA bus */
 189     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 190                                           ICH9_LPC_FUNC), true,
 191                                           TYPE_ICH9_LPC_DEVICE);
 192
 193     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 194                              TYPE_HOTPLUG_HANDLER,
 195                              (Object **)&pcms->acpi_dev,
 196                              object_property_allow_set_link,
 197                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 198     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 199                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 200
 201     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 202     lpc_dev = DEVICE(lpc);
 203     for (i = 0; i < GSI_NUM_PINS; i++) {
 204         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
 205     }
 206     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 207                  ICH9_LPC_NB_PIRQS);
 208     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 209     isa_bus = ich9_lpc->isa_bus;
 210
 211     if (kvm_pic_in_kernel()) {
 212         i8259 = kvm_i8259_init(isa_bus);
 213     } else if (xen_enabled()) {
 214         i8259 = xen_interrupt_controller_init();
 215     } else {
 216         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 217     }
 218
 219     for (i = 0; i < ISA_NUM_IRQS; i++) {
 220         gsi_state->i8259_irq[i] = i8259[i];
 221     }
 222     g_free(i8259);
 223
 224     if (pcmc->pci_enabled) {
 225         ioapic_init_gsi(gsi_state, "q35");
 226     }
 227
 228     pc_register_ferr_irq(pcms->gsi[13]);
 229
 230     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 231     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 232         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 233     }
 234
 235     /* init basic PC hardware */
 236     pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
 237                          (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit,
 238                          0xff0104);
 239
 240     /* connect pm stuff to lpc */
 241     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 242
 243     if (pcms->sata) {
 244         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 245         ahci = pci_create_simple_multifunction(host_bus,
 246                                                PCI_DEVFN(ICH9_SATA1_DEV,
 247                                                          ICH9_SATA1_FUNC),
 248                                                true, "ich9-ahci");
 249         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 250         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 251         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 252         ide_drive_get(hd, ahci_get_num_ports(ahci));
 253         ahci_ide_create_devs(ahci, hd);
 254     } else {
 255         idebus[0] = idebus[1] = NULL;
 256     }
 257
 258     if (machine_usb(machine)) {
 259         /* Should we create 6 UHCI according to ich9 spec? */
 260         ehci_create_ich9_with_companions(host_bus, 0x1d);
 261     }
 262
 263     if (pcms->smbus) {
 264         /* TODO: Populate SPD eeprom data.  */
 265         smbus_eeprom_init(ich9_smb_init(host_bus,
 266                                         PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 267                                         0xb100),
 268                           8, NULL, 0);
 269     }
 270
 271     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 272
 273     /* the rest devices to which pci devfn is automatically assigned */
 274     pc_vga_init(isa_bus, host_bus);
 275     pc_nic_init(pcmc, isa_bus, host_bus);
 276
 277     if (pcms->acpi_nvdimm_state.is_enabled) {
 278         nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 279                                pcms->fw_cfg, OBJECT(pcms));
 280     }
 281 }
 282
 283 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 284     static void pc_init_##suffix(MachineState *machine) \
 285     { \
 286         void (*compat)(MachineState *m) = (compatfn); \
 287         if (compat) { \
 288             compat(machine); \
 289         } \
 290         pc_q35_init(machine); \
 291     } \
 292     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 293
 294
 295 static void pc_q35_machine_options(MachineClass *m)
 296 {
 297     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 298     pcmc->default_nic_model = "e1000e";
 299
 300     m->family = "pc_q35";
 301     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 302     m->units_per_default_bus = 1;
 303     m->default_machine_opts = "firmware=bios-256k.bin";
 304     m->default_display = "std";
 305     m->no_floppy = 1;
 306     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 307     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 308     m->max_cpus = 288;
 309 }
 310
 311 static void pc_q35_2_12_machine_options(MachineClass *m)
 312 {
 313     pc_q35_machine_options(m);
 314     m->alias = "q35";
 315 }
 316
 317 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 318                    pc_q35_2_12_machine_options);
 319
 320 static void pc_q35_2_11_machine_options(MachineClass *m)
 321 {
 322     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 323
 324     pc_q35_2_12_machine_options(m);
 325     pcmc->default_nic_model = "e1000";
 326     m->alias = NULL;
 327     SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);
 328 }
 329
 330 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 331                    pc_q35_2_11_machine_options);
 332
 333 static void pc_q35_2_10_machine_options(MachineClass *m)
 334 {
 335     pc_q35_2_11_machine_options(m);
 336     SET_MACHINE_COMPAT(m, PC_COMPAT_2_10);
 337     m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 338     m->auto_enable_numa_with_memhp = false;
 339 }
 340
 341 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 342                    pc_q35_2_10_machine_options);
 343
 344 static void pc_q35_2_9_machine_options(MachineClass *m)
 345 {
 346     pc_q35_2_10_machine_options(m);
 347     SET_MACHINE_COMPAT(m, PC_COMPAT_2_9);
 348 }
 349
 350 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 351                    pc_q35_2_9_machine_options);
 352
 353 static void pc_q35_2_8_machine_options(MachineClass *m)
 354 {
 355     pc_q35_2_9_machine_options(m);
 356     SET_MACHINE_COMPAT(m, PC_COMPAT_2_8);
 357 }
 358
 359 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 360                    pc_q35_2_8_machine_options);
 361
 362 static void pc_q35_2_7_machine_options(MachineClass *m)
 363 {
 364     pc_q35_2_8_machine_options(m);
 365     m->max_cpus = 255;
 366     SET_MACHINE_COMPAT(m, PC_COMPAT_2_7);
 367 }
 368
 369 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 370                    pc_q35_2_7_machine_options);
 371
 372 static void pc_q35_2_6_machine_options(MachineClass *m)
 373 {
 374     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 375     pc_q35_2_7_machine_options(m);
 376     pcmc->legacy_cpu_hotplug = true;
 377     pcmc->linuxboot_dma_enabled = false;
 378     SET_MACHINE_COMPAT(m, PC_COMPAT_2_6);
 379 }
 380
 381 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 382                    pc_q35_2_6_machine_options);
 383
 384 static void pc_q35_2_5_machine_options(MachineClass *m)
 385 {
 386     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 387     pc_q35_2_6_machine_options(m);
 388     pcmc->save_tsc_khz = false;
 389     m->legacy_fw_cfg_order = 1;
 390     SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 391 }
 392
 393 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 394                    pc_q35_2_5_machine_options);
 395
 396 static void pc_q35_2_4_machine_options(MachineClass *m)
 397 {
 398     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 399     pc_q35_2_5_machine_options(m);
 400     m->hw_version = "2.4.0";
 401     pcmc->broken_reserved_end = true;
 402     SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 403 }
 404
 405 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 406                    pc_q35_2_4_machine_options);