hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/loader.h"
  32 #include "sysemu/arch_init.h"
  33 #include "hw/i2c/smbus.h"
  34 #include "hw/boards.h"
  35 #include "hw/timer/mc146818rtc.h"
  36 #include "hw/xen/xen.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "exec/address-spaces.h"
  41 #include "hw/i386/ich9.h"
  42 #include "hw/i386/smbios.h"
  43 #include "hw/ide/pci.h"
  44 #include "hw/ide/ahci.h"
  45 #include "hw/usb.h"
  46 #include "hw/cpu/icc_bus.h"
  47
  48 /* ICH9 AHCI has 6 ports */
  49 #define MAX_SATA_PORTS     6
  50
  51 static bool has_pci_info;
  52 static bool has_acpi_build = true;
  53 static bool smbios_defaults = true;
  54 static bool smbios_legacy_mode;
  55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
  56  * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
  57  * pages in the host.
  58  */
  59 static bool gigabyte_align = true;
  60
  61 /* PC hardware initialisation */
  62 static void pc_q35_init(QEMUMachineInitArgs *args)
  63 {
  64     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  65     Q35PCIHost *q35_host;
  66     PCIHostState *phb;
  67     PCIBus *host_bus;
  68     PCIDevice *lpc;
  69     BusState *idebus[MAX_SATA_PORTS];
  70     ISADevice *rtc_state;
  71     ISADevice *floppy;
  72     MemoryRegion *pci_memory;
  73     MemoryRegion *rom_memory;
  74     MemoryRegion *ram_memory;
  75     GSIState *gsi_state;
  76     ISABus *isa_bus;
  77     int pci_enabled = 1;
  78     qemu_irq *cpu_irq;
  79     qemu_irq *gsi;
  80     qemu_irq *i8259;
  81     int i;
  82     ICH9LPCState *ich9_lpc;
  83     PCIDevice *ahci;
  84     DeviceState *icc_bridge;
  85     PcGuestInfo *guest_info;
  86
  87     if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
  88         fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
  89         exit(1);
  90     }
  91
  92     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
  93     object_property_add_child(qdev_get_machine(), "icc-bridge",
  94                               OBJECT(icc_bridge), NULL);
  95
  96     pc_cpus_init(args->cpu_model, icc_bridge);
  97     pc_acpi_init("q35-acpi-dsdt.aml");
  98
  99     kvmclock_create();
 100
 101     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 102      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 103      * also known as MMCFG).
 104      * If it doesn't, we need to split it in chunks below and above 4G.
 105      * In any case, try to make sure that guest addresses aligned at
 106      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 107      * For old machine types, use whatever split we used historically to avoid
 108      * breaking migration.
 109      */
 110     if (args->ram_size >= 0xb0000000) {
 111         ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
 112         above_4g_mem_size = args->ram_size - lowmem;
 113         below_4g_mem_size = lowmem;
 114     } else {
 115         above_4g_mem_size = 0;
 116         below_4g_mem_size = args->ram_size;
 117     }
 118
 119     /* pci enabled */
 120     if (pci_enabled) {
 121         pci_memory = g_new(MemoryRegion, 1);
 122         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 123         rom_memory = pci_memory;
 124     } else {
 125         pci_memory = NULL;
 126         rom_memory = get_system_memory();
 127     }
 128
 129     guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
 130     guest_info->has_pci_info = has_pci_info;
 131     guest_info->isapc_ram_fw = false;
 132     guest_info->has_acpi_build = has_acpi_build;
 133
 134     if (smbios_defaults) {
 135         /* These values are guest ABI, do not change */
 136         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 137                             args->machine->name, smbios_legacy_mode);
 138     }
 139
 140     /* allocate ram and load rom/bios */
 141     if (!xen_enabled()) {
 142         pc_memory_init(get_system_memory(),
 143                        args->kernel_filename, args->kernel_cmdline,
 144                        args->initrd_filename,
 145                        below_4g_mem_size, above_4g_mem_size,
 146                        rom_memory, &ram_memory, guest_info);
 147     }
 148
 149     /* irq lines */
 150     gsi_state = g_malloc0(sizeof(*gsi_state));
 151     if (kvm_irqchip_in_kernel()) {
 152         kvm_pc_setup_irq_routing(pci_enabled);
 153         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 154                                  GSI_NUM_PINS);
 155     } else {
 156         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 157     }
 158
 159     /* create pci host bus */
 160     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 161
 162     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 163     q35_host->mch.ram_memory = ram_memory;
 164     q35_host->mch.pci_address_space = pci_memory;
 165     q35_host->mch.system_memory = get_system_memory();
 166     q35_host->mch.address_space_io = get_system_io();
 167     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
 168     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
 169     q35_host->mch.guest_info = guest_info;
 170     /* pci */
 171     qdev_init_nofail(DEVICE(q35_host));
 172     phb = PCI_HOST_BRIDGE(q35_host);
 173     host_bus = phb->bus;
 174     /* create ISA bus */
 175     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 176                                           ICH9_LPC_FUNC), true,
 177                                           TYPE_ICH9_LPC_DEVICE);
 178     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 179     ich9_lpc->pic = gsi;
 180     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 181     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 182                  ICH9_LPC_NB_PIRQS);
 183     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 184     isa_bus = ich9_lpc->isa_bus;
 185
 186     /*end early*/
 187     isa_bus_irqs(isa_bus, gsi);
 188
 189     if (kvm_irqchip_in_kernel()) {
 190         i8259 = kvm_i8259_init(isa_bus);
 191     } else if (xen_enabled()) {
 192         i8259 = xen_interrupt_controller_init();
 193     } else {
 194         cpu_irq = pc_allocate_cpu_irq();
 195         i8259 = i8259_init(isa_bus, cpu_irq[0]);
 196     }
 197
 198     for (i = 0; i < ISA_NUM_IRQS; i++) {
 199         gsi_state->i8259_irq[i] = i8259[i];
 200     }
 201     if (pci_enabled) {
 202         ioapic_init_gsi(gsi_state, NULL);
 203     }
 204     qdev_init_nofail(icc_bridge);
 205
 206     pc_register_ferr_irq(gsi[13]);
 207
 208     /* init basic PC hardware */
 209     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);
 210
 211     /* connect pm stuff to lpc */
 212     ich9_lpc_pm_init(lpc);
 213
 214     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 215     ahci = pci_create_simple_multifunction(host_bus,
 216                                            PCI_DEVFN(ICH9_SATA1_DEV,
 217                                                      ICH9_SATA1_FUNC),
 218                                            true, "ich9-ahci");
 219     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 220     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 221
 222     if (usb_enabled(false)) {
 223         /* Should we create 6 UHCI according to ich9 spec? */
 224         ehci_create_ich9_with_companions(host_bus, 0x1d);
 225     }
 226
 227     /* TODO: Populate SPD eeprom data.  */
 228     smbus_eeprom_init(ich9_smb_init(host_bus,
 229                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 230                                     0xb100),
 231                       8, NULL, 0);
 232
 233     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order,
 234                  floppy, idebus[0], idebus[1], rtc_state);
 235
 236     /* the rest devices to which pci devfn is automatically assigned */
 237     pc_vga_init(isa_bus, host_bus);
 238     pc_nic_init(isa_bus, host_bus);
 239     if (pci_enabled) {
 240         pc_pci_device_init(host_bus);
 241     }
 242 }
 243
 244 static void pc_compat_2_0(QEMUMachineInitArgs *args)
 245 {
 246     smbios_legacy_mode = true;
 247 }
 248
 249 static void pc_compat_1_7(QEMUMachineInitArgs *args)
 250 {
 251     pc_compat_2_0(args);
 252     smbios_defaults = false;
 253     gigabyte_align = false;
 254     option_rom_has_mr = true;
 255     x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC);
 256 }
 257
 258 static void pc_compat_1_6(QEMUMachineInitArgs *args)
 259 {
 260     pc_compat_1_7(args);
 261     has_pci_info = false;
 262     rom_file_has_mr = false;
 263     has_acpi_build = false;
 264 }
 265
 266 static void pc_compat_1_5(QEMUMachineInitArgs *args)
 267 {
 268     pc_compat_1_6(args);
 269 }
 270
 271 static void pc_compat_1_4(QEMUMachineInitArgs *args)
 272 {
 273     pc_compat_1_5(args);
 274     x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
 275     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
 276 }
 277
 278 static void pc_q35_init_2_0(QEMUMachineInitArgs *args)
 279 {
 280     pc_compat_2_0(args);
 281     pc_q35_init(args);
 282 }
 283
 284 static void pc_q35_init_1_7(QEMUMachineInitArgs *args)
 285 {
 286     pc_compat_1_7(args);
 287     pc_q35_init(args);
 288 }
 289
 290 static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
 291 {
 292     pc_compat_1_6(args);
 293     pc_q35_init(args);
 294 }
 295
 296 static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
 297 {
 298     pc_compat_1_5(args);
 299     pc_q35_init(args);
 300 }
 301
 302 static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
 303 {
 304     pc_compat_1_4(args);
 305     pc_q35_init(args);
 306 }
 307
 308 #define PC_Q35_MACHINE_OPTIONS \
 309     PC_DEFAULT_MACHINE_OPTIONS, \
 310     .desc = "Standard PC (Q35 + ICH9, 2009)", \
 311     .hot_add_cpu = pc_hot_add_cpu
 312
 313 #define PC_Q35_2_1_MACHINE_OPTIONS                      \
 314     PC_Q35_MACHINE_OPTIONS,                             \
 315     .default_machine_opts = "firmware=bios-256k.bin"
 316
 317 static QEMUMachine pc_q35_machine_v2_1 = {
 318     PC_Q35_2_1_MACHINE_OPTIONS,
 319     .name = "pc-q35-2.1",
 320     .alias = "q35",
 321     .init = pc_q35_init,
 322 };
 323
 324 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
 325
 326 static QEMUMachine pc_q35_machine_v2_0 = {
 327     PC_Q35_2_0_MACHINE_OPTIONS,
 328     .name = "pc-q35-2.0",
 329     .init = pc_q35_init_2_0,
 330 };
 331
 332 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
 333
 334 static QEMUMachine pc_q35_machine_v1_7 = {
 335     PC_Q35_1_7_MACHINE_OPTIONS,
 336     .name = "pc-q35-1.7",
 337     .init = pc_q35_init_1_7,
 338     .compat_props = (GlobalProperty[]) {
 339         PC_Q35_COMPAT_1_7,
 340         { /* end of list */ }
 341     },
 342 };
 343
 344 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
 345
 346 static QEMUMachine pc_q35_machine_v1_6 = {
 347     PC_Q35_1_6_MACHINE_OPTIONS,
 348     .name = "pc-q35-1.6",
 349     .init = pc_q35_init_1_6,
 350     .compat_props = (GlobalProperty[]) {
 351         PC_Q35_COMPAT_1_6,
 352         { /* end of list */ }
 353     },
 354 };
 355
 356 static QEMUMachine pc_q35_machine_v1_5 = {
 357     PC_Q35_1_6_MACHINE_OPTIONS,
 358     .name = "pc-q35-1.5",
 359     .init = pc_q35_init_1_5,
 360     .compat_props = (GlobalProperty[]) {
 361         PC_Q35_COMPAT_1_5,
 362         { /* end of list */ }
 363     },
 364 };
 365
 366 #define PC_Q35_1_4_MACHINE_OPTIONS \
 367     PC_Q35_1_6_MACHINE_OPTIONS, \
 368     .hot_add_cpu = NULL
 369
 370 static QEMUMachine pc_q35_machine_v1_4 = {
 371     PC_Q35_1_4_MACHINE_OPTIONS,
 372     .name = "pc-q35-1.4",
 373     .init = pc_q35_init_1_4,
 374     .compat_props = (GlobalProperty[]) {
 375         PC_COMPAT_1_4,
 376         { /* end of list */ }
 377     },
 378 };
 379
 380 static void pc_q35_machine_init(void)
 381 {
 382     qemu_register_machine(&pc_q35_machine_v2_1);
 383     qemu_register_machine(&pc_q35_machine_v2_0);
 384     qemu_register_machine(&pc_q35_machine_v1_7);
 385     qemu_register_machine(&pc_q35_machine_v1_6);
 386     qemu_register_machine(&pc_q35_machine_v1_5);
 387     qemu_register_machine(&pc_q35_machine_v1_4);
 388 }
 389
 390 machine_init(pc_q35_machine_init);