hw/i386/q35-acpi-dsdt.dsl

   1 /*
   2  * Bochs/QEMU ACPI DSDT ASL definition
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19 /*
  20  * Copyright (c) 2010 Isaku Yamahata
  21  *                    yamahata at valinux co jp
  22  * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
  23  */
  24
  25 ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
  26
  27 DefinitionBlock (
  28     "q35-acpi-dsdt.aml",// Output Filename
  29     "DSDT",             // Signature
  30     0x01,               // DSDT Compliance Revision
  31     "BXPC",             // OEMID
  32     "BXDSDT",           // TABLE ID
  33     0x2                 // OEM Revision
  34     )
  35 {
  36
  37 #include "acpi-dsdt-dbug.dsl"
  38
  39     Scope(\_SB) {
  40         OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
  41         OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
  42         Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
  43             PCIB, 8,
  44         }
  45     }
  46
  47
  48 /****************************************************************
  49  * PCI Bus definition
  50  ****************************************************************/
  51     Scope(\_SB) {
  52         Device(PCI0) {
  53             Name(_HID, EisaId("PNP0A08"))
  54             Name(_CID, EisaId("PNP0A03"))
  55             Name(_ADR, 0x00)
  56             Name(_UID, 1)
  57
  58             External(ISA, DeviceObj)
  59
  60             // _OSC: based on sample of ACPI3.0b spec
  61             Name(SUPP, 0) // PCI _OSC Support Field value
  62             Name(CTRL, 0) // PCI _OSC Control Field value
  63             Method(_OSC, 4) {
  64                 // Create DWORD-addressable fields from the Capabilities Buffer
  65                 CreateDWordField(Arg3, 0, CDW1)
  66
  67                 // Check for proper UUID
  68                 If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  69                     // Create DWORD-addressable fields from the Capabilities Buffer
  70                     CreateDWordField(Arg3, 4, CDW2)
  71                     CreateDWordField(Arg3, 8, CDW3)
  72
  73                     // Save Capabilities DWORD2 & 3
  74                     Store(CDW2, SUPP)
  75                     Store(CDW3, CTRL)
  76
  77                     // Always allow native PME, AER (no dependencies)
  78                     // Never allow SHPC (no SHPC controller in this system)
  79                     And(CTRL, 0x1D, CTRL)
  80
  81 #if 0 // For now, nothing to do
  82                     If (Not(And(CDW1, 1))) { // Query flag clear?
  83                         // Disable GPEs for features granted native control.
  84                         If (And(CTRL, 0x01)) { // Hot plug control granted?
  85                             Store(0, HPCE) // clear the hot plug SCI enable bit
  86                             Store(1, HPCS) // clear the hot plug SCI status bit
  87                         }
  88                         If (And(CTRL, 0x04)) { // PME control granted?
  89                             Store(0, PMCE) // clear the PME SCI enable bit
  90                             Store(1, PMCS) // clear the PME SCI status bit
  91                         }
  92                         If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
  93                             // Set status to not restore PCI Express cap structure
  94                             // upon resume from S3
  95                             Store(1, S3CR)
  96                         }
  97                     }
  98 #endif
  99                     If (LNotEqual(Arg1, One)) {
 100                         // Unknown revision
 101                         Or(CDW1, 0x08, CDW1)
 102                     }
 103                     If (LNotEqual(CDW3, CTRL)) {
 104                         // Capabilities bits were masked
 105                         Or(CDW1, 0x10, CDW1)
 106                     }
 107                     // Update DWORD3 in the buffer
 108                     Store(CTRL, CDW3)
 109                 } Else {
 110                     Or(CDW1, 4, CDW1) // Unrecognized UUID
 111                 }
 112                 Return (Arg3)
 113             }
 114         }
 115     }
 116
 117 #include "acpi-dsdt-hpet.dsl"
 118
 119
 120 /****************************************************************
 121  * LPC ISA bridge
 122  ****************************************************************/
 123
 124     Scope(\_SB.PCI0) {
 125         /* PCI D31:f0 LPC ISA bridge */
 126         Device(ISA) {
 127             Name (_ADR, 0x001F0000)  // _ADR: Address
 128
 129             /* ICH9 PCI to ISA irq remapping */
 130             OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
 131
 132             OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
 133             Field(LPCD, AnyAcc, NoLock, Preserve) {
 134                 COMA,   3,
 135                     ,   1,
 136                 COMB,   3,
 137
 138                 Offset(0x01),
 139                 LPTD,   2,
 140                     ,   2,
 141                 FDCD,   2
 142             }
 143             OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
 144             Field(LPCE, AnyAcc, NoLock, Preserve) {
 145                 CAEN,   1,
 146                 CBEN,   1,
 147                 LPEN,   1,
 148                 FDEN,   1
 149             }
 150         }
 151     }
 152
 153 #include "acpi-dsdt-isa.dsl"
 154
 155
 156 /****************************************************************
 157  * PCI IRQs
 158  ****************************************************************/
 159
 160     /* Zero => PIC mode, One => APIC Mode */
 161     Name(\PICF, Zero)
 162     Method(\_PIC, 1, NotSerialized) {
 163         Store(Arg0, \PICF)
 164     }
 165
 166     Scope(\_SB) {
 167         Scope(PCI0) {
 168 #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
 169     Package() { nr##ffff, 0, lnk0, 0 },           \
 170     Package() { nr##ffff, 1, lnk1, 0 },           \
 171     Package() { nr##ffff, 2, lnk2, 0 },           \
 172     Package() { nr##ffff, 3, lnk3, 0 }
 173
 174 #define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
 175 #define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
 176 #define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
 177 #define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
 178
 179 #define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
 180 #define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
 181 #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
 182 #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
 183
 184             Name(PRTP, package() {
 185                 prt_slot_lnkE(0x0000),
 186                 prt_slot_lnkF(0x0001),
 187                 prt_slot_lnkG(0x0002),
 188                 prt_slot_lnkH(0x0003),
 189                 prt_slot_lnkE(0x0004),
 190                 prt_slot_lnkF(0x0005),
 191                 prt_slot_lnkG(0x0006),
 192                 prt_slot_lnkH(0x0007),
 193                 prt_slot_lnkE(0x0008),
 194                 prt_slot_lnkF(0x0009),
 195                 prt_slot_lnkG(0x000a),
 196                 prt_slot_lnkH(0x000b),
 197                 prt_slot_lnkE(0x000c),
 198                 prt_slot_lnkF(0x000d),
 199                 prt_slot_lnkG(0x000e),
 200                 prt_slot_lnkH(0x000f),
 201                 prt_slot_lnkE(0x0010),
 202                 prt_slot_lnkF(0x0011),
 203                 prt_slot_lnkG(0x0012),
 204                 prt_slot_lnkH(0x0013),
 205                 prt_slot_lnkE(0x0014),
 206                 prt_slot_lnkF(0x0015),
 207                 prt_slot_lnkG(0x0016),
 208                 prt_slot_lnkH(0x0017),
 209                 prt_slot_lnkE(0x0018),
 210
 211                 /* INTA -> PIRQA for slot 25 - 31
 212                    see the default value of D<N>IR */
 213                 prt_slot_lnkA(0x0019),
 214                 prt_slot_lnkA(0x001a),
 215                 prt_slot_lnkA(0x001b),
 216                 prt_slot_lnkA(0x001c),
 217                 prt_slot_lnkA(0x001d),
 218
 219                 /* PCIe->PCI bridge. use PIRQ[E-H] */
 220                 prt_slot_lnkE(0x001e),
 221
 222                 prt_slot_lnkA(0x001f)
 223             })
 224
 225 #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
 226     Package() { nr##ffff, 0, gsi0, 0 },           \
 227     Package() { nr##ffff, 1, gsi1, 0 },           \
 228     Package() { nr##ffff, 2, gsi2, 0 },           \
 229     Package() { nr##ffff, 3, gsi3, 0 }
 230
 231 #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
 232 #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
 233 #define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
 234 #define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
 235
 236 #define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
 237 #define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
 238 #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
 239 #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
 240
 241             Name(PRTA, package() {
 242                 prt_slot_gsiE(0x0000),
 243                 prt_slot_gsiF(0x0001),
 244                 prt_slot_gsiG(0x0002),
 245                 prt_slot_gsiH(0x0003),
 246                 prt_slot_gsiE(0x0004),
 247                 prt_slot_gsiF(0x0005),
 248                 prt_slot_gsiG(0x0006),
 249                 prt_slot_gsiH(0x0007),
 250                 prt_slot_gsiE(0x0008),
 251                 prt_slot_gsiF(0x0009),
 252                 prt_slot_gsiG(0x000a),
 253                 prt_slot_gsiH(0x000b),
 254                 prt_slot_gsiE(0x000c),
 255                 prt_slot_gsiF(0x000d),
 256                 prt_slot_gsiG(0x000e),
 257                 prt_slot_gsiH(0x000f),
 258                 prt_slot_gsiE(0x0010),
 259                 prt_slot_gsiF(0x0011),
 260                 prt_slot_gsiG(0x0012),
 261                 prt_slot_gsiH(0x0013),
 262                 prt_slot_gsiE(0x0014),
 263                 prt_slot_gsiF(0x0015),
 264                 prt_slot_gsiG(0x0016),
 265                 prt_slot_gsiH(0x0017),
 266                 prt_slot_gsiE(0x0018),
 267
 268                 /* INTA -> PIRQA for slot 25 - 31, but 30
 269                    see the default value of D<N>IR */
 270                 prt_slot_gsiA(0x0019),
 271                 prt_slot_gsiA(0x001a),
 272                 prt_slot_gsiA(0x001b),
 273                 prt_slot_gsiA(0x001c),
 274                 prt_slot_gsiA(0x001d),
 275
 276                 /* PCIe->PCI bridge. use PIRQ[E-H] */
 277                 prt_slot_gsiE(0x001e),
 278
 279                 prt_slot_gsiA(0x001f)
 280             })
 281
 282             Method(_PRT, 0, NotSerialized) {
 283                 /* PCI IRQ routing table, example from ACPI 2.0a specification,
 284                    section 6.2.8.1 */
 285                 /* Note: we provide the same info as the PCI routing
 286                    table of the Bochs BIOS */
 287                 If (LEqual(\PICF, Zero)) {
 288                     Return (PRTP)
 289                 } Else {
 290                     Return (PRTA)
 291                 }
 292             }
 293         }
 294
 295         Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
 296             PRQA,   8,
 297             PRQB,   8,
 298             PRQC,   8,
 299             PRQD,   8,
 300
 301             Offset(0x08),
 302             PRQE,   8,
 303             PRQF,   8,
 304             PRQG,   8,
 305             PRQH,   8
 306         }
 307
 308         Method(IQST, 1, NotSerialized) {
 309             // _STA method - get status
 310             If (And(0x80, Arg0)) {
 311                 Return (0x09)
 312             }
 313             Return (0x0B)
 314         }
 315         Method(IQCR, 1, Serialized) {
 316             // _CRS method - get current settings
 317             Name(PRR0, ResourceTemplate() {
 318                 Interrupt(, Level, ActiveHigh, Shared) { 0 }
 319             })
 320             CreateDWordField(PRR0, 0x05, PRRI)
 321             Store(And(Arg0, 0x0F), PRRI)
 322             Return (PRR0)
 323         }
 324
 325 #define define_link(link, uid, reg)                             \
 326         Device(link) {                                          \
 327             Name(_HID, EISAID("PNP0C0F"))                       \
 328             Name(_UID, uid)                                     \
 329             Name(_PRS, ResourceTemplate() {                     \
 330                 Interrupt(, Level, ActiveHigh, Shared) {        \
 331                     5, 10, 11                                   \
 332                 }                                               \
 333             })                                                  \
 334             Method(_STA, 0, NotSerialized) {                    \
 335                 Return (IQST(reg))                              \
 336             }                                                   \
 337             Method(_DIS, 0, NotSerialized) {                    \
 338                 Or(reg, 0x80, reg)                              \
 339             }                                                   \
 340             Method(_CRS, 0, NotSerialized) {                    \
 341                 Return (IQCR(reg))                              \
 342             }                                                   \
 343             Method(_SRS, 1, NotSerialized) {                    \
 344                 CreateDWordField(Arg0, 0x05, PRRI)              \
 345                 Store(PRRI, reg)                                \
 346             }                                                   \
 347         }
 348
 349         define_link(LNKA, 0, PRQA)
 350         define_link(LNKB, 1, PRQB)
 351         define_link(LNKC, 2, PRQC)
 352         define_link(LNKD, 3, PRQD)
 353         define_link(LNKE, 4, PRQE)
 354         define_link(LNKF, 5, PRQF)
 355         define_link(LNKG, 6, PRQG)
 356         define_link(LNKH, 7, PRQH)
 357
 358 #define define_gsi_link(link, uid, gsi)                         \
 359         Device(link) {                                          \
 360             Name(_HID, EISAID("PNP0C0F"))                       \
 361             Name(_UID, uid)                                     \
 362             Name(_PRS, ResourceTemplate() {                     \
 363                 Interrupt(, Level, ActiveHigh, Shared) {        \
 364                     gsi                                         \
 365                 }                                               \
 366             })                                                  \
 367             Name(_CRS, ResourceTemplate() {                     \
 368                 Interrupt(, Level, ActiveHigh, Shared) {        \
 369                     gsi                                         \
 370                 }                                               \
 371             })                                                  \
 372             Method(_SRS, 1, NotSerialized) {                    \
 373             }                                                   \
 374         }
 375
 376         define_gsi_link(GSIA, 0, 0x10)
 377         define_gsi_link(GSIB, 0, 0x11)
 378         define_gsi_link(GSIC, 0, 0x12)
 379         define_gsi_link(GSID, 0, 0x13)
 380         define_gsi_link(GSIE, 0, 0x14)
 381         define_gsi_link(GSIF, 0, 0x15)
 382         define_gsi_link(GSIG, 0, 0x16)
 383         define_gsi_link(GSIH, 0, 0x17)
 384     }
 385
 386 #include "hw/acpi/pc-hotplug.h"
 387 #define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
 388 #include "acpi-dsdt-cpu-hotplug.dsl"
 389 #include "acpi-dsdt-mem-hotplug.dsl"
 390
 391
 392 /****************************************************************
 393  * General purpose events
 394  ****************************************************************/
 395     Scope(\_GPE) {
 396         Name(_HID, "ACPI0006")
 397
 398         Method(_L00) {
 399         }
 400         Method(_L01) {
 401         }
 402         Method(_E02) {
 403             // CPU hotplug event
 404             \_SB.PRSC()
 405         }
 406         Method(_E03) {
 407             // Memory hotplug event
 408             \_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD()
 409         }
 410         Method(_L04) {
 411         }
 412         Method(_L05) {
 413         }
 414         Method(_L06) {
 415         }
 416         Method(_L07) {
 417         }
 418         Method(_L08) {
 419         }
 420         Method(_L09) {
 421         }
 422         Method(_L0A) {
 423         }
 424         Method(_L0B) {
 425         }
 426         Method(_L0C) {
 427         }
 428         Method(_L0D) {
 429         }
 430         Method(_L0E) {
 431         }
 432         Method(_L0F) {
 433         }
 434     }
 435 }