hw/i386/q35-acpi-dsdt.dsl

   1 /*
   2  * Bochs/QEMU ACPI DSDT ASL definition
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19 /*
  20  * Copyright (c) 2010 Isaku Yamahata
  21  *                    yamahata at valinux co jp
  22  * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
  23  */
  24
  25
  26 ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
  27
  28 DefinitionBlock (
  29     "q35-acpi-dsdt.aml",// Output Filename
  30     "DSDT",             // Signature
  31     0x01,               // DSDT Compliance Revision
  32     "BXPC",             // OEMID
  33     "BXDSDT",           // TABLE ID
  34     0x2                 // OEM Revision
  35     )
  36 {
  37
  38 #include "acpi-dsdt-dbug.dsl"
  39
  40     Scope(\_SB) {
  41         OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
  42         OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
  43         Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
  44             PCIB, 8,
  45         }
  46     }
  47
  48
  49 /****************************************************************
  50  * PCI Bus definition
  51  ****************************************************************/
  52     Scope(\_SB) {
  53         Device(PCI0) {
  54             Name(_HID, EisaId("PNP0A08"))
  55             Name(_CID, EisaId("PNP0A03"))
  56             Name(_ADR, 0x00)
  57             Name(_UID, 1)
  58
  59             External(ISA, DeviceObj)
  60
  61             // _OSC: based on sample of ACPI3.0b spec
  62             Name(SUPP, 0) // PCI _OSC Support Field value
  63             Name(CTRL, 0) // PCI _OSC Control Field value
  64             Method(_OSC, 4) {
  65                 // Create DWORD-addressable fields from the Capabilities Buffer
  66                 CreateDWordField(Arg3, 0, CDW1)
  67
  68                 // Check for proper UUID
  69                 If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  70                     // Create DWORD-addressable fields from the Capabilities Buffer
  71                     CreateDWordField(Arg3, 4, CDW2)
  72                     CreateDWordField(Arg3, 8, CDW3)
  73
  74                     // Save Capabilities DWORD2 & 3
  75                     Store(CDW2, SUPP)
  76                     Store(CDW3, CTRL)
  77
  78                     // Always allow native PME, AER (no dependencies)
  79                     // Never allow SHPC (no SHPC controller in this system)
  80                     And(CTRL, 0x1D, CTRL)
  81
  82 #if 0 // For now, nothing to do
  83                     If (Not(And(CDW1, 1))) { // Query flag clear?
  84                         // Disable GPEs for features granted native control.
  85                         If (And(CTRL, 0x01)) { // Hot plug control granted?
  86                             Store(0, HPCE) // clear the hot plug SCI enable bit
  87                             Store(1, HPCS) // clear the hot plug SCI status bit
  88                         }
  89                         If (And(CTRL, 0x04)) { // PME control granted?
  90                             Store(0, PMCE) // clear the PME SCI enable bit
  91                             Store(1, PMCS) // clear the PME SCI status bit
  92                         }
  93                         If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
  94                             // Set status to not restore PCI Express cap structure
  95                             // upon resume from S3
  96                             Store(1, S3CR)
  97                         }
  98                     }
  99 #endif
 100                     If (LNotEqual(Arg1, One)) {
 101                         // Unknown revision
 102                         Or(CDW1, 0x08, CDW1)
 103                     }
 104                     If (LNotEqual(CDW3, CTRL)) {
 105                         // Capabilities bits were masked
 106                         Or(CDW1, 0x10, CDW1)
 107                     }
 108                     // Update DWORD3 in the buffer
 109                     Store(CTRL, CDW3)
 110                 } Else {
 111                     Or(CDW1, 4, CDW1) // Unrecognized UUID
 112                 }
 113                 Return (Arg3)
 114             }
 115         }
 116     }
 117
 118 #include "acpi-dsdt-hpet.dsl"
 119
 120
 121 /****************************************************************
 122  * LPC ISA bridge
 123  ****************************************************************/
 124
 125     Scope(\_SB.PCI0) {
 126         /* PCI D31:f0 LPC ISA bridge */
 127         Device(ISA) {
 128             Name (_ADR, 0x001F0000)  // _ADR: Address
 129
 130             /* ICH9 PCI to ISA irq remapping */
 131             OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
 132
 133             OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
 134             Field(LPCD, AnyAcc, NoLock, Preserve) {
 135                 COMA,   3,
 136                     ,   1,
 137                 COMB,   3,
 138
 139                 Offset(0x01),
 140                 LPTD,   2,
 141                     ,   2,
 142                 FDCD,   2
 143             }
 144             OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
 145             Field(LPCE, AnyAcc, NoLock, Preserve) {
 146                 CAEN,   1,
 147                 CBEN,   1,
 148                 LPEN,   1,
 149                 FDEN,   1
 150             }
 151         }
 152     }
 153
 154 #include "acpi-dsdt-isa.dsl"
 155
 156
 157 /****************************************************************
 158  * PCI IRQs
 159  ****************************************************************/
 160
 161     /* Zero => PIC mode, One => APIC Mode */
 162     Name(\PICF, Zero)
 163     Method(\_PIC, 1, NotSerialized) {
 164         Store(Arg0, \PICF)
 165     }
 166
 167     Scope(\_SB) {
 168         Scope(PCI0) {
 169 #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
 170     Package() { nr##ffff, 0, lnk0, 0 },           \
 171     Package() { nr##ffff, 1, lnk1, 0 },           \
 172     Package() { nr##ffff, 2, lnk2, 0 },           \
 173     Package() { nr##ffff, 3, lnk3, 0 }
 174
 175 #define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
 176 #define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
 177 #define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
 178 #define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
 179
 180 #define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
 181 #define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
 182 #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
 183 #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
 184
 185             Name(PRTP, package() {
 186                 prt_slot_lnkE(0x0000),
 187                 prt_slot_lnkF(0x0001),
 188                 prt_slot_lnkG(0x0002),
 189                 prt_slot_lnkH(0x0003),
 190                 prt_slot_lnkE(0x0004),
 191                 prt_slot_lnkF(0x0005),
 192                 prt_slot_lnkG(0x0006),
 193                 prt_slot_lnkH(0x0007),
 194                 prt_slot_lnkE(0x0008),
 195                 prt_slot_lnkF(0x0009),
 196                 prt_slot_lnkG(0x000a),
 197                 prt_slot_lnkH(0x000b),
 198                 prt_slot_lnkE(0x000c),
 199                 prt_slot_lnkF(0x000d),
 200                 prt_slot_lnkG(0x000e),
 201                 prt_slot_lnkH(0x000f),
 202                 prt_slot_lnkE(0x0010),
 203                 prt_slot_lnkF(0x0011),
 204                 prt_slot_lnkG(0x0012),
 205                 prt_slot_lnkH(0x0013),
 206                 prt_slot_lnkE(0x0014),
 207                 prt_slot_lnkF(0x0015),
 208                 prt_slot_lnkG(0x0016),
 209                 prt_slot_lnkH(0x0017),
 210                 prt_slot_lnkE(0x0018),
 211
 212                 /* INTA -> PIRQA for slot 25 - 31
 213                    see the default value of D<N>IR */
 214                 prt_slot_lnkA(0x0019),
 215                 prt_slot_lnkA(0x001a),
 216                 prt_slot_lnkA(0x001b),
 217                 prt_slot_lnkA(0x001c),
 218                 prt_slot_lnkA(0x001d),
 219
 220                 /* PCIe->PCI bridge. use PIRQ[E-H] */
 221                 prt_slot_lnkE(0x001e),
 222
 223                 prt_slot_lnkA(0x001f)
 224             })
 225
 226 #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
 227     Package() { nr##ffff, 0, gsi0, 0 },           \
 228     Package() { nr##ffff, 1, gsi1, 0 },           \
 229     Package() { nr##ffff, 2, gsi2, 0 },           \
 230     Package() { nr##ffff, 3, gsi3, 0 }
 231
 232 #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
 233 #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
 234 #define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
 235 #define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
 236
 237 #define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
 238 #define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
 239 #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
 240 #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
 241
 242             Name(PRTA, package() {
 243                 prt_slot_gsiE(0x0000),
 244                 prt_slot_gsiF(0x0001),
 245                 prt_slot_gsiG(0x0002),
 246                 prt_slot_gsiH(0x0003),
 247                 prt_slot_gsiE(0x0004),
 248                 prt_slot_gsiF(0x0005),
 249                 prt_slot_gsiG(0x0006),
 250                 prt_slot_gsiH(0x0007),
 251                 prt_slot_gsiE(0x0008),
 252                 prt_slot_gsiF(0x0009),
 253                 prt_slot_gsiG(0x000a),
 254                 prt_slot_gsiH(0x000b),
 255                 prt_slot_gsiE(0x000c),
 256                 prt_slot_gsiF(0x000d),
 257                 prt_slot_gsiG(0x000e),
 258                 prt_slot_gsiH(0x000f),
 259                 prt_slot_gsiE(0x0010),
 260                 prt_slot_gsiF(0x0011),
 261                 prt_slot_gsiG(0x0012),
 262                 prt_slot_gsiH(0x0013),
 263                 prt_slot_gsiE(0x0014),
 264                 prt_slot_gsiF(0x0015),
 265                 prt_slot_gsiG(0x0016),
 266                 prt_slot_gsiH(0x0017),
 267                 prt_slot_gsiE(0x0018),
 268
 269                 /* INTA -> PIRQA for slot 25 - 31, but 30
 270                    see the default value of D<N>IR */
 271                 prt_slot_gsiA(0x0019),
 272                 prt_slot_gsiA(0x001a),
 273                 prt_slot_gsiA(0x001b),
 274                 prt_slot_gsiA(0x001c),
 275                 prt_slot_gsiA(0x001d),
 276
 277                 /* PCIe->PCI bridge. use PIRQ[E-H] */
 278                 prt_slot_gsiE(0x001e),
 279
 280                 prt_slot_gsiA(0x001f)
 281             })
 282
 283             Method(_PRT, 0, NotSerialized) {
 284                 /* PCI IRQ routing table, example from ACPI 2.0a specification,
 285                    section 6.2.8.1 */
 286                 /* Note: we provide the same info as the PCI routing
 287                    table of the Bochs BIOS */
 288                 If (LEqual(\PICF, Zero)) {
 289                     Return (PRTP)
 290                 } Else {
 291                     Return (PRTA)
 292                 }
 293             }
 294         }
 295
 296         Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
 297             PRQA,   8,
 298             PRQB,   8,
 299             PRQC,   8,
 300             PRQD,   8,
 301
 302             Offset(0x08),
 303             PRQE,   8,
 304             PRQF,   8,
 305             PRQG,   8,
 306             PRQH,   8
 307         }
 308
 309         Method(IQST, 1, NotSerialized) {
 310             // _STA method - get status
 311             If (And(0x80, Arg0)) {
 312                 Return (0x09)
 313             }
 314             Return (0x0B)
 315         }
 316         Method(IQCR, 1, Serialized) {
 317             // _CRS method - get current settings
 318             Name(PRR0, ResourceTemplate() {
 319                 Interrupt(, Level, ActiveHigh, Shared) { 0 }
 320             })
 321             CreateDWordField(PRR0, 0x05, PRRI)
 322             Store(And(Arg0, 0x0F), PRRI)
 323             Return (PRR0)
 324         }
 325
 326 #define define_link(link, uid, reg)                             \
 327         Device(link) {                                          \
 328             Name(_HID, EISAID("PNP0C0F"))                       \
 329             Name(_UID, uid)                                     \
 330             Name(_PRS, ResourceTemplate() {                     \
 331                 Interrupt(, Level, ActiveHigh, Shared) {        \
 332                     5, 10, 11                                   \
 333                 }                                               \
 334             })                                                  \
 335             Method(_STA, 0, NotSerialized) {                    \
 336                 Return (IQST(reg))                              \
 337             }                                                   \
 338             Method(_DIS, 0, NotSerialized) {                    \
 339                 Or(reg, 0x80, reg)                              \
 340             }                                                   \
 341             Method(_CRS, 0, NotSerialized) {                    \
 342                 Return (IQCR(reg))                              \
 343             }                                                   \
 344             Method(_SRS, 1, NotSerialized) {                    \
 345                 CreateDWordField(Arg0, 0x05, PRRI)              \
 346                 Store(PRRI, reg)                                \
 347             }                                                   \
 348         }
 349
 350         define_link(LNKA, 0, PRQA)
 351         define_link(LNKB, 1, PRQB)
 352         define_link(LNKC, 2, PRQC)
 353         define_link(LNKD, 3, PRQD)
 354         define_link(LNKE, 4, PRQE)
 355         define_link(LNKF, 5, PRQF)
 356         define_link(LNKG, 6, PRQG)
 357         define_link(LNKH, 7, PRQH)
 358
 359 #define define_gsi_link(link, uid, gsi)                         \
 360         Device(link) {                                          \
 361             Name(_HID, EISAID("PNP0C0F"))                       \
 362             Name(_UID, uid)                                     \
 363             Name(_PRS, ResourceTemplate() {                     \
 364                 Interrupt(, Level, ActiveHigh, Shared) {        \
 365                     gsi                                         \
 366                 }                                               \
 367             })                                                  \
 368             Name(_CRS, ResourceTemplate() {                     \
 369                 Interrupt(, Level, ActiveHigh, Shared) {        \
 370                     gsi                                         \
 371                 }                                               \
 372             })                                                  \
 373             Method(_SRS, 1, NotSerialized) {                    \
 374             }                                                   \
 375         }
 376
 377         define_gsi_link(GSIA, 0, 0x10)
 378         define_gsi_link(GSIB, 0, 0x11)
 379         define_gsi_link(GSIC, 0, 0x12)
 380         define_gsi_link(GSID, 0, 0x13)
 381         define_gsi_link(GSIE, 0, 0x14)
 382         define_gsi_link(GSIF, 0, 0x15)
 383         define_gsi_link(GSIG, 0, 0x16)
 384         define_gsi_link(GSIH, 0, 0x17)
 385     }
 386
 387 #include "hw/acpi/pc-hotplug.h"
 388 #define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
 389 #include "acpi-dsdt-cpu-hotplug.dsl"
 390 #include "acpi-dsdt-mem-hotplug.dsl"
 391
 392
 393 /****************************************************************
 394  * General purpose events
 395  ****************************************************************/
 396     Scope(\_GPE) {
 397         Name(_HID, "ACPI0006")
 398
 399         Method(_L00) {
 400         }
 401         Method(_L01) {
 402         }
 403         Method(_E02) {
 404             // CPU hotplug event
 405             \_SB.PRSC()
 406         }
 407         Method(_E03) {
 408             // Memory hotplug event
 409             \_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD()
 410         }
 411         Method(_L04) {
 412         }
 413         Method(_L05) {
 414         }
 415         Method(_L06) {
 416         }
 417         Method(_L07) {
 418         }
 419         Method(_L08) {
 420         }
 421         Method(_L09) {
 422         }
 423         Method(_L0A) {
 424         }
 425         Method(_L0B) {
 426         }
 427         Method(_L0C) {
 428         }
 429         Method(_L0D) {
 430         }
 431         Method(_L0E) {
 432         }
 433         Method(_L0F) {
 434         }
 435     }
 436 }