hw/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_PIT
  27
  28 #define RW_STATE_LSB 0
  29 #define RW_STATE_MSB 1
  30 #define RW_STATE_WORD0 2
  31 #define RW_STATE_WORD1 3
  32 #define RW_STATE_LATCHED_WORD0 4
  33 #define RW_STATE_LATCHED_WORD1 5
  34
  35 PITChannelState pit_channels[3];
  36
  37 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  38
  39 static int pit_get_count(PITChannelState *s)
  40 {
  41     uint64_t d;
  42     int counter;
  43
  44     d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
  45     switch(s->mode) {
  46     case 0:
  47     case 1:
  48     case 4:
  49     case 5:
  50         counter = (s->count - d) & 0xffff;
  51         break;
  52     case 3:
  53         /* XXX: may be incorrect for odd counts */
  54         counter = s->count - ((2 * d) % s->count);
  55         break;
  56     default:
  57         counter = s->count - (d % s->count);
  58         break;
  59     }
  60     return counter;
  61 }
  62
  63 /* get pit output bit */
  64 int pit_get_out(PITChannelState *s, int64_t current_time)
  65 {
  66     uint64_t d;
  67     int out;
  68
  69     d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
  70     switch(s->mode) {
  71     default:
  72     case 0:
  73         out = (d >= s->count);
  74         break;
  75     case 1:
  76         out = (d < s->count);
  77         break;
  78     case 2:
  79         if ((d % s->count) == 0 && d != 0)
  80             out = 1;
  81         else
  82             out = 0;
  83         break;
  84     case 3:
  85         out = (d % s->count) < ((s->count + 1) >> 1);
  86         break;
  87     case 4:
  88     case 5:
  89         out = (d == s->count);
  90         break;
  91     }
  92     return out;
  93 }
  94
  95 /* return -1 if no transition will occur.  */
  96 static int64_t pit_get_next_transition_time(PITChannelState *s,
  97                                             int64_t current_time)
  98 {
  99     uint64_t d, next_time, base;
 100     int period2;
 101
 102     d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
 103     switch(s->mode) {
 104     default:
 105     case 0:
 106     case 1:
 107         if (d < s->count)
 108             next_time = s->count;
 109         else
 110             return -1;
 111         break;
 112     case 2:
 113         base = (d / s->count) * s->count;
 114         if ((d - base) == 0 && d != 0)
 115             next_time = base + s->count;
 116         else
 117             next_time = base + s->count + 1;
 118         break;
 119     case 3:
 120         base = (d / s->count) * s->count;
 121         period2 = ((s->count + 1) >> 1);
 122         if ((d - base) < period2)
 123             next_time = base + period2;
 124         else
 125             next_time = base + s->count;
 126         break;
 127     case 4:
 128     case 5:
 129         if (d < s->count)
 130             next_time = s->count;
 131         else if (d == s->count)
 132             next_time = s->count + 1;
 133         else
 134             return -1;
 135         break;
 136     }
 137     /* convert to timer units */
 138     next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
 139     return next_time;
 140 }
 141
 142 /* val must be 0 or 1 */
 143 void pit_set_gate(PITChannelState *s, int val)
 144 {
 145     switch(s->mode) {
 146     default:
 147     case 0:
 148     case 4:
 149         /* XXX: just disable/enable counting */
 150         break;
 151     case 1:
 152     case 5:
 153         if (s->gate < val) {
 154             /* restart counting on rising edge */
 155             s->count_load_time = qemu_get_clock(vm_clock);
 156             pit_irq_timer_update(s, s->count_load_time);
 157         }
 158         break;
 159     case 2:
 160     case 3:
 161         if (s->gate < val) {
 162             /* restart counting on rising edge */
 163             s->count_load_time = qemu_get_clock(vm_clock);
 164             pit_irq_timer_update(s, s->count_load_time);
 165         }
 166         /* XXX: disable/enable counting */
 167         break;
 168     }
 169     s->gate = val;
 170 }
 171
 172 static inline void pit_load_count(PITChannelState *s, int val)
 173 {
 174     if (val == 0)
 175         val = 0x10000;
 176     s->count_load_time = qemu_get_clock(vm_clock);
 177     s->count = val;
 178     pit_irq_timer_update(s, s->count_load_time);
 179 }
 180
 181 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 182 {
 183     int channel, access;
 184     PITChannelState *s;
 185
 186     addr &= 3;
 187     if (addr == 3) {
 188         channel = val >> 6;
 189         if (channel == 3)
 190             return;
 191         s = &pit_channels[channel];
 192         access = (val >> 4) & 3;
 193         switch(access) {
 194         case 0:
 195             s->latched_count = pit_get_count(s);
 196             s->rw_state = RW_STATE_LATCHED_WORD0;
 197             break;
 198         default:
 199             s->mode = (val >> 1) & 7;
 200             s->bcd = val & 1;
 201             s->rw_state = access - 1 +  RW_STATE_LSB;
 202             /* XXX: update irq timer ? */
 203             break;
 204         }
 205     } else {
 206         s = &pit_channels[addr];
 207         switch(s->rw_state) {
 208         case RW_STATE_LSB:
 209             pit_load_count(s, val);
 210             break;
 211         case RW_STATE_MSB:
 212             pit_load_count(s, val << 8);
 213             break;
 214         case RW_STATE_WORD0:
 215         case RW_STATE_WORD1:
 216             if (s->rw_state & 1) {
 217                 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
 218             } else {
 219                 s->latched_count = val;
 220             }
 221             s->rw_state ^= 1;
 222             break;
 223         }
 224     }
 225 }
 226
 227 static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
 228 {
 229     int ret, count;
 230     PITChannelState *s;
 231
 232     addr &= 3;
 233     s = &pit_channels[addr];
 234     switch(s->rw_state) {
 235     case RW_STATE_LSB:
 236     case RW_STATE_MSB:
 237     case RW_STATE_WORD0:
 238     case RW_STATE_WORD1:
 239         count = pit_get_count(s);
 240         if (s->rw_state & 1)
 241             ret = (count >> 8) & 0xff;
 242         else
 243             ret = count & 0xff;
 244         if (s->rw_state & 2)
 245             s->rw_state ^= 1;
 246         break;
 247     default:
 248     case RW_STATE_LATCHED_WORD0:
 249     case RW_STATE_LATCHED_WORD1:
 250         if (s->rw_state & 1)
 251             ret = s->latched_count >> 8;
 252         else
 253             ret = s->latched_count & 0xff;
 254         s->rw_state ^= 1;
 255         break;
 256     }
 257     return ret;
 258 }
 259
 260 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 261 {
 262     int64_t expire_time;
 263     int irq_level;
 264
 265     if (!s->irq_timer)
 266         return;
 267     expire_time = pit_get_next_transition_time(s, current_time);
 268     irq_level = pit_get_out(s, current_time);
 269     pic_set_irq(s->irq, irq_level);
 270 #ifdef DEBUG_PIT
 271     printf("irq_level=%d next_delay=%f\n",
 272            irq_level,
 273            (double)(expire_time - current_time) / ticks_per_sec);
 274 #endif
 275     s->next_transition_time = expire_time;
 276     if (expire_time != -1)
 277         qemu_mod_timer(s->irq_timer, expire_time);
 278     else
 279         qemu_del_timer(s->irq_timer);
 280 }
 281
 282 static void pit_irq_timer(void *opaque)
 283 {
 284     PITChannelState *s = opaque;
 285
 286     pit_irq_timer_update(s, s->next_transition_time);
 287 }
 288
 289 static void pit_save(QEMUFile *f, void *opaque)
 290 {
 291     PITChannelState *s;
 292     int i;
 293
 294     for(i = 0; i < 3; i++) {
 295         s = &pit_channels[i];
 296         qemu_put_be32s(f, &s->count);
 297         qemu_put_be16s(f, &s->latched_count);
 298         qemu_put_8s(f, &s->rw_state);
 299         qemu_put_8s(f, &s->mode);
 300         qemu_put_8s(f, &s->bcd);
 301         qemu_put_8s(f, &s->gate);
 302         qemu_put_be64s(f, &s->count_load_time);
 303         if (s->irq_timer) {
 304             qemu_put_be64s(f, &s->next_transition_time);
 305             qemu_put_timer(f, s->irq_timer);
 306         }
 307     }
 308 }
 309
 310 static int pit_load(QEMUFile *f, void *opaque, int version_id)
 311 {
 312     PITChannelState *s;
 313     int i;
 314
 315     if (version_id != 1)
 316         return -EINVAL;
 317
 318     for(i = 0; i < 3; i++) {
 319         s = &pit_channels[i];
 320         qemu_get_be32s(f, &s->count);
 321         qemu_get_be16s(f, &s->latched_count);
 322         qemu_get_8s(f, &s->rw_state);
 323         qemu_get_8s(f, &s->mode);
 324         qemu_get_8s(f, &s->bcd);
 325         qemu_get_8s(f, &s->gate);
 326         qemu_get_be64s(f, &s->count_load_time);
 327         if (s->irq_timer) {
 328             qemu_get_be64s(f, &s->next_transition_time);
 329             qemu_get_timer(f, s->irq_timer);
 330         }
 331     }
 332     return 0;
 333 }
 334
 335 void pit_init(int base, int irq)
 336 {
 337     PITChannelState *s;
 338     int i;
 339
 340     for(i = 0;i < 3; i++) {
 341         s = &pit_channels[i];
 342         if (i == 0) {
 343             /* the timer 0 is connected to an IRQ */
 344             s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
 345             s->irq = irq;
 346         }
 347         s->mode = 3;
 348         s->gate = (i != 2);
 349         pit_load_count(s, 0);
 350     }
 351
 352     register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
 353
 354     register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
 355     register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
 356 }
 357