2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-timer.h"
34 #define DPRINTF(fmt, ...) \
35 do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
40 //#define DEBUG_IRQ_LATENCY
41 //#define DEBUG_IRQ_COUNT
43 typedef struct PicState
{
44 uint8_t last_irr
; /* edge detection */
45 uint8_t irr
; /* interrupt request register */
46 uint8_t imr
; /* interrupt mask register */
47 uint8_t isr
; /* interrupt service register */
48 uint8_t priority_add
; /* highest irq priority */
50 uint8_t read_reg_select
;
55 uint8_t rotate_on_auto_eoi
;
56 uint8_t special_fully_nested_mode
;
57 uint8_t init4
; /* true if 4 byte init */
58 uint8_t single_mode
; /* true if slave pic is not initialized */
59 uint8_t elcr
; /* PIIX edge/trigger selection*/
62 bool master
; /* reflects /SP input pin */
68 /* 0 is master pic, 1 is slave pic */
69 /* XXX: better separation between the two pics */
71 void *irq_request_opaque
;
74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
75 static int irq_level
[16];
77 #ifdef DEBUG_IRQ_COUNT
78 static uint64_t irq_count
[16];
82 /* return the highest priority found in mask (highest = smallest
83 number). Return 8 if no irq */
84 static int get_priority(PicState
*s
, int mask
)
90 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
95 /* return the pic wanted interrupt. return -1 if none */
96 static int pic_get_irq(PicState
*s
)
98 int mask
, cur_priority
, priority
;
100 mask
= s
->irr
& ~s
->imr
;
101 priority
= get_priority(s
, mask
);
104 /* compute current priority. If special fully nested mode on the
105 master, the IRQ coming from the slave is not taken into account
106 for the priority computation. */
110 if (s
->special_fully_nested_mode
&& s
->master
) {
113 cur_priority
= get_priority(s
, mask
);
114 if (priority
< cur_priority
) {
115 /* higher priority found: an irq should be generated */
116 return (priority
+ s
->priority_add
) & 7;
122 /* Update INT output. Must be called every time the output may have changed. */
123 static void pic_update_irq(PicState
*s
)
127 irq
= pic_get_irq(s
);
129 DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
130 s
->master
? 0 : 1, s
->imr
, s
->irr
, s
->priority_add
);
131 qemu_irq_raise(s
->int_out
);
133 qemu_irq_lower(s
->int_out
);
137 /* set irq level. If an edge is detected, then the IRR is set to 1 */
138 static void pic_set_irq1(PicState
*s
, int irq
, int level
)
142 if (s
->elcr
& mask
) {
143 /* level triggered */
149 s
->last_irr
&= ~mask
;
154 if ((s
->last_irr
& mask
) == 0) {
159 s
->last_irr
&= ~mask
;
165 #ifdef DEBUG_IRQ_LATENCY
166 int64_t irq_time
[16];
169 static void i8259_set_irq(void *opaque
, int irq
, int level
)
171 PicState2
*s
= opaque
;
173 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
174 if (level
!= irq_level
[irq
]) {
175 DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq
, level
);
176 irq_level
[irq
] = level
;
177 #ifdef DEBUG_IRQ_COUNT
183 #ifdef DEBUG_IRQ_LATENCY
185 irq_time
[irq
] = qemu_get_clock_ns(vm_clock
);
188 pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
191 /* acknowledge interrupt 'irq' */
192 static void pic_intack(PicState
*s
, int irq
)
195 if (s
->rotate_on_auto_eoi
)
196 s
->priority_add
= (irq
+ 1) & 7;
198 s
->isr
|= (1 << irq
);
200 /* We don't clear a level sensitive interrupt here */
201 if (!(s
->elcr
& (1 << irq
)))
202 s
->irr
&= ~(1 << irq
);
206 int pic_read_irq(PicState2
*s
)
208 int irq
, irq2
, intno
;
210 irq
= pic_get_irq(&s
->pics
[0]);
213 irq2
= pic_get_irq(&s
->pics
[1]);
215 pic_intack(&s
->pics
[1], irq2
);
217 /* spurious IRQ on slave controller */
220 intno
= s
->pics
[1].irq_base
+ irq2
;
222 intno
= s
->pics
[0].irq_base
+ irq
;
224 pic_intack(&s
->pics
[0], irq
);
226 /* spurious IRQ on host controller */
228 intno
= s
->pics
[0].irq_base
+ irq
;
231 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
236 #ifdef DEBUG_IRQ_LATENCY
237 printf("IRQ%d latency=%0.3fus\n",
239 (double)(qemu_get_clock_ns(vm_clock
) -
240 irq_time
[irq
]) * 1000000.0 / get_ticks_per_sec());
242 DPRINTF("pic_interrupt: irq=%d\n", irq
);
246 static void pic_init_reset(PicState
*s
)
254 s
->read_reg_select
= 0;
259 s
->rotate_on_auto_eoi
= 0;
260 s
->special_fully_nested_mode
= 0;
263 /* Note: ELCR is not reset */
267 static void pic_reset(void *opaque
)
269 PicState
*s
= opaque
;
275 static void pic_ioport_write(void *opaque
, target_phys_addr_t addr64
,
276 uint64_t val64
, unsigned size
)
278 PicState
*s
= opaque
;
279 uint32_t addr
= addr64
;
280 uint32_t val
= val64
;
281 int priority
, cmd
, irq
;
283 DPRINTF("write: addr=0x%02x val=0x%02x\n", addr
, val
);
289 s
->single_mode
= val
& 2;
291 hw_error("level sensitive irq not supported");
292 } else if (val
& 0x08) {
296 s
->read_reg_select
= val
& 1;
298 s
->special_mask
= (val
>> 5) & 1;
304 s
->rotate_on_auto_eoi
= cmd
>> 2;
306 case 1: /* end of interrupt */
308 priority
= get_priority(s
, s
->isr
);
310 irq
= (priority
+ s
->priority_add
) & 7;
311 s
->isr
&= ~(1 << irq
);
313 s
->priority_add
= (irq
+ 1) & 7;
319 s
->isr
&= ~(1 << irq
);
323 s
->priority_add
= (val
+ 1) & 7;
328 s
->isr
&= ~(1 << irq
);
329 s
->priority_add
= (irq
+ 1) & 7;
338 switch(s
->init_state
) {
345 s
->irq_base
= val
& 0xf8;
346 s
->init_state
= s
->single_mode
? (s
->init4
? 3 : 0) : 2;
356 s
->special_fully_nested_mode
= (val
>> 4) & 1;
357 s
->auto_eoi
= (val
>> 1) & 1;
364 static uint64_t pic_ioport_read(void *opaque
, target_phys_addr_t addr
,
367 PicState
*s
= opaque
;
371 ret
= pic_get_irq(s
);
381 if (s
->read_reg_select
)
389 DPRINTF("read: addr=0x%02x val=0x%02x\n", addr
, ret
);
393 int pic_get_output(PicState2
*s
)
395 return (pic_get_irq(&s
->pics
[0]) >= 0);
398 static void elcr_ioport_write(void *opaque
, target_phys_addr_t addr
,
399 uint64_t val
, unsigned size
)
401 PicState
*s
= opaque
;
402 s
->elcr
= val
& s
->elcr_mask
;
405 static uint64_t elcr_ioport_read(void *opaque
, target_phys_addr_t addr
,
408 PicState
*s
= opaque
;
412 static const VMStateDescription vmstate_pic
= {
415 .minimum_version_id
= 1,
416 .minimum_version_id_old
= 1,
417 .fields
= (VMStateField
[]) {
418 VMSTATE_UINT8(last_irr
, PicState
),
419 VMSTATE_UINT8(irr
, PicState
),
420 VMSTATE_UINT8(imr
, PicState
),
421 VMSTATE_UINT8(isr
, PicState
),
422 VMSTATE_UINT8(priority_add
, PicState
),
423 VMSTATE_UINT8(irq_base
, PicState
),
424 VMSTATE_UINT8(read_reg_select
, PicState
),
425 VMSTATE_UINT8(poll
, PicState
),
426 VMSTATE_UINT8(special_mask
, PicState
),
427 VMSTATE_UINT8(init_state
, PicState
),
428 VMSTATE_UINT8(auto_eoi
, PicState
),
429 VMSTATE_UINT8(rotate_on_auto_eoi
, PicState
),
430 VMSTATE_UINT8(special_fully_nested_mode
, PicState
),
431 VMSTATE_UINT8(init4
, PicState
),
432 VMSTATE_UINT8(single_mode
, PicState
),
433 VMSTATE_UINT8(elcr
, PicState
),
434 VMSTATE_END_OF_LIST()
438 static const MemoryRegionOps pic_base_ioport_ops
= {
439 .read
= pic_ioport_read
,
440 .write
= pic_ioport_write
,
442 .min_access_size
= 1,
443 .max_access_size
= 1,
447 static const MemoryRegionOps pic_elcr_ioport_ops
= {
448 .read
= elcr_ioport_read
,
449 .write
= elcr_ioport_write
,
451 .min_access_size
= 1,
452 .max_access_size
= 1,
456 /* XXX: add generic master/slave system */
457 static void pic_init(int io_addr
, int elcr_addr
, PicState
*s
, qemu_irq int_out
,
460 s
->int_out
= int_out
;
463 memory_region_init_io(&s
->base_io
, &pic_base_ioport_ops
, s
, "pic", 2);
464 memory_region_init_io(&s
->elcr_io
, &pic_elcr_ioport_ops
, s
, "elcr", 1);
466 isa_register_ioport(NULL
, &s
->base_io
, io_addr
);
467 if (elcr_addr
>= 0) {
468 isa_register_ioport(NULL
, &s
->elcr_io
, elcr_addr
);
471 vmstate_register(NULL
, io_addr
, &vmstate_pic
, s
);
472 qemu_register_reset(pic_reset
, s
);
475 void pic_info(Monitor
*mon
)
484 s
= &isa_pic
->pics
[i
];
485 monitor_printf(mon
, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
486 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
487 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
488 s
->irq_base
, s
->read_reg_select
, s
->elcr
,
489 s
->special_fully_nested_mode
);
493 void irq_info(Monitor
*mon
)
495 #ifndef DEBUG_IRQ_COUNT
496 monitor_printf(mon
, "irq statistic code not compiled.\n");
501 monitor_printf(mon
, "IRQ statistics:\n");
502 for (i
= 0; i
< 16; i
++) {
503 count
= irq_count
[i
];
505 monitor_printf(mon
, "%2d: %" PRId64
"\n", i
, count
);
510 qemu_irq
*i8259_init(qemu_irq parent_irq
)
515 s
= g_malloc0(sizeof(PicState2
));
516 irqs
= qemu_allocate_irqs(i8259_set_irq
, s
, 16);
517 pic_init(0x20, 0x4d0, &s
->pics
[0], parent_irq
, true);
518 pic_init(0xa0, 0x4d1, &s
->pics
[1], irqs
[2], false);
519 s
->pics
[0].elcr_mask
= 0xf8;
520 s
->pics
[1].elcr_mask
= 0xde;