hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 #ifdef DEBUG_PIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 //#define DEBUG_IRQ_LATENCY
  41 //#define DEBUG_IRQ_COUNT
  42
  43 typedef struct PicState {
  44     uint8_t last_irr; /* edge detection */
  45     uint8_t irr; /* interrupt request register */
  46     uint8_t imr; /* interrupt mask register */
  47     uint8_t isr; /* interrupt service register */
  48     uint8_t priority_add; /* highest irq priority */
  49     uint8_t irq_base;
  50     uint8_t read_reg_select;
  51     uint8_t poll;
  52     uint8_t special_mask;
  53     uint8_t init_state;
  54     uint8_t auto_eoi;
  55     uint8_t rotate_on_auto_eoi;
  56     uint8_t special_fully_nested_mode;
  57     uint8_t init4; /* true if 4 byte init */
  58     uint8_t single_mode; /* true if slave pic is not initialized */
  59     uint8_t elcr; /* PIIX edge/trigger selection*/
  60     uint8_t elcr_mask;
  61     qemu_irq int_out;
  62     PicState2 *pics_state;
  63     MemoryRegion base_io;
  64     MemoryRegion elcr_io;
  65 } PicState;
  66
  67 struct PicState2 {
  68     /* 0 is master pic, 1 is slave pic */
  69     /* XXX: better separation between the two pics */
  70     PicState pics[2];
  71     void *irq_request_opaque;
  72 };
  73
  74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  75 static int irq_level[16];
  76 #endif
  77 #ifdef DEBUG_IRQ_COUNT
  78 static uint64_t irq_count[16];
  79 #endif
  80 PicState2 *isa_pic;
  81
  82 /* return the highest priority found in mask (highest = smallest
  83    number). Return 8 if no irq */
  84 static int get_priority(PicState *s, int mask)
  85 {
  86     int priority;
  87     if (mask == 0)
  88         return 8;
  89     priority = 0;
  90     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  91         priority++;
  92     return priority;
  93 }
  94
  95 /* return the pic wanted interrupt. return -1 if none */
  96 static int pic_get_irq(PicState *s)
  97 {
  98     int mask, cur_priority, priority;
  99
 100     mask = s->irr & ~s->imr;
 101     priority = get_priority(s, mask);
 102     if (priority == 8)
 103         return -1;
 104     /* compute current priority. If special fully nested mode on the
 105        master, the IRQ coming from the slave is not taken into account
 106        for the priority computation. */
 107     mask = s->isr;
 108     if (s->special_mask)
 109         mask &= ~s->imr;
 110     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 111         mask &= ~(1 << 2);
 112     cur_priority = get_priority(s, mask);
 113     if (priority < cur_priority) {
 114         /* higher priority found: an irq should be generated */
 115         return (priority + s->priority_add) & 7;
 116     } else {
 117         return -1;
 118     }
 119 }
 120
 121 static void pic_set_irq1(PicState *s, int irq, int level);
 122
 123 /* raise irq to CPU if necessary. must be called every time the active
 124    irq may change */
 125 static void pic_update_irq(PicState2 *s)
 126 {
 127     int irq2, irq;
 128
 129     /* first look at slave pic */
 130     irq2 = pic_get_irq(&s->pics[1]);
 131     if (irq2 >= 0) {
 132         /* if irq request by slave pic, signal master PIC */
 133         pic_set_irq1(&s->pics[0], 2, 1);
 134         pic_set_irq1(&s->pics[0], 2, 0);
 135     }
 136     /* look at requested irq */
 137     irq = pic_get_irq(&s->pics[0]);
 138     if (irq >= 0) {
 139 #if defined(DEBUG_PIC)
 140         {
 141             int i;
 142             for(i = 0; i < 2; i++) {
 143                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 144                        i, s->pics[i].imr, s->pics[i].irr,
 145                        s->pics[i].priority_add);
 146
 147             }
 148         }
 149         printf("pic: cpu_interrupt\n");
 150 #endif
 151         qemu_irq_raise(s->pics[0].int_out);
 152     } else {
 153         qemu_irq_lower(s->pics[0].int_out);
 154     }
 155 }
 156
 157 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 158 static void pic_set_irq1(PicState *s, int irq, int level)
 159 {
 160     int mask;
 161     mask = 1 << irq;
 162     if (s->elcr & mask) {
 163         /* level triggered */
 164         if (level) {
 165             s->irr |= mask;
 166             s->last_irr |= mask;
 167         } else {
 168             s->irr &= ~mask;
 169             s->last_irr &= ~mask;
 170         }
 171     } else {
 172         /* edge triggered */
 173         if (level) {
 174             if ((s->last_irr & mask) == 0) {
 175                 s->irr |= mask;
 176             }
 177             s->last_irr |= mask;
 178         } else {
 179             s->last_irr &= ~mask;
 180         }
 181     }
 182 }
 183
 184 #ifdef DEBUG_IRQ_LATENCY
 185 int64_t irq_time[16];
 186 #endif
 187
 188 static void i8259_set_irq(void *opaque, int irq, int level)
 189 {
 190     PicState2 *s = opaque;
 191
 192 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 193     if (level != irq_level[irq]) {
 194         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 195         irq_level[irq] = level;
 196 #ifdef DEBUG_IRQ_COUNT
 197         if (level == 1)
 198             irq_count[irq]++;
 199 #endif
 200     }
 201 #endif
 202 #ifdef DEBUG_IRQ_LATENCY
 203     if (level) {
 204         irq_time[irq] = qemu_get_clock_ns(vm_clock);
 205     }
 206 #endif
 207     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 208     pic_update_irq(s);
 209 }
 210
 211 /* acknowledge interrupt 'irq' */
 212 static void pic_intack(PicState *s, int irq)
 213 {
 214     if (s->auto_eoi) {
 215         if (s->rotate_on_auto_eoi)
 216             s->priority_add = (irq + 1) & 7;
 217     } else {
 218         s->isr |= (1 << irq);
 219     }
 220     /* We don't clear a level sensitive interrupt here */
 221     if (!(s->elcr & (1 << irq)))
 222         s->irr &= ~(1 << irq);
 223 }
 224
 225 int pic_read_irq(PicState2 *s)
 226 {
 227     int irq, irq2, intno;
 228
 229     irq = pic_get_irq(&s->pics[0]);
 230     if (irq >= 0) {
 231         pic_intack(&s->pics[0], irq);
 232         if (irq == 2) {
 233             irq2 = pic_get_irq(&s->pics[1]);
 234             if (irq2 >= 0) {
 235                 pic_intack(&s->pics[1], irq2);
 236             } else {
 237                 /* spurious IRQ on slave controller */
 238                 irq2 = 7;
 239             }
 240             intno = s->pics[1].irq_base + irq2;
 241 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 242             irq = irq2 + 8;
 243 #endif
 244         } else {
 245             intno = s->pics[0].irq_base + irq;
 246         }
 247     } else {
 248         /* spurious IRQ on host controller */
 249         irq = 7;
 250         intno = s->pics[0].irq_base + irq;
 251     }
 252     pic_update_irq(s);
 253
 254 #ifdef DEBUG_IRQ_LATENCY
 255     printf("IRQ%d latency=%0.3fus\n",
 256            irq,
 257            (double)(qemu_get_clock_ns(vm_clock) -
 258                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 259 #endif
 260     DPRINTF("pic_interrupt: irq=%d\n", irq);
 261     return intno;
 262 }
 263
 264 static void pic_reset(void *opaque)
 265 {
 266     PicState *s = opaque;
 267
 268     s->last_irr = 0;
 269     s->irr = 0;
 270     s->imr = 0;
 271     s->isr = 0;
 272     s->priority_add = 0;
 273     s->irq_base = 0;
 274     s->read_reg_select = 0;
 275     s->poll = 0;
 276     s->special_mask = 0;
 277     s->init_state = 0;
 278     s->auto_eoi = 0;
 279     s->rotate_on_auto_eoi = 0;
 280     s->special_fully_nested_mode = 0;
 281     s->init4 = 0;
 282     s->single_mode = 0;
 283     /* Note: ELCR is not reset */
 284 }
 285
 286 static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
 287                              uint64_t val64, unsigned size)
 288 {
 289     PicState *s = opaque;
 290     uint32_t addr = addr64;
 291     uint32_t val = val64;
 292     int priority, cmd, irq;
 293
 294     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 295     if (addr == 0) {
 296         if (val & 0x10) {
 297             /* init */
 298             pic_reset(s);
 299             /* deassert a pending interrupt */
 300             qemu_irq_lower(s->pics_state->pics[0].int_out);
 301             s->init_state = 1;
 302             s->init4 = val & 1;
 303             s->single_mode = val & 2;
 304             if (val & 0x08)
 305                 hw_error("level sensitive irq not supported");
 306         } else if (val & 0x08) {
 307             if (val & 0x04)
 308                 s->poll = 1;
 309             if (val & 0x02)
 310                 s->read_reg_select = val & 1;
 311             if (val & 0x40)
 312                 s->special_mask = (val >> 5) & 1;
 313         } else {
 314             cmd = val >> 5;
 315             switch(cmd) {
 316             case 0:
 317             case 4:
 318                 s->rotate_on_auto_eoi = cmd >> 2;
 319                 break;
 320             case 1: /* end of interrupt */
 321             case 5:
 322                 priority = get_priority(s, s->isr);
 323                 if (priority != 8) {
 324                     irq = (priority + s->priority_add) & 7;
 325                     s->isr &= ~(1 << irq);
 326                     if (cmd == 5)
 327                         s->priority_add = (irq + 1) & 7;
 328                     pic_update_irq(s->pics_state);
 329                 }
 330                 break;
 331             case 3:
 332                 irq = val & 7;
 333                 s->isr &= ~(1 << irq);
 334                 pic_update_irq(s->pics_state);
 335                 break;
 336             case 6:
 337                 s->priority_add = (val + 1) & 7;
 338                 pic_update_irq(s->pics_state);
 339                 break;
 340             case 7:
 341                 irq = val & 7;
 342                 s->isr &= ~(1 << irq);
 343                 s->priority_add = (irq + 1) & 7;
 344                 pic_update_irq(s->pics_state);
 345                 break;
 346             default:
 347                 /* no operation */
 348                 break;
 349             }
 350         }
 351     } else {
 352         switch(s->init_state) {
 353         case 0:
 354             /* normal mode */
 355             s->imr = val;
 356             pic_update_irq(s->pics_state);
 357             break;
 358         case 1:
 359             s->irq_base = val & 0xf8;
 360             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 361             break;
 362         case 2:
 363             if (s->init4) {
 364                 s->init_state = 3;
 365             } else {
 366                 s->init_state = 0;
 367             }
 368             break;
 369         case 3:
 370             s->special_fully_nested_mode = (val >> 4) & 1;
 371             s->auto_eoi = (val >> 1) & 1;
 372             s->init_state = 0;
 373             break;
 374         }
 375     }
 376 }
 377
 378 static uint32_t pic_poll_read(PicState *s)
 379 {
 380     int ret;
 381
 382     ret = pic_get_irq(s);
 383     if (ret >= 0) {
 384         bool slave = (s == &isa_pic->pics[1]);
 385
 386         if (slave) {
 387             s->pics_state->pics[0].isr &= ~(1 << 2);
 388             s->pics_state->pics[0].irr &= ~(1 << 2);
 389         }
 390         s->irr &= ~(1 << ret);
 391         s->isr &= ~(1 << ret);
 392         if (slave || ret != 2)
 393             pic_update_irq(s->pics_state);
 394     } else {
 395         ret = 0x07;
 396         pic_update_irq(s->pics_state);
 397     }
 398
 399     return ret;
 400 }
 401
 402 static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
 403                                 unsigned size)
 404 {
 405     PicState *s = opaque;
 406     unsigned int addr = addr1;
 407     int ret;
 408
 409     if (s->poll) {
 410         ret = pic_poll_read(s);
 411         s->poll = 0;
 412     } else {
 413         if (addr == 0) {
 414             if (s->read_reg_select)
 415                 ret = s->isr;
 416             else
 417                 ret = s->irr;
 418         } else {
 419             ret = s->imr;
 420         }
 421     }
 422     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
 423     return ret;
 424 }
 425
 426 /* memory mapped interrupt status */
 427 /* XXX: may be the same than pic_read_irq() */
 428 uint32_t pic_intack_read(PicState2 *s)
 429 {
 430     int ret;
 431
 432     ret = pic_poll_read(&s->pics[0]);
 433     if (ret == 2)
 434         ret = pic_poll_read(&s->pics[1]) + 8;
 435     /* Prepare for ISR read */
 436     s->pics[0].read_reg_select = 1;
 437
 438     return ret;
 439 }
 440
 441 int pic_get_output(PicState2 *s)
 442 {
 443     return (pic_get_irq(&s->pics[0]) >= 0);
 444 }
 445
 446 static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
 447                               uint64_t val, unsigned size)
 448 {
 449     PicState *s = opaque;
 450     s->elcr = val & s->elcr_mask;
 451 }
 452
 453 static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
 454                                  unsigned size)
 455 {
 456     PicState *s = opaque;
 457     return s->elcr;
 458 }
 459
 460 static const VMStateDescription vmstate_pic = {
 461     .name = "i8259",
 462     .version_id = 1,
 463     .minimum_version_id = 1,
 464     .minimum_version_id_old = 1,
 465     .fields      = (VMStateField []) {
 466         VMSTATE_UINT8(last_irr, PicState),
 467         VMSTATE_UINT8(irr, PicState),
 468         VMSTATE_UINT8(imr, PicState),
 469         VMSTATE_UINT8(isr, PicState),
 470         VMSTATE_UINT8(priority_add, PicState),
 471         VMSTATE_UINT8(irq_base, PicState),
 472         VMSTATE_UINT8(read_reg_select, PicState),
 473         VMSTATE_UINT8(poll, PicState),
 474         VMSTATE_UINT8(special_mask, PicState),
 475         VMSTATE_UINT8(init_state, PicState),
 476         VMSTATE_UINT8(auto_eoi, PicState),
 477         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 478         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 479         VMSTATE_UINT8(init4, PicState),
 480         VMSTATE_UINT8(single_mode, PicState),
 481         VMSTATE_UINT8(elcr, PicState),
 482         VMSTATE_END_OF_LIST()
 483     }
 484 };
 485
 486 static const MemoryRegionOps pic_base_ioport_ops = {
 487     .read = pic_ioport_read,
 488     .write = pic_ioport_write,
 489     .impl = {
 490         .min_access_size = 1,
 491         .max_access_size = 1,
 492     },
 493 };
 494
 495 static const MemoryRegionOps pic_elcr_ioport_ops = {
 496     .read = elcr_ioport_read,
 497     .write = elcr_ioport_write,
 498     .impl = {
 499         .min_access_size = 1,
 500         .max_access_size = 1,
 501     },
 502 };
 503
 504 /* XXX: add generic master/slave system */
 505 static void pic_init(int io_addr, int elcr_addr, PicState *s, qemu_irq int_out)
 506 {
 507     s->int_out = int_out;
 508
 509     memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
 510     memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
 511
 512     isa_register_ioport(NULL, &s->base_io, io_addr);
 513     if (elcr_addr >= 0) {
 514         isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
 515     }
 516
 517     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 518     qemu_register_reset(pic_reset, s);
 519 }
 520
 521 void pic_info(Monitor *mon)
 522 {
 523     int i;
 524     PicState *s;
 525
 526     if (!isa_pic)
 527         return;
 528
 529     for(i=0;i<2;i++) {
 530         s = &isa_pic->pics[i];
 531         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 532                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 533                        i, s->irr, s->imr, s->isr, s->priority_add,
 534                        s->irq_base, s->read_reg_select, s->elcr,
 535                        s->special_fully_nested_mode);
 536     }
 537 }
 538
 539 void irq_info(Monitor *mon)
 540 {
 541 #ifndef DEBUG_IRQ_COUNT
 542     monitor_printf(mon, "irq statistic code not compiled.\n");
 543 #else
 544     int i;
 545     int64_t count;
 546
 547     monitor_printf(mon, "IRQ statistics:\n");
 548     for (i = 0; i < 16; i++) {
 549         count = irq_count[i];
 550         if (count > 0)
 551             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 552     }
 553 #endif
 554 }
 555
 556 qemu_irq *i8259_init(qemu_irq parent_irq)
 557 {
 558     qemu_irq *irqs;
 559     PicState2 *s;
 560
 561     s = g_malloc0(sizeof(PicState2));
 562     irqs = qemu_allocate_irqs(i8259_set_irq, s, 16);
 563     pic_init(0x20, 0x4d0, &s->pics[0], parent_irq);
 564     pic_init(0xa0, 0x4d1, &s->pics[1], irqs[2]);
 565     s->pics[0].elcr_mask = 0xf8;
 566     s->pics[1].elcr_mask = 0xde;
 567     s->pics[0].pics_state = s;
 568     s->pics[1].pics_state = s;
 569     isa_pic = s;
 570     return irqs;
 571 }