hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t elcr; /* PIIX edge/trigger selection*/
  48     uint8_t elcr_mask;
  49 } PicState;
  50
  51 /* 0 is master pic, 1 is slave pic */
  52 static PicState pics[2];
  53
  54 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  55 static int irq_level[16];
  56 #endif
  57 #ifdef DEBUG_IRQ_COUNT
  58 static uint64_t irq_count[16];
  59 #endif
  60
  61 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  62 static inline void pic_set_irq1(PicState *s, int irq, int level)
  63 {
  64     int mask;
  65     mask = 1 << irq;
  66     if (s->elcr & mask) {
  67         /* level triggered */
  68         if (level) {
  69             s->irr |= mask;
  70             s->last_irr |= mask;
  71         } else {
  72             s->irr &= ~mask;
  73             s->last_irr &= ~mask;
  74         }
  75     } else {
  76         /* edge triggered */
  77         if (level) {
  78             if ((s->last_irr & mask) == 0)
  79                 s->irr |= mask;
  80             s->last_irr |= mask;
  81         } else {
  82             s->last_irr &= ~mask;
  83         }
  84     }
  85 }
  86
  87 /* return the highest priority found in mask (highest = smallest
  88    number). Return 8 if no irq */
  89 static inline int get_priority(PicState *s, int mask)
  90 {
  91     int priority;
  92     if (mask == 0)
  93         return 8;
  94     priority = 0;
  95     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  96         priority++;
  97     return priority;
  98 }
  99
 100 /* return the pic wanted interrupt. return -1 if none */
 101 static int pic_get_irq(PicState *s)
 102 {
 103     int mask, cur_priority, priority;
 104
 105     mask = s->irr & ~s->imr;
 106     priority = get_priority(s, mask);
 107     if (priority == 8)
 108         return -1;
 109     /* compute current priority. If special fully nested mode on the
 110        master, the IRQ coming from the slave is not taken into account
 111        for the priority computation. */
 112     mask = s->isr;
 113     if (s->special_fully_nested_mode && s == &pics[0])
 114         mask &= ~(1 << 2);
 115     cur_priority = get_priority(s, mask);
 116     if (priority < cur_priority) {
 117         /* higher priority found: an irq should be generated */
 118         return (priority + s->priority_add) & 7;
 119     } else {
 120         return -1;
 121     }
 122 }
 123
 124 /* raise irq to CPU if necessary. must be called every time the active
 125    irq may change */
 126 static void pic_update_irq(void)
 127 {
 128     int irq2, irq;
 129
 130     /* first look at slave pic */
 131     irq2 = pic_get_irq(&pics[1]);
 132     if (irq2 >= 0) {
 133         /* if irq request by slave pic, signal master PIC */
 134         pic_set_irq1(&pics[0], 2, 1);
 135         pic_set_irq1(&pics[0], 2, 0);
 136     }
 137     /* look at requested irq */
 138     irq = pic_get_irq(&pics[0]);
 139     if (irq >= 0) {
 140 #if defined(DEBUG_PIC)
 141         {
 142             int i;
 143             for(i = 0; i < 2; i++) {
 144                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 145                        i, pics[i].imr, pics[i].irr, pics[i].priority_add);
 146
 147             }
 148         }
 149         printf("pic: cpu_interrupt\n");
 150 #endif
 151         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 152     }
 153 }
 154
 155 #ifdef DEBUG_IRQ_LATENCY
 156 int64_t irq_time[16];
 157 #endif
 158
 159 void pic_set_irq(int irq, int level)
 160 {
 161 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 162     if (level != irq_level[irq]) {
 163 #if defined(DEBUG_PIC)
 164         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
 165 #endif
 166         irq_level[irq] = level;
 167 #ifdef DEBUG_IRQ_COUNT
 168         if (level == 1)
 169             irq_count[irq]++;
 170 #endif
 171     }
 172 #endif
 173 #ifdef DEBUG_IRQ_LATENCY
 174     if (level) {
 175         irq_time[irq] = qemu_get_clock(vm_clock);
 176     }
 177 #endif
 178     pic_set_irq1(&pics[irq >> 3], irq & 7, level);
 179     pic_update_irq();
 180 }
 181
 182 /* acknowledge interrupt 'irq' */
 183 static inline void pic_intack(PicState *s, int irq)
 184 {
 185     if (s->auto_eoi) {
 186         if (s->rotate_on_auto_eoi)
 187             s->priority_add = (irq + 1) & 7;
 188     } else {
 189         s->isr |= (1 << irq);
 190     }
 191     s->irr &= ~(1 << irq);
 192 }
 193
 194 int cpu_get_pic_interrupt(CPUState *env)
 195 {
 196     int irq, irq2, intno;
 197
 198     /* read the irq from the PIC */
 199
 200     irq = pic_get_irq(&pics[0]);
 201     if (irq >= 0) {
 202         pic_intack(&pics[0], irq);
 203         if (irq == 2) {
 204             irq2 = pic_get_irq(&pics[1]);
 205             if (irq2 >= 0) {
 206                 pic_intack(&pics[1], irq2);
 207             } else {
 208                 /* spurious IRQ on slave controller */
 209                 irq2 = 7;
 210             }
 211             intno = pics[1].irq_base + irq2;
 212             irq = irq2 + 8;
 213         } else {
 214             intno = pics[0].irq_base + irq;
 215         }
 216     } else {
 217         /* spurious IRQ on host controller */
 218         irq = 7;
 219         intno = pics[0].irq_base + irq;
 220     }
 221     pic_update_irq();
 222
 223 #ifdef DEBUG_IRQ_LATENCY
 224     printf("IRQ%d latency=%0.3fus\n",
 225            irq,
 226            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 227 #endif
 228 #if defined(DEBUG_PIC)
 229     printf("pic_interrupt: irq=%d\n", irq);
 230 #endif
 231     return intno;
 232 }
 233
 234 static void pic_reset(void *opaque)
 235 {
 236     PicState *s = opaque;
 237     int tmp;
 238
 239     tmp = s->elcr_mask;
 240     memset(s, 0, sizeof(PicState));
 241     s->elcr_mask = tmp;
 242 }
 243
 244 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 245 {
 246     PicState *s = opaque;
 247     int priority, cmd, irq;
 248
 249 #ifdef DEBUG_PIC
 250     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 251 #endif
 252     addr &= 1;
 253     if (addr == 0) {
 254         if (val & 0x10) {
 255             /* init */
 256             pic_reset(s);
 257             /* deassert a pending interrupt */
 258             cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 259
 260             s->init_state = 1;
 261             s->init4 = val & 1;
 262             if (val & 0x02)
 263                 hw_error("single mode not supported");
 264             if (val & 0x08)
 265                 hw_error("level sensitive irq not supported");
 266         } else if (val & 0x08) {
 267             if (val & 0x04)
 268                 s->poll = 1;
 269             if (val & 0x02)
 270                 s->read_reg_select = val & 1;
 271             if (val & 0x40)
 272                 s->special_mask = (val >> 5) & 1;
 273         } else {
 274             cmd = val >> 5;
 275             switch(cmd) {
 276             case 0:
 277             case 4:
 278                 s->rotate_on_auto_eoi = cmd >> 2;
 279                 break;
 280             case 1: /* end of interrupt */
 281             case 5:
 282                 priority = get_priority(s, s->isr);
 283                 if (priority != 8) {
 284                     irq = (priority + s->priority_add) & 7;
 285                     s->isr &= ~(1 << irq);
 286                     if (cmd == 5)
 287                         s->priority_add = (irq + 1) & 7;
 288                     pic_update_irq();
 289                 }
 290                 break;
 291             case 3:
 292                 irq = val & 7;
 293                 s->isr &= ~(1 << irq);
 294                 pic_update_irq();
 295                 break;
 296             case 6:
 297                 s->priority_add = (val + 1) & 7;
 298                 pic_update_irq();
 299                 break;
 300             case 7:
 301                 irq = val & 7;
 302                 s->isr &= ~(1 << irq);
 303                 s->priority_add = (irq + 1) & 7;
 304                 pic_update_irq();
 305                 break;
 306             default:
 307                 /* no operation */
 308                 break;
 309             }
 310         }
 311     } else {
 312         switch(s->init_state) {
 313         case 0:
 314             /* normal mode */
 315             s->imr = val;
 316             pic_update_irq();
 317             break;
 318         case 1:
 319             s->irq_base = val & 0xf8;
 320             s->init_state = 2;
 321             break;
 322         case 2:
 323             if (s->init4) {
 324                 s->init_state = 3;
 325             } else {
 326                 s->init_state = 0;
 327             }
 328             break;
 329         case 3:
 330             s->special_fully_nested_mode = (val >> 4) & 1;
 331             s->auto_eoi = (val >> 1) & 1;
 332             s->init_state = 0;
 333             break;
 334         }
 335     }
 336 }
 337
 338 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 339 {
 340     int ret;
 341
 342     ret = pic_get_irq(s);
 343     if (ret >= 0) {
 344         if (addr1 >> 7) {
 345             pics[0].isr &= ~(1 << 2);
 346             pics[0].irr &= ~(1 << 2);
 347         }
 348         s->irr &= ~(1 << ret);
 349         s->isr &= ~(1 << ret);
 350         if (addr1 >> 7 || ret != 2)
 351             pic_update_irq();
 352     } else {
 353         ret = 0x07;
 354         pic_update_irq();
 355     }
 356
 357     return ret;
 358 }
 359
 360 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 361 {
 362     PicState *s = opaque;
 363     unsigned int addr;
 364     int ret;
 365
 366     addr = addr1;
 367     addr &= 1;
 368     if (s->poll) {
 369         ret = pic_poll_read(s, addr1);
 370         s->poll = 0;
 371     } else {
 372         if (addr == 0) {
 373             if (s->read_reg_select)
 374                 ret = s->isr;
 375             else
 376                 ret = s->irr;
 377         } else {
 378             ret = s->imr;
 379         }
 380     }
 381 #ifdef DEBUG_PIC
 382     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 383 #endif
 384     return ret;
 385 }
 386
 387 /* memory mapped interrupt status */
 388 uint32_t pic_intack_read(CPUState *env)
 389 {
 390     int ret;
 391
 392     ret = pic_poll_read(&pics[0], 0x00);
 393     if (ret == 2)
 394         ret = pic_poll_read(&pics[1], 0x80) + 8;
 395     /* Prepare for ISR read */
 396     pics[0].read_reg_select = 1;
 397
 398     return ret;
 399 }
 400
 401 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 402 {
 403     PicState *s = opaque;
 404     s->elcr = val & s->elcr_mask;
 405 }
 406
 407 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 408 {
 409     PicState *s = opaque;
 410     return s->elcr;
 411 }
 412
 413 static void pic_save(QEMUFile *f, void *opaque)
 414 {
 415     PicState *s = opaque;
 416
 417     qemu_put_8s(f, &s->last_irr);
 418     qemu_put_8s(f, &s->irr);
 419     qemu_put_8s(f, &s->imr);
 420     qemu_put_8s(f, &s->isr);
 421     qemu_put_8s(f, &s->priority_add);
 422     qemu_put_8s(f, &s->irq_base);
 423     qemu_put_8s(f, &s->read_reg_select);
 424     qemu_put_8s(f, &s->poll);
 425     qemu_put_8s(f, &s->special_mask);
 426     qemu_put_8s(f, &s->init_state);
 427     qemu_put_8s(f, &s->auto_eoi);
 428     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 429     qemu_put_8s(f, &s->special_fully_nested_mode);
 430     qemu_put_8s(f, &s->init4);
 431     qemu_put_8s(f, &s->elcr);
 432 }
 433
 434 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 435 {
 436     PicState *s = opaque;
 437
 438     if (version_id != 1)
 439         return -EINVAL;
 440
 441     qemu_get_8s(f, &s->last_irr);
 442     qemu_get_8s(f, &s->irr);
 443     qemu_get_8s(f, &s->imr);
 444     qemu_get_8s(f, &s->isr);
 445     qemu_get_8s(f, &s->priority_add);
 446     qemu_get_8s(f, &s->irq_base);
 447     qemu_get_8s(f, &s->read_reg_select);
 448     qemu_get_8s(f, &s->poll);
 449     qemu_get_8s(f, &s->special_mask);
 450     qemu_get_8s(f, &s->init_state);
 451     qemu_get_8s(f, &s->auto_eoi);
 452     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 453     qemu_get_8s(f, &s->special_fully_nested_mode);
 454     qemu_get_8s(f, &s->init4);
 455     qemu_get_8s(f, &s->elcr);
 456     return 0;
 457 }
 458
 459 /* XXX: add generic master/slave system */
 460 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 461 {
 462     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 463     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 464     if (elcr_addr >= 0) {
 465         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 466         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 467     }
 468     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 469     qemu_register_reset(pic_reset, s);
 470 }
 471
 472 void pic_info(void)
 473 {
 474     int i;
 475     PicState *s;
 476
 477     for(i=0;i<2;i++) {
 478         s = &pics[i];
 479         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 480                     i, s->irr, s->imr, s->isr, s->priority_add,
 481                     s->irq_base, s->read_reg_select, s->elcr,
 482                     s->special_fully_nested_mode);
 483     }
 484 }
 485
 486 void irq_info(void)
 487 {
 488 #ifndef DEBUG_IRQ_COUNT
 489     term_printf("irq statistic code not compiled.\n");
 490 #else
 491     int i;
 492     int64_t count;
 493
 494     term_printf("IRQ statistics:\n");
 495     for (i = 0; i < 16; i++) {
 496         count = irq_count[i];
 497         if (count > 0)
 498             term_printf("%2d: %lld\n", i, count);
 499     }
 500 #endif
 501 }
 502
 503 void pic_init(void)
 504 {
 505     pic_init1(0x20, 0x4d0, &pics[0]);
 506     pic_init1(0xa0, 0x4d1, &pics[1]);
 507     pics[0].elcr_mask = 0xf8;
 508     pics[1].elcr_mask = 0xde;
 509 }
 510