hw/ich9.h

   1 #ifndef HW_ICH9_H
   2 #define HW_ICH9_H
   3
   4 #include "hw/hw.h"
   5 #include "qemu/range.h"
   6 #include "hw/isa.h"
   7 #include "hw/sysbus.h"
   8 #include "hw/pc.h"
   9 #include "hw/apm.h"
  10 #include "hw/ioapic.h"
  11 #include "hw/pci/pci.h"
  12 #include "hw/pci/pcie_host.h"
  13 #include "hw/pci/pci_bridge.h"
  14 #include "hw/acpi.h"
  15 #include "hw/acpi_ich9.h"
  16 #include "hw/pam.h"
  17 #include "hw/pci/pci_bus.h"
  18
  19 void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
  20 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
  21 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
  22 void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
  23 PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
  24 i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
  25
  26 #define ICH9_CC_SIZE                            (16 * 1024)     /* 16KB */
  27
  28 #define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
  29 #define ICH9_LPC_DEVICE(obj) \
  30      OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
  31
  32 typedef struct ICH9LPCState {
  33     /* ICH9 LPC PCI to ISA bridge */
  34     PCIDevice d;
  35
  36     /* (pci device, intx) -> pirq
  37      * In real chipset case, the unused slots are never used
  38      * as ICH9 supports only D25-D32 irq routing.
  39      * On the other hand in qemu case, any slot/function can be populated
  40      * via command line option.
  41      * So fallback interrupt routing for any devices in any slots is necessary.
  42     */
  43     uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
  44
  45     APMState apm;
  46     ICH9LPCPMRegs pm;
  47     uint32_t sci_level; /* track sci level */
  48
  49     /* 10.1 Chipset Configuration registers(Memory Space)
  50      which is pointed by RCBA */
  51     uint8_t chip_config[ICH9_CC_SIZE];
  52     /* isa bus */
  53     ISABus *isa_bus;
  54     MemoryRegion rbca_mem;
  55     Notifier machine_ready;
  56
  57     qemu_irq *pic;
  58     qemu_irq *ioapic;
  59 } ICH9LPCState;
  60
  61 #define Q35_MASK(bit, ms_bit, ls_bit) \
  62 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
  63
  64 /* ICH9: Chipset Configuration Registers */
  65 #define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)
  66
  67 #define ICH9_CC
  68 #define ICH9_CC_D28IP                           0x310C
  69 #define ICH9_CC_D28IP_SHIFT                     4
  70 #define ICH9_CC_D28IP_MASK                      0xf
  71 #define ICH9_CC_D28IP_DEFAULT                   0x00214321
  72 #define ICH9_CC_D31IR                           0x3140
  73 #define ICH9_CC_D30IR                           0x3142
  74 #define ICH9_CC_D29IR                           0x3144
  75 #define ICH9_CC_D28IR                           0x3146
  76 #define ICH9_CC_D27IR                           0x3148
  77 #define ICH9_CC_D26IR                           0x314C
  78 #define ICH9_CC_D25IR                           0x3150
  79 #define ICH9_CC_DIR_DEFAULT                     0x3210
  80 #define ICH9_CC_D30IR_DEFAULT                   0x0
  81 #define ICH9_CC_DIR_SHIFT                       4
  82 #define ICH9_CC_DIR_MASK                        0x7
  83 #define ICH9_CC_OIC                             0x31FF
  84 #define ICH9_CC_OIC_AEN                         0x1
  85
  86 /* D28:F[0-5] */
  87 #define ICH9_PCIE_DEV                           28
  88 #define ICH9_PCIE_FUNC_MAX                      6
  89
  90
  91 /* D29:F0 USB UHCI Controller #1 */
  92 #define ICH9_USB_UHCI1_DEV                      29
  93 #define ICH9_USB_UHCI1_FUNC                     0
  94
  95 /* D30:F0 DMI-to-PCI brdige */
  96 #define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
  97 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0
  98
  99 #define ICH9_D2P_BRIDGE_DEV                     30
 100 #define ICH9_D2P_BRIDGE_FUNC                    0
 101
 102 #define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)
 103
 104 #define ICH9_D2P_A2_REVISION                    0x92
 105
 106
 107 /* D31:F1 LPC controller */
 108 #define ICH9_A2_LPC                             "ICH9 A2 LPC"
 109 #define ICH9_A2_LPC_SAVEVM_VERSION              0
 110
 111 #define ICH9_LPC_DEV                            31
 112 #define ICH9_LPC_FUNC                           0
 113
 114 #define ICH9_A2_LPC_REVISION                    0x2
 115 #define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */
 116
 117 #define ICH9_LPC_PMBASE                         0x40
 118 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
 119 #define ICH9_LPC_PMBASE_RTE                     0x1
 120 #define ICH9_LPC_PMBASE_DEFAULT                 0x1
 121 #define ICH9_LPC_ACPI_CTRL                      0x44
 122 #define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
 123 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
 124 #define ICH9_LPC_ACPI_CTRL_9                    0x0
 125 #define ICH9_LPC_ACPI_CTRL_10                   0x1
 126 #define ICH9_LPC_ACPI_CTRL_11                   0x2
 127 #define ICH9_LPC_ACPI_CTRL_20                   0x4
 128 #define ICH9_LPC_ACPI_CTRL_21                   0x5
 129 #define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0
 130
 131 #define ICH9_LPC_PIRQA_ROUT                     0x60
 132 #define ICH9_LPC_PIRQB_ROUT                     0x61
 133 #define ICH9_LPC_PIRQC_ROUT                     0x62
 134 #define ICH9_LPC_PIRQD_ROUT                     0x63
 135
 136 #define ICH9_LPC_PIRQE_ROUT                     0x68
 137 #define ICH9_LPC_PIRQF_ROUT                     0x69
 138 #define ICH9_LPC_PIRQG_ROUT                     0x6a
 139 #define ICH9_LPC_PIRQH_ROUT                     0x6b
 140
 141 #define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
 142 #define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
 143 #define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80
 144
 145 #define ICH9_LPC_RCBA                           0xf0
 146 #define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
 147 #define ICH9_LPC_RCBA_EN                        0x1
 148 #define ICH9_LPC_RCBA_DEFAULT                   0x0
 149
 150 #define ICH9_LPC_PIC_NUM_PINS                   16
 151 #define ICH9_LPC_IOAPIC_NUM_PINS                24
 152
 153 /* D31:F2 SATA Controller #1 */
 154 #define ICH9_SATA1_DEV                          31
 155 #define ICH9_SATA1_FUNC                         2
 156
 157 /* D30:F1 power management I/O registers
 158    offset from the address ICH9_LPC_PMBASE */
 159
 160 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
 161 #define ICH9_PMIO_SIZE                          128
 162 #define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)
 163
 164 #define ICH9_PMIO_PM1_STS                       0x00
 165 #define ICH9_PMIO_PM1_EN                        0x02
 166 #define ICH9_PMIO_PM1_CNT                       0x04
 167 #define ICH9_PMIO_PM1_TMR                       0x08
 168 #define ICH9_PMIO_GPE0_STS                      0x20
 169 #define ICH9_PMIO_GPE0_EN                       0x28
 170 #define ICH9_PMIO_GPE0_LEN                      16
 171 #define ICH9_PMIO_SMI_EN                        0x30
 172 #define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
 173 #define ICH9_PMIO_SMI_STS                       0x34
 174
 175 /* FADT ACPI_ENABLE/ACPI_DISABLE */
 176 #define ICH9_APM_ACPI_ENABLE                    0x2
 177 #define ICH9_APM_ACPI_DISABLE                   0x3
 178
 179
 180 /* D31:F3 SMBus controller */
 181 #define ICH9_A2_SMB_REVISION                    0x02
 182 #define ICH9_SMB_PI                             0x00
 183
 184 #define ICH9_SMB_SMBMBAR0                       0x10
 185 #define ICH9_SMB_SMBMBAR1                       0x14
 186 #define ICH9_SMB_SMBM_BAR                       0
 187 #define ICH9_SMB_SMBM_SIZE                      (1 << 8)
 188 #define ICH9_SMB_SMB_BASE                       0x20
 189 #define ICH9_SMB_SMB_BASE_BAR                   4
 190 #define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
 191 #define ICH9_SMB_HOSTC                          0x40
 192 #define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
 193 #define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
 194 #define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
 195 #define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))
 196
 197 /* D31:F3 SMBus I/O and memory mapped I/O registers */
 198 #define ICH9_SMB_DEV                            31
 199 #define ICH9_SMB_FUNC                           3
 200
 201 #define ICH9_SMB_HST_STS                        0x00
 202 #define ICH9_SMB_HST_CNT                        0x02
 203 #define ICH9_SMB_HST_CMD                        0x03
 204 #define ICH9_SMB_XMIT_SLVA                      0x04
 205 #define ICH9_SMB_HST_D0                         0x05
 206 #define ICH9_SMB_HST_D1                         0x06
 207 #define ICH9_SMB_HOST_BLOCK_DB                  0x07
 208
 209 #endif /* HW_ICH9_H */