4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * lspci dump of a ICH-9 real device in IDE mode (hopefully close enough):
25 * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
26 * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
27 * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
28 * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
30 * Interrupt: pin B routed to IRQ 222
31 * Region 0: I/O ports at d000 [size=8]
32 * Region 1: I/O ports at cc00 [size=4]
33 * Region 2: I/O ports at c880 [size=8]
34 * Region 3: I/O ports at c800 [size=4]
35 * Region 4: I/O ports at c480 [size=32]
36 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
37 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
38 * Address: fee0f00c Data: 41d9
39 * Capabilities: [70] Power Management version 3
40 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
41 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
42 * Capabilities: [a8] SATA HBA <?>
43 * Capabilities: [b0] Vendor Specific Information <?>
44 * Kernel driver in use: ahci
45 * Kernel modules: ahci
46 * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
47 * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
48 * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
49 * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
50 * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
51 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
52 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
53 * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
54 * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
55 * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
56 * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
57 * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
58 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
59 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
61 * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
72 #include "cpu-common.h"
75 #include <hw/ide/pci.h>
77 /* #define DEBUG_AHCI */
80 #define DPRINTF(port, fmt, ...) \
81 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \
82 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
84 #define DPRINTF(port, fmt, ...) do {} while(0)
87 #define AHCI_PCI_BAR 5
88 #define AHCI_MAX_PORTS 32
89 #define AHCI_MAX_SG 168 /* hardware max is 64K */
90 #define AHCI_DMA_BOUNDARY 0xffffffff
91 #define AHCI_USE_CLUSTERING 0
92 #define AHCI_MAX_CMDS 32
93 #define AHCI_CMD_SZ 32
94 #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
95 #define AHCI_RX_FIS_SZ 256
96 #define AHCI_CMD_TBL_CDB 0x40
97 #define AHCI_CMD_TBL_HDR_SZ 0x80
98 #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
99 #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
100 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
103 #define AHCI_IRQ_ON_SG (1 << 31)
104 #define AHCI_CMD_ATAPI (1 << 5)
105 #define AHCI_CMD_WRITE (1 << 6)
106 #define AHCI_CMD_PREFETCH (1 << 7)
107 #define AHCI_CMD_RESET (1 << 8)
108 #define AHCI_CMD_CLR_BUSY (1 << 10)
110 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
111 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
112 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
114 /* global controller registers */
115 #define HOST_CAP 0x00 /* host capabilities */
116 #define HOST_CTL 0x04 /* global host control */
117 #define HOST_IRQ_STAT 0x08 /* interrupt status */
118 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
119 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
122 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
123 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
124 #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
127 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */
128 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */
129 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */
130 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
131 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
132 #define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
134 /* registers for each SATA port */
135 #define PORT_LST_ADDR 0x00 /* command list DMA addr */
136 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
137 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
138 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
139 #define PORT_IRQ_STAT 0x10 /* interrupt status */
140 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
141 #define PORT_CMD 0x18 /* port command */
142 #define PORT_TFDATA 0x20 /* taskfile data */
143 #define PORT_SIG 0x24 /* device TF signature */
144 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
145 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
146 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
147 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
148 #define PORT_CMD_ISSUE 0x38 /* command issue */
149 #define PORT_RESERVED 0x3c /* reserved */
151 /* PORT_IRQ_{STAT,MASK} bits */
152 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
153 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
154 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
155 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
156 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
157 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
158 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
159 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
161 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
162 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
163 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
164 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
165 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
166 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
167 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
168 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
169 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
171 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
172 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
174 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
175 PORT_IRQ_HBUS_DATA_ERR)
176 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
177 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
178 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
181 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
182 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
183 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
184 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
185 #define PORT_CMD_CLO (1 << 3) /* Command list override */
186 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
187 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
188 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
190 #define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
191 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
192 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
193 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
195 #define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */
196 #define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */
197 #define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */
198 #define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */
199 #define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */
200 #define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */
201 #define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */
202 #define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence
204 #define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */
205 #define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier
207 #define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */
208 #define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error
210 #define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */
211 #define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
212 #define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
213 #define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
214 #define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */
217 #define AHCI_FLAG_NO_NCQ (1 << 24)
218 #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
219 #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */
220 #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */
221 #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */
223 #define ATA_SRST (1 << 2) /* software reset */
226 #define STATE_RESET 1
228 #define SATA_SCR_SSTATUS_DET_NODEV 0x0
229 #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
231 #define SATA_SCR_SSTATUS_SPD_NODEV 0x00
232 #define SATA_SCR_SSTATUS_SPD_GEN1 0x10
234 #define SATA_SCR_SSTATUS_IPM_NODEV 0x000
235 #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
237 #define AHCI_SCR_SCTL_DET 0xf
239 #define SATA_FIS_TYPE_REGISTER_H2D 0x27
240 #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
242 #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
243 #define AHCI_CMD_HDR_PRDT_LEN 16
245 #define SATA_SIGNATURE_CDROM 0xeb140000
246 #define SATA_SIGNATURE_DISK 0x00000101
248 #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
249 /* Shouldn't this be 0x2c? */
253 #define AHCI_PORT_REGS_START_ADDR 0x100
254 #define AHCI_PORT_REGS_END_ADDR (AHCI_PORT_REGS_START_ADDR + SATA_PORTS * 0x80)
255 #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
257 #define AHCI_NUM_COMMAND_SLOTS 31
258 #define AHCI_SUPPORTED_SPEED 20
259 #define AHCI_SUPPORTED_SPEED_GEN1 1
260 #define AHCI_VERSION_1_0 0x10000
262 #define AHCI_PROGMODE_MAJOR_REV_1 1
264 #define AHCI_COMMAND_TABLE_ACMD 0x40
266 #define IDE_FEATURE_DMA 1
268 #define READ_FPDMA_QUEUED 0x60
269 #define WRITE_FPDMA_QUEUED 0x61
271 #define RES_FIS_DSFIS 0x00
272 #define RES_FIS_PSFIS 0x20
273 #define RES_FIS_RFIS 0x40
274 #define RES_FIS_SDBFIS 0x58
275 #define RES_FIS_UFIS 0x60
277 typedef struct AHCIControlRegs
{
285 typedef struct AHCIPortRegs
{
287 uint32_t lst_addr_hi
;
289 uint32_t fis_addr_hi
;
304 typedef struct AHCICmdHdr
{
308 uint32_t reserved
[4];
309 } __attribute__ ((packed
)) AHCICmdHdr
;
311 typedef struct AHCI_SG
{
315 } __attribute__ ((packed
)) AHCI_SG
;
317 typedef struct AHCIDevice AHCIDevice
;
319 typedef struct NCQTransferState
{
321 BlockDriverAIOCB
*aiocb
;
324 uint16_t sector_count
;
337 AHCIPortRegs port_regs
;
338 struct AHCIState
*hba
;
343 int done_atapi_packet
;
345 BlockDriverCompletionFunc
*dma_cb
;
347 NCQTransferState ncq_tfs
[AHCI_MAX_CMDS
];
350 typedef struct AHCIState
{
351 AHCIDevice dev
[SATA_PORTS
];
352 AHCIControlRegs control_regs
;
357 typedef struct AHCIPCIState
{
362 typedef struct NCQFrame
{
366 uint8_t sector_count_low
;
374 uint8_t sector_count_high
;
383 } __attribute__ ((packed
)) NCQFrame
;
385 static void check_cmd(AHCIState
*s
, int port
);
386 static int handle_cmd(AHCIState
*s
,int port
,int slot
);
387 static void ahci_reset_port(AHCIState
*s
, int port
);
388 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
);
390 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
394 pr
= &s
->dev
[port
].port_regs
;
400 case PORT_LST_ADDR_HI
:
401 val
= pr
->lst_addr_hi
;
406 case PORT_FIS_ADDR_HI
:
407 val
= pr
->fis_addr_hi
;
419 val
= ((uint16_t)s
->dev
[port
].port
.ifs
[0].error
<< 8) |
420 s
->dev
[port
].port
.ifs
[0].status
;
426 if (s
->dev
[port
].port
.ifs
[0].bs
) {
427 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
428 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
430 val
= SATA_SCR_SSTATUS_DET_NODEV
;
440 pr
->scr_act
&= ~s
->dev
[port
].finished
;
441 s
->dev
[port
].finished
= 0;
451 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
456 static void ahci_irq_raise(AHCIState
*s
, AHCIDevice
*dev
)
458 struct AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
460 DPRINTF(0, "raise irq\n");
462 if (msi_enabled(&d
->card
)) {
463 msi_notify(&d
->card
, 0);
465 qemu_irq_raise(s
->irq
);
469 static void ahci_irq_lower(AHCIState
*s
, AHCIDevice
*dev
)
471 struct AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
473 DPRINTF(0, "lower irq\n");
475 if (!msi_enabled(&d
->card
)) {
476 qemu_irq_lower(s
->irq
);
480 static void ahci_check_irq(AHCIState
*s
)
484 DPRINTF(-1, "check irq %#x\n", s
->control_regs
.irqstatus
);
486 for (i
= 0; i
< SATA_PORTS
; i
++) {
487 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
488 if (pr
->irq_stat
& pr
->irq_mask
) {
489 s
->control_regs
.irqstatus
|= (1 << i
);
493 if (s
->control_regs
.irqstatus
&&
494 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
495 ahci_irq_raise(s
, NULL
);
497 ahci_irq_lower(s
, NULL
);
501 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
504 DPRINTF(d
->port_no
, "trigger irq %#x -> %x\n",
505 irq_type
, d
->port_regs
.irq_mask
& irq_type
);
507 d
->port_regs
.irq_stat
|= irq_type
;
511 static void map_page(uint8_t **ptr
, uint64_t addr
, uint32_t wanted
)
513 target_phys_addr_t len
= wanted
;
516 cpu_physical_memory_unmap(*ptr
, 1, len
, len
);
519 *ptr
= cpu_physical_memory_map(addr
, &len
, 1);
521 cpu_physical_memory_unmap(*ptr
, 1, len
, len
);
526 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
528 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
530 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
534 map_page(&s
->dev
[port
].lst
,
535 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
536 s
->dev
[port
].cur_cmd
= NULL
;
538 case PORT_LST_ADDR_HI
:
539 pr
->lst_addr_hi
= val
;
540 map_page(&s
->dev
[port
].lst
,
541 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
542 s
->dev
[port
].cur_cmd
= NULL
;
546 map_page(&s
->dev
[port
].res_fis
,
547 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
549 case PORT_FIS_ADDR_HI
:
550 pr
->fis_addr_hi
= val
;
551 map_page(&s
->dev
[port
].res_fis
,
552 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
555 pr
->irq_stat
&= ~val
;
558 pr
->irq_mask
= val
& 0xfdc000ff;
562 pr
->cmd
= val
& ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
564 if (pr
->cmd
& PORT_CMD_START
) {
565 pr
->cmd
|= PORT_CMD_LIST_ON
;
568 if (pr
->cmd
& PORT_CMD_FIS_RX
) {
569 pr
->cmd
|= PORT_CMD_FIS_ON
;
575 s
->dev
[port
].port
.ifs
[0].error
= (val
>> 8) & 0xff;
576 s
->dev
[port
].port
.ifs
[0].status
= val
& 0xff;
585 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
586 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
587 ahci_reset_port(s
, port
);
599 pr
->cmd_issue
|= val
;
607 static uint32_t ahci_mem_readl(void *ptr
, target_phys_addr_t addr
)
613 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
616 val
= s
->control_regs
.cap
;
619 val
= s
->control_regs
.ghc
;
622 val
= s
->control_regs
.irqstatus
;
624 case HOST_PORTS_IMPL
:
625 val
= s
->control_regs
.impl
;
628 val
= s
->control_regs
.version
;
632 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr
, val
);
633 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
634 (addr
< AHCI_PORT_REGS_END_ADDR
)) {
635 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
636 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
644 static void ahci_mem_writel(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
649 /* Only aligned reads are allowed on AHCI */
651 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
652 TARGET_FMT_plx
"\n", addr
);
656 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
657 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr
, val
);
660 case HOST_CAP
: /* R/WO, RO */
661 /* FIXME handle R/WO */
663 case HOST_CTL
: /* R/W */
664 if (val
& HOST_CTL_RESET
) {
665 DPRINTF(-1, "HBA Reset\n");
668 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
672 case HOST_IRQ_STAT
: /* R/WC, RO */
673 s
->control_regs
.irqstatus
&= ~val
;
676 case HOST_PORTS_IMPL
: /* R/WO, RO */
677 /* FIXME handle R/WO */
679 case HOST_VERSION
: /* RO */
680 /* FIXME report write? */
683 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr
);
685 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
686 (addr
< AHCI_PORT_REGS_END_ADDR
)) {
687 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
688 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
693 static CPUReadMemoryFunc
* const ahci_readfn
[3]={
699 static CPUWriteMemoryFunc
* const ahci_writefn
[3]={
705 static void ahci_reg_init(AHCIState
*s
)
709 s
->control_regs
.cap
= (SATA_PORTS
- 1) |
710 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
711 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
712 HOST_CAP_NCQ
| HOST_CAP_AHCI
;
714 s
->control_regs
.impl
= (1 << SATA_PORTS
) - 1;
716 s
->control_regs
.version
= AHCI_VERSION_1_0
;
718 for (i
= 0; i
< SATA_PORTS
; i
++) {
719 s
->dev
[i
].port_state
= STATE_RUN
;
723 static uint32_t read_from_sglist(uint8_t *buffer
, uint32_t len
,
727 uint32_t total
= 0, once
;
728 ScatterGatherEntry
*cur_prd
;
731 cur_prd
= sglist
->sg
;
732 sgcount
= sglist
->nsg
;
733 for (i
= 0; len
&& sgcount
; i
++) {
734 once
= MIN(cur_prd
->len
, len
);
735 cpu_physical_memory_read(cur_prd
->base
, buffer
, once
);
746 static uint32_t write_to_sglist(uint8_t *buffer
, uint32_t len
,
750 uint32_t total
= 0, once
;
751 ScatterGatherEntry
*cur_prd
;
754 DPRINTF(-1, "total: 0x%x bytes\n", len
);
756 cur_prd
= sglist
->sg
;
757 sgcount
= sglist
->nsg
;
758 for (i
= 0; len
&& sgcount
; i
++) {
759 once
= MIN(cur_prd
->len
, len
);
760 DPRINTF(-1, "write 0x%x bytes to 0x%lx\n", once
, (long)cur_prd
->base
);
761 cpu_physical_memory_write(cur_prd
->base
, buffer
, once
);
772 static void check_cmd(AHCIState
*s
, int port
)
774 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
777 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
778 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
779 if ((pr
->cmd_issue
& (1 << slot
)) &&
780 !handle_cmd(s
, port
, slot
)) {
781 pr
->cmd_issue
&= ~(1 << slot
);
787 static void ahci_check_cmd_bh(void *opaque
)
789 AHCIDevice
*ad
= opaque
;
791 qemu_bh_delete(ad
->check_bh
);
794 if ((ad
->busy_slot
!= -1) &&
795 !(ad
->port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
))) {
797 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
801 check_cmd(ad
->hba
, ad
->port_no
);
804 static void ahci_reset_port(AHCIState
*s
, int port
)
806 AHCIDevice
*d
= &s
->dev
[port
];
807 AHCIPortRegs
*pr
= &d
->port_regs
;
808 IDEState
*ide_state
= &d
->port
.ifs
[0];
809 uint8_t init_fis
[0x20];
812 DPRINTF(port
, "reset port\n");
814 ide_bus_reset(&d
->port
);
815 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
825 ide_state
= &s
->dev
[port
].port
.ifs
[0];
826 if (!ide_state
->bs
) {
830 /* reset ncq queue */
831 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
832 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
833 if (!ncq_tfs
->used
) {
837 if (ncq_tfs
->aiocb
) {
838 bdrv_aio_cancel(ncq_tfs
->aiocb
);
839 ncq_tfs
->aiocb
= NULL
;
842 qemu_sglist_destroy(&ncq_tfs
->sglist
);
846 memset(init_fis
, 0, sizeof(init_fis
));
847 s
->dev
[port
].port_state
= STATE_RUN
;
848 if (!ide_state
->bs
) {
849 s
->dev
[port
].port_regs
.sig
= 0;
850 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
851 } else if (ide_state
->drive_kind
== IDE_CD
) {
852 s
->dev
[port
].port_regs
.sig
= SATA_SIGNATURE_CDROM
;
853 ide_state
->lcyl
= 0x14;
854 ide_state
->hcyl
= 0xeb;
855 DPRINTF(port
, "set lcyl = %d\n", ide_state
->lcyl
);
856 init_fis
[5] = ide_state
->lcyl
;
857 init_fis
[6] = ide_state
->hcyl
;
858 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
860 s
->dev
[port
].port_regs
.sig
= SATA_SIGNATURE_DISK
;
861 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
864 ide_state
->error
= 1;
867 ahci_write_fis_d2h(d
, init_fis
);
870 static void debug_print_fis(uint8_t *fis
, int cmd_len
)
875 fprintf(stderr
, "fis:");
876 for (i
= 0; i
< cmd_len
; i
++) {
877 if ((i
& 0xf) == 0) {
878 fprintf(stderr
, "\n%02x:",i
);
880 fprintf(stderr
, "%02x ",fis
[i
]);
882 fprintf(stderr
, "\n");
886 static void ahci_write_fis_sdb(AHCIState
*s
, int port
, uint32_t finished
)
888 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
892 if (!s
->dev
[port
].res_fis
||
893 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
897 sdb_fis
= &s
->dev
[port
].res_fis
[RES_FIS_SDBFIS
];
898 ide_state
= &s
->dev
[port
].port
.ifs
[0];
901 *(uint32_t*)sdb_fis
= 0;
904 sdb_fis
[0] = ide_state
->error
;
905 sdb_fis
[2] = ide_state
->status
& 0x77;
906 s
->dev
[port
].finished
|= finished
;
907 *(uint32_t*)(sdb_fis
+ 4) = cpu_to_le32(s
->dev
[port
].finished
);
909 ahci_trigger_irq(s
, &s
->dev
[port
], PORT_IRQ_STAT_SDBS
);
912 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
)
914 AHCIPortRegs
*pr
= &ad
->port_regs
;
917 target_phys_addr_t cmd_len
= 0x80;
920 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
926 uint64_t tbl_addr
= le64_to_cpu(ad
->cur_cmd
->tbl_addr
);
927 cmd_fis
= cpu_physical_memory_map(tbl_addr
, &cmd_len
, 0);
931 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
934 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
935 d2h_fis
[2] = ad
->port
.ifs
[0].status
;
936 d2h_fis
[3] = ad
->port
.ifs
[0].error
;
938 d2h_fis
[4] = cmd_fis
[4];
939 d2h_fis
[5] = cmd_fis
[5];
940 d2h_fis
[6] = cmd_fis
[6];
941 d2h_fis
[7] = cmd_fis
[7];
942 d2h_fis
[8] = cmd_fis
[8];
943 d2h_fis
[9] = cmd_fis
[9];
944 d2h_fis
[10] = cmd_fis
[10];
945 d2h_fis
[11] = cmd_fis
[11];
946 d2h_fis
[12] = cmd_fis
[12];
947 d2h_fis
[13] = cmd_fis
[13];
948 for (i
= 14; i
< 0x20; i
++) {
952 if (d2h_fis
[2] & ERR_STAT
) {
953 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_TFES
);
956 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_D2H_REG_FIS
);
959 cpu_physical_memory_unmap(cmd_fis
, 0, cmd_len
, cmd_len
);
963 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
)
965 AHCICmdHdr
*cmd
= ad
->cur_cmd
;
966 uint32_t opts
= le32_to_cpu(cmd
->opts
);
967 uint64_t prdt_addr
= le64_to_cpu(cmd
->tbl_addr
) + 0x80;
968 int sglist_alloc_hint
= opts
>> AHCI_CMD_HDR_PRDT_LEN
;
969 target_phys_addr_t prdt_len
= (sglist_alloc_hint
* sizeof(AHCI_SG
));
970 target_phys_addr_t real_prdt_len
= prdt_len
;
975 if (!sglist_alloc_hint
) {
976 DPRINTF(ad
->port_no
, "no sg list given by guest: 0x%08x\n", opts
);
981 if (!(prdt
= cpu_physical_memory_map(prdt_addr
, &prdt_len
, 0))){
982 DPRINTF(ad
->port_no
, "map failed\n");
986 if (prdt_len
< real_prdt_len
) {
987 DPRINTF(ad
->port_no
, "mapped less than expected\n");
992 /* Get entries in the PRDT, init a qemu sglist accordingly */
993 if (sglist_alloc_hint
> 0) {
994 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
996 qemu_sglist_init(sglist
, sglist_alloc_hint
);
997 for (i
= 0; i
< sglist_alloc_hint
; i
++) {
998 /* flags_size is zero-based */
999 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
1000 le32_to_cpu(tbl
[i
].flags_size
) + 1);
1005 cpu_physical_memory_unmap(prdt
, 0, prdt_len
, prdt_len
);
1009 static void ncq_cb(void *opaque
, int ret
)
1011 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
1012 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
1014 /* Clear bit for this tag in SActive */
1015 ncq_tfs
->drive
->port_regs
.scr_act
&= ~(1 << ncq_tfs
->tag
);
1019 ide_state
->error
= ABRT_ERR
;
1020 ide_state
->status
= READY_STAT
| ERR_STAT
;
1021 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
1023 ide_state
->status
= READY_STAT
| SEEK_STAT
;
1026 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
1027 (1 << ncq_tfs
->tag
));
1029 DPRINTF(ncq_tfs
->drive
->port_no
, "NCQ transfer tag %d finished\n",
1032 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1036 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1039 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1040 uint8_t tag
= ncq_fis
->tag
>> 3;
1041 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[tag
];
1043 if (ncq_tfs
->used
) {
1044 /* error - already in use */
1045 fprintf(stderr
, "%s: tag %d already used\n", __FUNCTION__
, tag
);
1050 ncq_tfs
->drive
= &s
->dev
[port
];
1051 ncq_tfs
->slot
= slot
;
1052 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1053 ((uint64_t)ncq_fis
->lba4
<< 32) |
1054 ((uint64_t)ncq_fis
->lba3
<< 24) |
1055 ((uint64_t)ncq_fis
->lba2
<< 16) |
1056 ((uint64_t)ncq_fis
->lba1
<< 8) |
1057 (uint64_t)ncq_fis
->lba0
;
1059 /* Note: We calculate the sector count, but don't currently rely on it.
1060 * The total size of the DMA buffer tells us the transfer size instead. */
1061 ncq_tfs
->sector_count
= ((uint16_t)ncq_fis
->sector_count_high
<< 8) |
1062 ncq_fis
->sector_count_low
;
1064 DPRINTF(port
, "NCQ transfer LBA from %ld to %ld, drive max %ld\n",
1065 ncq_tfs
->lba
, ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 2,
1066 s
->dev
[port
].port
.ifs
[0].nb_sectors
- 1);
1068 ahci_populate_sglist(&s
->dev
[port
], &ncq_tfs
->sglist
);
1071 switch(ncq_fis
->command
) {
1072 case READ_FPDMA_QUEUED
:
1073 DPRINTF(port
, "NCQ reading %d sectors from LBA %ld, tag %d\n",
1074 ncq_tfs
->sector_count
-1, ncq_tfs
->lba
, ncq_tfs
->tag
);
1075 ncq_tfs
->is_read
= 1;
1077 DPRINTF(port
, "tag %d aio read %ld\n", ncq_tfs
->tag
, ncq_tfs
->lba
);
1078 ncq_tfs
->aiocb
= dma_bdrv_read(ncq_tfs
->drive
->port
.ifs
[0].bs
,
1079 &ncq_tfs
->sglist
, ncq_tfs
->lba
,
1082 case WRITE_FPDMA_QUEUED
:
1083 DPRINTF(port
, "NCQ writing %d sectors to LBA %ld, tag %d\n",
1084 ncq_tfs
->sector_count
-1, ncq_tfs
->lba
, ncq_tfs
->tag
);
1085 ncq_tfs
->is_read
= 0;
1087 DPRINTF(port
, "tag %d aio write %ld\n", ncq_tfs
->tag
, ncq_tfs
->lba
);
1088 ncq_tfs
->aiocb
= dma_bdrv_write(ncq_tfs
->drive
->port
.ifs
[0].bs
,
1089 &ncq_tfs
->sglist
, ncq_tfs
->lba
,
1093 DPRINTF(port
, "error: tried to process non-NCQ command as NCQ\n");
1094 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1099 static int handle_cmd(AHCIState
*s
, int port
, int slot
)
1101 IDEState
*ide_state
;
1106 target_phys_addr_t cmd_len
;
1108 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1109 /* Engine currently busy, try again later */
1110 DPRINTF(port
, "engine busy\n");
1114 cmd
= &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
];
1116 if (!s
->dev
[port
].lst
) {
1117 DPRINTF(port
, "error: lst not given but cmd handled");
1121 /* remember current slot handle for later */
1122 s
->dev
[port
].cur_cmd
= cmd
;
1124 opts
= le32_to_cpu(cmd
->opts
);
1125 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1128 cmd_fis
= cpu_physical_memory_map(tbl_addr
, &cmd_len
, 1);
1131 DPRINTF(port
, "error: guest passed us an invalid cmd fis\n");
1135 /* The device we are working for */
1136 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1138 if (!ide_state
->bs
) {
1139 DPRINTF(port
, "error: guest accessed unused port");
1143 debug_print_fis(cmd_fis
, 0x90);
1144 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4);
1146 switch (cmd_fis
[0]) {
1147 case SATA_FIS_TYPE_REGISTER_H2D
:
1150 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
1151 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
1157 switch (cmd_fis
[1]) {
1158 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
:
1163 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
1164 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
1170 switch (s
->dev
[port
].port_state
) {
1172 if (cmd_fis
[15] & ATA_SRST
) {
1173 s
->dev
[port
].port_state
= STATE_RESET
;
1177 if (!(cmd_fis
[15] & ATA_SRST
)) {
1178 ahci_reset_port(s
, port
);
1183 if (cmd_fis
[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
) {
1185 /* Check for NCQ command */
1186 if ((cmd_fis
[2] == READ_FPDMA_QUEUED
) ||
1187 (cmd_fis
[2] == WRITE_FPDMA_QUEUED
)) {
1188 process_ncq_command(s
, port
, cmd_fis
, slot
);
1192 /* Decompose the FIS */
1193 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1194 ide_state
->feature
= cmd_fis
[3];
1195 if (!ide_state
->nsector
) {
1196 ide_state
->nsector
= 256;
1199 if (ide_state
->drive_kind
!= IDE_CD
) {
1200 ide_set_sector(ide_state
, (cmd_fis
[6] << 16) | (cmd_fis
[5] << 8) |
1204 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1205 * table to ide_state->io_buffer
1207 if (opts
& AHCI_CMD_ATAPI
) {
1208 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1209 ide_state
->lcyl
= 0x14;
1210 ide_state
->hcyl
= 0xeb;
1211 debug_print_fis(ide_state
->io_buffer
, 0x10);
1212 ide_state
->feature
= IDE_FEATURE_DMA
;
1213 s
->dev
[port
].done_atapi_packet
= 0;
1214 /* XXX send PIO setup FIS */
1217 ide_state
->error
= 0;
1219 /* Reset transferred byte counter */
1222 /* We're ready to process the command in FIS byte 2. */
1223 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1225 if (s
->dev
[port
].port
.ifs
[0].status
& READY_STAT
) {
1226 ahci_write_fis_d2h(&s
->dev
[port
], cmd_fis
);
1231 cpu_physical_memory_unmap(cmd_fis
, 1, cmd_len
, cmd_len
);
1233 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1234 /* async command, complete later */
1235 s
->dev
[port
].busy_slot
= slot
;
1239 /* done handling the command */
1243 /* DMA dev <-> ram */
1244 static int ahci_start_transfer(IDEDMA
*dma
)
1246 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1247 IDEState
*s
= &ad
->port
.ifs
[0];
1248 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1249 /* write == ram -> device */
1250 uint32_t opts
= le32_to_cpu(ad
->cur_cmd
->opts
);
1251 int is_write
= opts
& AHCI_CMD_WRITE
;
1252 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1255 if (is_atapi
&& !ad
->done_atapi_packet
) {
1256 /* already prepopulated iobuffer */
1257 ad
->done_atapi_packet
= 1;
1261 if (!ahci_populate_sglist(ad
, &s
->sg
)) {
1265 DPRINTF(ad
->port_no
, "%sing %d bytes on %s w/%s sglist\n",
1266 is_write
? "writ" : "read", size
, is_atapi
? "atapi" : "ata",
1267 has_sglist
? "" : "o");
1269 if (is_write
&& has_sglist
&& (s
->data_ptr
< s
->data_end
)) {
1270 read_from_sglist(s
->data_ptr
, size
, &s
->sg
);
1273 if (!is_write
&& has_sglist
&& (s
->data_ptr
< s
->data_end
)) {
1274 write_to_sglist(s
->data_ptr
, size
, &s
->sg
);
1277 /* update number of transferred bytes */
1278 ad
->cur_cmd
->status
= cpu_to_le32(le32_to_cpu(ad
->cur_cmd
->status
) + size
);
1281 /* declare that we processed everything */
1282 s
->data_ptr
= s
->data_end
;
1285 qemu_sglist_destroy(&s
->sg
);
1288 s
->end_transfer_func(s
);
1290 if (!(s
->status
& DRQ_STAT
)) {
1292 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_DSS
);
1298 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1299 BlockDriverCompletionFunc
*dma_cb
)
1301 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1303 DPRINTF(ad
->port_no
, "\n");
1304 ad
->dma_cb
= dma_cb
;
1305 ad
->dma_status
|= BM_STATUS_DMAING
;
1309 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int is_write
)
1311 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1312 IDEState
*s
= &ad
->port
.ifs
[0];
1315 ahci_populate_sglist(ad
, &s
->sg
);
1317 s
->io_buffer_size
= 0;
1318 for (i
= 0; i
< s
->sg
.nsg
; i
++) {
1319 s
->io_buffer_size
+= s
->sg
.sg
[i
].len
;
1322 DPRINTF(ad
->port_no
, "len=%#x\n", s
->io_buffer_size
);
1323 return s
->io_buffer_size
!= 0;
1326 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1328 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1329 IDEState
*s
= &ad
->port
.ifs
[0];
1330 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1331 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1333 if (ahci_populate_sglist(ad
, &s
->sg
)) {
1338 write_to_sglist(p
, l
, &s
->sg
);
1340 read_from_sglist(p
, l
, &s
->sg
);
1343 /* update number of transferred bytes */
1344 ad
->cur_cmd
->status
= cpu_to_le32(le32_to_cpu(ad
->cur_cmd
->status
) + l
);
1345 s
->io_buffer_index
+= l
;
1347 DPRINTF(ad
->port_no
, "len=%#x\n", l
);
1352 static int ahci_dma_set_unit(IDEDMA
*dma
, int unit
)
1354 /* only a single unit per link */
1358 static int ahci_dma_add_status(IDEDMA
*dma
, int status
)
1360 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1361 ad
->dma_status
|= status
;
1362 DPRINTF(ad
->port_no
, "set status: %x\n", status
);
1364 if (status
& BM_STATUS_INT
) {
1365 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_DSS
);
1371 static int ahci_dma_set_inactive(IDEDMA
*dma
)
1373 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1375 DPRINTF(ad
->port_no
, "dma done\n");
1377 /* update d2h status */
1378 ahci_write_fis_d2h(ad
, NULL
);
1382 /* maybe we still have something to process, check later */
1383 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1384 qemu_bh_schedule(ad
->check_bh
);
1389 static void ahci_irq_set(void *opaque
, int n
, int level
)
1393 static void ahci_dma_restart_cb(void *opaque
, int running
, int reason
)
1397 static int ahci_dma_reset(IDEDMA
*dma
)
1402 static const IDEDMAOps ahci_dma_ops
= {
1403 .start_dma
= ahci_start_dma
,
1404 .start_transfer
= ahci_start_transfer
,
1405 .prepare_buf
= ahci_dma_prepare_buf
,
1406 .rw_buf
= ahci_dma_rw_buf
,
1407 .set_unit
= ahci_dma_set_unit
,
1408 .add_status
= ahci_dma_add_status
,
1409 .set_inactive
= ahci_dma_set_inactive
,
1410 .restart_cb
= ahci_dma_restart_cb
,
1411 .reset
= ahci_dma_reset
,
1414 static void ahci_init(AHCIState
*s
, DeviceState
*qdev
)
1420 s
->mem
= cpu_register_io_memory(ahci_readfn
, ahci_writefn
, s
,
1421 DEVICE_LITTLE_ENDIAN
);
1422 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, SATA_PORTS
);
1424 for (i
= 0; i
< SATA_PORTS
; i
++) {
1425 AHCIDevice
*ad
= &s
->dev
[i
];
1427 ide_bus_new(&ad
->port
, qdev
, i
);
1428 ide_init2(&ad
->port
, irqs
[i
]);
1432 ad
->port
.dma
= &ad
->dma
;
1433 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1434 ad
->port_regs
.cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1438 static void ahci_pci_map(PCIDevice
*pci_dev
, int region_num
,
1439 pcibus_t addr
, pcibus_t size
, int type
)
1441 struct AHCIPCIState
*d
= (struct AHCIPCIState
*)pci_dev
;
1442 AHCIState
*s
= &d
->ahci
;
1444 cpu_register_physical_memory(addr
, size
, s
->mem
);
1447 static void ahci_reset(void *opaque
)
1449 struct AHCIPCIState
*d
= opaque
;
1452 for (i
= 0; i
< SATA_PORTS
; i
++) {
1453 ahci_reset_port(&d
->ahci
, i
);
1457 static int pci_ahci_init(PCIDevice
*dev
)
1459 struct AHCIPCIState
*d
;
1460 d
= DO_UPCAST(struct AHCIPCIState
, card
, dev
);
1462 pci_config_set_vendor_id(d
->card
.config
, PCI_VENDOR_ID_INTEL
);
1463 pci_config_set_device_id(d
->card
.config
, PCI_DEVICE_ID_INTEL_82801IR
);
1465 pci_config_set_class(d
->card
.config
, PCI_CLASS_STORAGE_SATA
);
1466 pci_config_set_revision(d
->card
.config
, 0x02);
1467 pci_config_set_prog_interface(d
->card
.config
, AHCI_PROGMODE_MAJOR_REV_1
);
1469 d
->card
.config
[PCI_CACHE_LINE_SIZE
] = 0x08; /* Cache line size */
1470 d
->card
.config
[PCI_LATENCY_TIMER
] = 0x00; /* Latency timer */
1471 pci_config_set_interrupt_pin(d
->card
.config
, 1);
1473 /* XXX Software should program this register */
1474 d
->card
.config
[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
1476 qemu_register_reset(ahci_reset
, d
);
1478 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1479 pci_register_bar(&d
->card
, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1482 msi_init(dev
, 0x50, 1, true, false);
1484 ahci_init(&d
->ahci
, &dev
->qdev
);
1485 d
->ahci
.irq
= d
->card
.irq
[0];
1490 static int pci_ahci_uninit(PCIDevice
*dev
)
1492 struct AHCIPCIState
*d
;
1493 d
= DO_UPCAST(struct AHCIPCIState
, card
, dev
);
1495 if (msi_enabled(dev
)) {
1499 qemu_unregister_reset(ahci_reset
, d
);
1504 static void pci_ahci_write_config(PCIDevice
*pci
, uint32_t addr
,
1505 uint32_t val
, int len
)
1507 pci_default_write_config(pci
, addr
, val
, len
);
1508 msi_write_config(pci
, addr
, val
, len
);
1511 static PCIDeviceInfo ahci_info
= {
1512 .qdev
.name
= "ahci",
1513 .qdev
.size
= sizeof(AHCIPCIState
),
1514 .init
= pci_ahci_init
,
1515 .exit
= pci_ahci_uninit
,
1516 .config_write
= pci_ahci_write_config
,
1519 static void ahci_pci_register_devices(void)
1521 pci_qdev_register(&ahci_info
);
1524 device_init(ahci_pci_register_devices
)