hw/ide/cmd646.c

   1 /*
   2  * QEMU IDE Emulation: PCI cmd646 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/isa/isa.h>
  29 #include "block/block.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/dma.h"
  32
  33 #include <hw/ide/pci.h>
  34
  35 /* CMD646 specific */
  36 #define MRDMODE         0x71
  37 #define   MRDMODE_INTR_CH0      0x04
  38 #define   MRDMODE_INTR_CH1      0x08
  39 #define   MRDMODE_BLK_CH0       0x10
  40 #define   MRDMODE_BLK_CH1       0x20
  41 #define UDIDETCR0       0x73
  42 #define UDIDETCR1       0x7B
  43
  44 static void cmd646_update_irq(PCIIDEState *d);
  45
  46 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
  47                                 unsigned size)
  48 {
  49     CMD646BAR *cmd646bar = opaque;
  50
  51     if (addr != 2 || size != 1) {
  52         return ((uint64_t)1 << (size * 8)) - 1;
  53     }
  54     return ide_status_read(cmd646bar->bus, addr + 2);
  55 }
  56
  57 static void cmd646_cmd_write(void *opaque, hwaddr addr,
  58                              uint64_t data, unsigned size)
  59 {
  60     CMD646BAR *cmd646bar = opaque;
  61
  62     if (addr != 2 || size != 1) {
  63         return;
  64     }
  65     ide_cmd_write(cmd646bar->bus, addr + 2, data);
  66 }
  67
  68 static const MemoryRegionOps cmd646_cmd_ops = {
  69     .read = cmd646_cmd_read,
  70     .write = cmd646_cmd_write,
  71     .endianness = DEVICE_LITTLE_ENDIAN,
  72 };
  73
  74 static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
  75                                  unsigned size)
  76 {
  77     CMD646BAR *cmd646bar = opaque;
  78
  79     if (size == 1) {
  80         return ide_ioport_read(cmd646bar->bus, addr);
  81     } else if (addr == 0) {
  82         if (size == 2) {
  83             return ide_data_readw(cmd646bar->bus, addr);
  84         } else {
  85             return ide_data_readl(cmd646bar->bus, addr);
  86         }
  87     }
  88     return ((uint64_t)1 << (size * 8)) - 1;
  89 }
  90
  91 static void cmd646_data_write(void *opaque, hwaddr addr,
  92                              uint64_t data, unsigned size)
  93 {
  94     CMD646BAR *cmd646bar = opaque;
  95
  96     if (size == 1) {
  97         ide_ioport_write(cmd646bar->bus, addr, data);
  98     } else if (addr == 0) {
  99         if (size == 2) {
 100             ide_data_writew(cmd646bar->bus, addr, data);
 101         } else {
 102             ide_data_writel(cmd646bar->bus, addr, data);
 103         }
 104     }
 105 }
 106
 107 static const MemoryRegionOps cmd646_data_ops = {
 108     .read = cmd646_data_read,
 109     .write = cmd646_data_write,
 110     .endianness = DEVICE_LITTLE_ENDIAN,
 111 };
 112
 113 static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
 114 {
 115     IDEBus *bus = &d->bus[bus_num];
 116     CMD646BAR *bar = &d->cmd646_bar[bus_num];
 117
 118     bar->bus = bus;
 119     bar->pci_dev = d;
 120     memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
 121                           "cmd646-cmd", 4);
 122     memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
 123                           "cmd646-data", 8);
 124 }
 125
 126 static uint64_t bmdma_read(void *opaque, hwaddr addr,
 127                            unsigned size)
 128 {
 129     BMDMAState *bm = opaque;
 130     PCIIDEState *pci_dev = bm->pci_dev;
 131     uint32_t val;
 132
 133     if (size != 1) {
 134         return ((uint64_t)1 << (size * 8)) - 1;
 135     }
 136
 137     switch(addr & 3) {
 138     case 0:
 139         val = bm->cmd;
 140         break;
 141     case 1:
 142         val = pci_dev->dev.config[MRDMODE];
 143         break;
 144     case 2:
 145         val = bm->status;
 146         break;
 147     case 3:
 148         if (bm == &pci_dev->bmdma[0]) {
 149             val = pci_dev->dev.config[UDIDETCR0];
 150         } else {
 151             val = pci_dev->dev.config[UDIDETCR1];
 152         }
 153         break;
 154     default:
 155         val = 0xff;
 156         break;
 157     }
 158 #ifdef DEBUG_IDE
 159     printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
 160 #endif
 161     return val;
 162 }
 163
 164 static void bmdma_write(void *opaque, hwaddr addr,
 165                         uint64_t val, unsigned size)
 166 {
 167     BMDMAState *bm = opaque;
 168     PCIIDEState *pci_dev = bm->pci_dev;
 169
 170     if (size != 1) {
 171         return;
 172     }
 173
 174 #ifdef DEBUG_IDE
 175     printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
 176 #endif
 177     switch(addr & 3) {
 178     case 0:
 179         bmdma_cmd_writeb(bm, val);
 180         break;
 181     case 1:
 182         pci_dev->dev.config[MRDMODE] =
 183             (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
 184         cmd646_update_irq(pci_dev);
 185         break;
 186     case 2:
 187         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
 188         break;
 189     case 3:
 190         if (bm == &pci_dev->bmdma[0])
 191             pci_dev->dev.config[UDIDETCR0] = val;
 192         else
 193             pci_dev->dev.config[UDIDETCR1] = val;
 194         break;
 195     }
 196 }
 197
 198 static const MemoryRegionOps cmd646_bmdma_ops = {
 199     .read = bmdma_read,
 200     .write = bmdma_write,
 201 };
 202
 203 static void bmdma_setup_bar(PCIIDEState *d)
 204 {
 205     BMDMAState *bm;
 206     int i;
 207
 208     memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
 209     for(i = 0;i < 2; i++) {
 210         bm = &d->bmdma[i];
 211         memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
 212                               "cmd646-bmdma-bus", 4);
 213         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 214         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 215                               &bmdma_addr_ioport_ops, bm,
 216                               "cmd646-bmdma-ioport", 4);
 217         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 218     }
 219 }
 220
 221 /* XXX: call it also when the MRDMODE is changed from the PCI config
 222    registers */
 223 static void cmd646_update_irq(PCIIDEState *d)
 224 {
 225     int pci_level;
 226     pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
 227                  !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
 228         ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
 229          !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
 230     qemu_set_irq(d->dev.irq[0], pci_level);
 231 }
 232
 233 /* the PCI irq level is the logical OR of the two channels */
 234 static void cmd646_set_irq(void *opaque, int channel, int level)
 235 {
 236     PCIIDEState *d = opaque;
 237     int irq_mask;
 238
 239     irq_mask = MRDMODE_INTR_CH0 << channel;
 240     if (level)
 241         d->dev.config[MRDMODE] |= irq_mask;
 242     else
 243         d->dev.config[MRDMODE] &= ~irq_mask;
 244     cmd646_update_irq(d);
 245 }
 246
 247 static void cmd646_reset(void *opaque)
 248 {
 249     PCIIDEState *d = opaque;
 250     unsigned int i;
 251
 252     for (i = 0; i < 2; i++) {
 253         ide_bus_reset(&d->bus[i]);
 254     }
 255 }
 256
 257 /* CMD646 PCI IDE controller */
 258 static int pci_cmd646_ide_initfn(PCIDevice *dev)
 259 {
 260     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
 261     uint8_t *pci_conf = d->dev.config;
 262     qemu_irq *irq;
 263     int i;
 264
 265     pci_conf[PCI_CLASS_PROG] = 0x8f;
 266
 267     pci_conf[0x51] = 0x04; // enable IDE0
 268     if (d->secondary) {
 269         /* XXX: if not enabled, really disable the seconday IDE controller */
 270         pci_conf[0x51] |= 0x08; /* enable IDE1 */
 271     }
 272
 273     setup_cmd646_bar(d, 0);
 274     setup_cmd646_bar(d, 1);
 275     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
 276     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
 277     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
 278     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
 279     bmdma_setup_bar(d);
 280     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 281
 282     /* TODO: RST# value should be 0 */
 283     pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
 284
 285     irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
 286     for (i = 0; i < 2; i++) {
 287         ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
 288         ide_init2(&d->bus[i], irq[i]);
 289
 290         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 291         d->bmdma[i].bus = &d->bus[i];
 292         qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
 293                                          &d->bmdma[i].dma);
 294     }
 295
 296     vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
 297     qemu_register_reset(cmd646_reset, d);
 298     return 0;
 299 }
 300
 301 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
 302 {
 303     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
 304     unsigned i;
 305
 306     for (i = 0; i < 2; ++i) {
 307         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 308         memory_region_destroy(&d->bmdma[i].extra_io);
 309         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 310         memory_region_destroy(&d->bmdma[i].addr_ioport);
 311         memory_region_destroy(&d->cmd646_bar[i].cmd);
 312         memory_region_destroy(&d->cmd646_bar[i].data);
 313     }
 314     memory_region_destroy(&d->bmdma_bar);
 315 }
 316
 317 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
 318                          int secondary_ide_enabled)
 319 {
 320     PCIDevice *dev;
 321
 322     dev = pci_create(bus, -1, "cmd646-ide");
 323     qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
 324     qdev_init_nofail(&dev->qdev);
 325
 326     pci_ide_create_devs(dev, hd_table);
 327 }
 328
 329 static Property cmd646_ide_properties[] = {
 330     DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
 331     DEFINE_PROP_END_OF_LIST(),
 332 };
 333
 334 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
 335 {
 336     DeviceClass *dc = DEVICE_CLASS(klass);
 337     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 338
 339     k->init = pci_cmd646_ide_initfn;
 340     k->exit = pci_cmd646_ide_exitfn;
 341     k->vendor_id = PCI_VENDOR_ID_CMD;
 342     k->device_id = PCI_DEVICE_ID_CMD_646;
 343     k->revision = 0x07;
 344     k->class_id = PCI_CLASS_STORAGE_IDE;
 345     dc->props = cmd646_ide_properties;
 346 }
 347
 348 static const TypeInfo cmd646_ide_info = {
 349     .name          = "cmd646-ide",
 350     .parent        = TYPE_PCI_DEVICE,
 351     .instance_size = sizeof(PCIIDEState),
 352     .class_init    = cmd646_ide_class_init,
 353 };
 354
 355 static void cmd646_ide_register_types(void)
 356 {
 357     type_register_static(&cmd646_ide_info);
 358 }
 359
 360 type_init(cmd646_ide_register_types)