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[mirror_qemu.git] / hw / ide / core.c
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include <hw/hw.h>
27 #include <hw/i386/pc.h>
28 #include <hw/pci/pci.h>
29 #include <hw/isa/isa.h>
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/dma.h"
34 #include "hw/block/block.h"
35 #include "sysemu/block-backend.h"
36 #include "qemu/cutils.h"
37
38 #include <hw/ide/internal.h>
39
40 /* These values were based on a Seagate ST3500418AS but have been modified
41 to make more sense in QEMU */
42 static const int smart_attributes[][12] = {
43 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
44 /* raw read error rate*/
45 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
46 /* spin up */
47 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
48 /* start stop count */
49 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
50 /* remapped sectors */
51 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
52 /* power on hours */
53 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* power cycle count */
55 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
56 /* airflow-temperature-celsius */
57 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
58 };
59
60 static void ide_dummy_transfer_stop(IDEState *s);
61
62 static void padstr(char *str, const char *src, int len)
63 {
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
70 str[i^1] = v;
71 }
72 }
73
74 static void put_le16(uint16_t *p, unsigned int v)
75 {
76 *p = cpu_to_le16(v);
77 }
78
79 static void ide_identify_size(IDEState *s)
80 {
81 uint16_t *p = (uint16_t *)s->identify_data;
82 put_le16(p + 60, s->nb_sectors);
83 put_le16(p + 61, s->nb_sectors >> 16);
84 put_le16(p + 100, s->nb_sectors);
85 put_le16(p + 101, s->nb_sectors >> 16);
86 put_le16(p + 102, s->nb_sectors >> 32);
87 put_le16(p + 103, s->nb_sectors >> 48);
88 }
89
90 static void ide_identify(IDEState *s)
91 {
92 uint16_t *p;
93 unsigned int oldsize;
94 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
95
96 p = (uint16_t *)s->identify_data;
97 if (s->identify_set) {
98 goto fill_buffer;
99 }
100 memset(p, 0, sizeof(s->identify_data));
101
102 put_le16(p + 0, 0x0040);
103 put_le16(p + 1, s->cylinders);
104 put_le16(p + 3, s->heads);
105 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
106 put_le16(p + 5, 512); /* XXX: retired, remove ? */
107 put_le16(p + 6, s->sectors);
108 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
109 put_le16(p + 20, 3); /* XXX: retired, remove ? */
110 put_le16(p + 21, 512); /* cache size in sectors */
111 put_le16(p + 22, 4); /* ecc bytes */
112 padstr((char *)(p + 23), s->version, 8); /* firmware version */
113 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
114 #if MAX_MULT_SECTORS > 1
115 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
116 #endif
117 put_le16(p + 48, 1); /* dword I/O */
118 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
119 put_le16(p + 51, 0x200); /* PIO transfer cycle */
120 put_le16(p + 52, 0x200); /* DMA transfer cycle */
121 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
122 put_le16(p + 54, s->cylinders);
123 put_le16(p + 55, s->heads);
124 put_le16(p + 56, s->sectors);
125 oldsize = s->cylinders * s->heads * s->sectors;
126 put_le16(p + 57, oldsize);
127 put_le16(p + 58, oldsize >> 16);
128 if (s->mult_sectors)
129 put_le16(p + 59, 0x100 | s->mult_sectors);
130 /* *(p + 60) := nb_sectors -- see ide_identify_size */
131 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
132 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
133 put_le16(p + 63, 0x07); /* mdma0-2 supported */
134 put_le16(p + 64, 0x03); /* pio3-4 supported */
135 put_le16(p + 65, 120);
136 put_le16(p + 66, 120);
137 put_le16(p + 67, 120);
138 put_le16(p + 68, 120);
139 if (dev && dev->conf.discard_granularity) {
140 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
141 }
142
143 if (s->ncq_queues) {
144 put_le16(p + 75, s->ncq_queues - 1);
145 /* NCQ supported */
146 put_le16(p + 76, (1 << 8));
147 }
148
149 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
150 put_le16(p + 81, 0x16); /* conforms to ata5 */
151 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
152 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
153 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
154 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
155 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
156 if (s->wwn) {
157 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
158 } else {
159 put_le16(p + 84, (1 << 14) | 0);
160 }
161 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
162 if (blk_enable_write_cache(s->blk)) {
163 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
164 } else {
165 put_le16(p + 85, (1 << 14) | 1);
166 }
167 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
168 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
169 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
170 if (s->wwn) {
171 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
172 } else {
173 put_le16(p + 87, (1 << 14) | 0);
174 }
175 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
176 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
177 /* *(p + 100) := nb_sectors -- see ide_identify_size */
178 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
179 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
180 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
181
182 if (dev && dev->conf.physical_block_size)
183 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
184 if (s->wwn) {
185 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
186 put_le16(p + 108, s->wwn >> 48);
187 put_le16(p + 109, s->wwn >> 32);
188 put_le16(p + 110, s->wwn >> 16);
189 put_le16(p + 111, s->wwn);
190 }
191 if (dev && dev->conf.discard_granularity) {
192 put_le16(p + 169, 1); /* TRIM support */
193 }
194
195 ide_identify_size(s);
196 s->identify_set = 1;
197
198 fill_buffer:
199 memcpy(s->io_buffer, p, sizeof(s->identify_data));
200 }
201
202 static void ide_atapi_identify(IDEState *s)
203 {
204 uint16_t *p;
205
206 p = (uint16_t *)s->identify_data;
207 if (s->identify_set) {
208 goto fill_buffer;
209 }
210 memset(p, 0, sizeof(s->identify_data));
211
212 /* Removable CDROM, 50us response, 12 byte packets */
213 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
214 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
215 put_le16(p + 20, 3); /* buffer type */
216 put_le16(p + 21, 512); /* cache size in sectors */
217 put_le16(p + 22, 4); /* ecc bytes */
218 padstr((char *)(p + 23), s->version, 8); /* firmware version */
219 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
220 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
221 #ifdef USE_DMA_CDROM
222 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
223 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
224 put_le16(p + 62, 7); /* single word dma0-2 supported */
225 put_le16(p + 63, 7); /* mdma0-2 supported */
226 #else
227 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
228 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
229 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
230 #endif
231 put_le16(p + 64, 3); /* pio3-4 supported */
232 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
233 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
234 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
235 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
236
237 put_le16(p + 71, 30); /* in ns */
238 put_le16(p + 72, 30); /* in ns */
239
240 if (s->ncq_queues) {
241 put_le16(p + 75, s->ncq_queues - 1);
242 /* NCQ supported */
243 put_le16(p + 76, (1 << 8));
244 }
245
246 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
247 if (s->wwn) {
248 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
249 put_le16(p + 87, (1 << 8)); /* WWN enabled */
250 }
251
252 #ifdef USE_DMA_CDROM
253 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
254 #endif
255
256 if (s->wwn) {
257 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
258 put_le16(p + 108, s->wwn >> 48);
259 put_le16(p + 109, s->wwn >> 32);
260 put_le16(p + 110, s->wwn >> 16);
261 put_le16(p + 111, s->wwn);
262 }
263
264 s->identify_set = 1;
265
266 fill_buffer:
267 memcpy(s->io_buffer, p, sizeof(s->identify_data));
268 }
269
270 static void ide_cfata_identify_size(IDEState *s)
271 {
272 uint16_t *p = (uint16_t *)s->identify_data;
273 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
274 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
275 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
276 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
277 }
278
279 static void ide_cfata_identify(IDEState *s)
280 {
281 uint16_t *p;
282 uint32_t cur_sec;
283
284 p = (uint16_t *)s->identify_data;
285 if (s->identify_set) {
286 goto fill_buffer;
287 }
288 memset(p, 0, sizeof(s->identify_data));
289
290 cur_sec = s->cylinders * s->heads * s->sectors;
291
292 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
293 put_le16(p + 1, s->cylinders); /* Default cylinders */
294 put_le16(p + 3, s->heads); /* Default heads */
295 put_le16(p + 6, s->sectors); /* Default sectors per track */
296 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
297 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
298 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
299 put_le16(p + 22, 0x0004); /* ECC bytes */
300 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
301 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
302 #if MAX_MULT_SECTORS > 1
303 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
304 #else
305 put_le16(p + 47, 0x0000);
306 #endif
307 put_le16(p + 49, 0x0f00); /* Capabilities */
308 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
309 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
310 put_le16(p + 53, 0x0003); /* Translation params valid */
311 put_le16(p + 54, s->cylinders); /* Current cylinders */
312 put_le16(p + 55, s->heads); /* Current heads */
313 put_le16(p + 56, s->sectors); /* Current sectors */
314 put_le16(p + 57, cur_sec); /* Current capacity */
315 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
316 if (s->mult_sectors) /* Multiple sector setting */
317 put_le16(p + 59, 0x100 | s->mult_sectors);
318 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
319 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
320 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
321 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
322 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
323 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
324 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
325 put_le16(p + 82, 0x400c); /* Command Set supported */
326 put_le16(p + 83, 0x7068); /* Command Set supported */
327 put_le16(p + 84, 0x4000); /* Features supported */
328 put_le16(p + 85, 0x000c); /* Command Set enabled */
329 put_le16(p + 86, 0x7044); /* Command Set enabled */
330 put_le16(p + 87, 0x4000); /* Features enabled */
331 put_le16(p + 91, 0x4060); /* Current APM level */
332 put_le16(p + 129, 0x0002); /* Current features option */
333 put_le16(p + 130, 0x0005); /* Reassigned sectors */
334 put_le16(p + 131, 0x0001); /* Initial power mode */
335 put_le16(p + 132, 0x0000); /* User signature */
336 put_le16(p + 160, 0x8100); /* Power requirement */
337 put_le16(p + 161, 0x8001); /* CF command set */
338
339 ide_cfata_identify_size(s);
340 s->identify_set = 1;
341
342 fill_buffer:
343 memcpy(s->io_buffer, p, sizeof(s->identify_data));
344 }
345
346 static void ide_set_signature(IDEState *s)
347 {
348 s->select &= 0xf0; /* clear head */
349 /* put signature */
350 s->nsector = 1;
351 s->sector = 1;
352 if (s->drive_kind == IDE_CD) {
353 s->lcyl = 0x14;
354 s->hcyl = 0xeb;
355 } else if (s->blk) {
356 s->lcyl = 0;
357 s->hcyl = 0;
358 } else {
359 s->lcyl = 0xff;
360 s->hcyl = 0xff;
361 }
362 }
363
364 typedef struct TrimAIOCB {
365 BlockAIOCB common;
366 BlockBackend *blk;
367 QEMUBH *bh;
368 int ret;
369 QEMUIOVector *qiov;
370 BlockAIOCB *aiocb;
371 int i, j;
372 } TrimAIOCB;
373
374 static void trim_aio_cancel(BlockAIOCB *acb)
375 {
376 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
377
378 /* Exit the loop so ide_issue_trim_cb will not continue */
379 iocb->j = iocb->qiov->niov - 1;
380 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
381
382 iocb->ret = -ECANCELED;
383
384 if (iocb->aiocb) {
385 blk_aio_cancel_async(iocb->aiocb);
386 iocb->aiocb = NULL;
387 }
388 }
389
390 static const AIOCBInfo trim_aiocb_info = {
391 .aiocb_size = sizeof(TrimAIOCB),
392 .cancel_async = trim_aio_cancel,
393 };
394
395 static void ide_trim_bh_cb(void *opaque)
396 {
397 TrimAIOCB *iocb = opaque;
398
399 iocb->common.cb(iocb->common.opaque, iocb->ret);
400
401 qemu_bh_delete(iocb->bh);
402 iocb->bh = NULL;
403 qemu_aio_unref(iocb);
404 }
405
406 static void ide_issue_trim_cb(void *opaque, int ret)
407 {
408 TrimAIOCB *iocb = opaque;
409 if (ret >= 0) {
410 while (iocb->j < iocb->qiov->niov) {
411 int j = iocb->j;
412 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
413 int i = iocb->i;
414 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
415
416 /* 6-byte LBA + 2-byte range per entry */
417 uint64_t entry = le64_to_cpu(buffer[i]);
418 uint64_t sector = entry & 0x0000ffffffffffffULL;
419 uint16_t count = entry >> 48;
420
421 if (count == 0) {
422 continue;
423 }
424
425 /* Got an entry! Submit and exit. */
426 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
427 ide_issue_trim_cb, opaque);
428 return;
429 }
430
431 iocb->j++;
432 iocb->i = -1;
433 }
434 } else {
435 iocb->ret = ret;
436 }
437
438 iocb->aiocb = NULL;
439 if (iocb->bh) {
440 qemu_bh_schedule(iocb->bh);
441 }
442 }
443
444 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
445 int64_t offset, QEMUIOVector *qiov, BdrvRequestFlags flags,
446 BlockCompletionFunc *cb, void *opaque)
447 {
448 TrimAIOCB *iocb;
449
450 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
451 iocb->blk = blk;
452 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
453 iocb->ret = 0;
454 iocb->qiov = qiov;
455 iocb->i = -1;
456 iocb->j = 0;
457 ide_issue_trim_cb(iocb, 0);
458 return &iocb->common;
459 }
460
461 void ide_abort_command(IDEState *s)
462 {
463 ide_transfer_stop(s);
464 s->status = READY_STAT | ERR_STAT;
465 s->error = ABRT_ERR;
466 }
467
468 /* prepare data transfer and tell what to do after */
469 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
470 EndTransferFunc *end_transfer_func)
471 {
472 s->end_transfer_func = end_transfer_func;
473 s->data_ptr = buf;
474 s->data_end = buf + size;
475 if (!(s->status & ERR_STAT)) {
476 s->status |= DRQ_STAT;
477 }
478 if (s->bus->dma->ops->start_transfer) {
479 s->bus->dma->ops->start_transfer(s->bus->dma);
480 }
481 }
482
483 static void ide_cmd_done(IDEState *s)
484 {
485 if (s->bus->dma->ops->cmd_done) {
486 s->bus->dma->ops->cmd_done(s->bus->dma);
487 }
488 }
489
490 static void ide_transfer_halt(IDEState *s,
491 void(*end_transfer_func)(IDEState *),
492 bool notify)
493 {
494 s->end_transfer_func = end_transfer_func;
495 s->data_ptr = s->io_buffer;
496 s->data_end = s->io_buffer;
497 s->status &= ~DRQ_STAT;
498 if (notify) {
499 ide_cmd_done(s);
500 }
501 }
502
503 void ide_transfer_stop(IDEState *s)
504 {
505 ide_transfer_halt(s, ide_transfer_stop, true);
506 }
507
508 static void ide_transfer_cancel(IDEState *s)
509 {
510 ide_transfer_halt(s, ide_transfer_cancel, false);
511 }
512
513 int64_t ide_get_sector(IDEState *s)
514 {
515 int64_t sector_num;
516 if (s->select & 0x40) {
517 /* lba */
518 if (!s->lba48) {
519 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
520 (s->lcyl << 8) | s->sector;
521 } else {
522 sector_num = ((int64_t)s->hob_hcyl << 40) |
523 ((int64_t) s->hob_lcyl << 32) |
524 ((int64_t) s->hob_sector << 24) |
525 ((int64_t) s->hcyl << 16) |
526 ((int64_t) s->lcyl << 8) | s->sector;
527 }
528 } else {
529 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
530 (s->select & 0x0f) * s->sectors + (s->sector - 1);
531 }
532 return sector_num;
533 }
534
535 void ide_set_sector(IDEState *s, int64_t sector_num)
536 {
537 unsigned int cyl, r;
538 if (s->select & 0x40) {
539 if (!s->lba48) {
540 s->select = (s->select & 0xf0) | (sector_num >> 24);
541 s->hcyl = (sector_num >> 16);
542 s->lcyl = (sector_num >> 8);
543 s->sector = (sector_num);
544 } else {
545 s->sector = sector_num;
546 s->lcyl = sector_num >> 8;
547 s->hcyl = sector_num >> 16;
548 s->hob_sector = sector_num >> 24;
549 s->hob_lcyl = sector_num >> 32;
550 s->hob_hcyl = sector_num >> 40;
551 }
552 } else {
553 cyl = sector_num / (s->heads * s->sectors);
554 r = sector_num % (s->heads * s->sectors);
555 s->hcyl = cyl >> 8;
556 s->lcyl = cyl;
557 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
558 s->sector = (r % s->sectors) + 1;
559 }
560 }
561
562 static void ide_rw_error(IDEState *s) {
563 ide_abort_command(s);
564 ide_set_irq(s->bus);
565 }
566
567 static bool ide_sect_range_ok(IDEState *s,
568 uint64_t sector, uint64_t nb_sectors)
569 {
570 uint64_t total_sectors;
571
572 blk_get_geometry(s->blk, &total_sectors);
573 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
574 return false;
575 }
576 return true;
577 }
578
579 static void ide_buffered_readv_cb(void *opaque, int ret)
580 {
581 IDEBufferedRequest *req = opaque;
582 if (!req->orphaned) {
583 if (!ret) {
584 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
585 req->original_qiov->size);
586 }
587 req->original_cb(req->original_opaque, ret);
588 }
589 QLIST_REMOVE(req, list);
590 qemu_vfree(req->iov.iov_base);
591 g_free(req);
592 }
593
594 #define MAX_BUFFERED_REQS 16
595
596 BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
597 QEMUIOVector *iov, int nb_sectors,
598 BlockCompletionFunc *cb, void *opaque)
599 {
600 BlockAIOCB *aioreq;
601 IDEBufferedRequest *req;
602 int c = 0;
603
604 QLIST_FOREACH(req, &s->buffered_requests, list) {
605 c++;
606 }
607 if (c > MAX_BUFFERED_REQS) {
608 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
609 }
610
611 req = g_new0(IDEBufferedRequest, 1);
612 req->original_qiov = iov;
613 req->original_cb = cb;
614 req->original_opaque = opaque;
615 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
616 req->iov.iov_len = iov->size;
617 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
618
619 aioreq = blk_aio_preadv(s->blk, sector_num << BDRV_SECTOR_BITS,
620 &req->qiov, 0, ide_buffered_readv_cb, req);
621
622 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
623 return aioreq;
624 }
625
626 /**
627 * Cancel all pending DMA requests.
628 * Any buffered DMA requests are instantly canceled,
629 * but any pending unbuffered DMA requests must be waited on.
630 */
631 void ide_cancel_dma_sync(IDEState *s)
632 {
633 IDEBufferedRequest *req;
634
635 /* First invoke the callbacks of all buffered requests
636 * and flag those requests as orphaned. Ideally there
637 * are no unbuffered (Scatter Gather DMA Requests or
638 * write requests) pending and we can avoid to drain. */
639 QLIST_FOREACH(req, &s->buffered_requests, list) {
640 if (!req->orphaned) {
641 #ifdef DEBUG_IDE
642 printf("%s: invoking cb %p of buffered request %p with"
643 " -ECANCELED\n", __func__, req->original_cb, req);
644 #endif
645 req->original_cb(req->original_opaque, -ECANCELED);
646 }
647 req->orphaned = true;
648 }
649
650 /*
651 * We can't cancel Scatter Gather DMA in the middle of the
652 * operation or a partial (not full) DMA transfer would reach
653 * the storage so we wait for completion instead (we beahve
654 * like if the DMA was completed by the time the guest trying
655 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
656 * set).
657 *
658 * In the future we'll be able to safely cancel the I/O if the
659 * whole DMA operation will be submitted to disk with a single
660 * aio operation with preadv/pwritev.
661 */
662 if (s->bus->dma->aiocb) {
663 #ifdef DEBUG_IDE
664 printf("%s: draining all remaining requests", __func__);
665 #endif
666 blk_drain(s->blk);
667 assert(s->bus->dma->aiocb == NULL);
668 }
669 }
670
671 static void ide_sector_read(IDEState *s);
672
673 static void ide_sector_read_cb(void *opaque, int ret)
674 {
675 IDEState *s = opaque;
676 int n;
677
678 s->pio_aiocb = NULL;
679 s->status &= ~BUSY_STAT;
680
681 if (ret == -ECANCELED) {
682 return;
683 }
684 if (ret != 0) {
685 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
686 IDE_RETRY_READ)) {
687 return;
688 }
689 }
690
691 block_acct_done(blk_get_stats(s->blk), &s->acct);
692
693 n = s->nsector;
694 if (n > s->req_nb_sectors) {
695 n = s->req_nb_sectors;
696 }
697
698 ide_set_sector(s, ide_get_sector(s) + n);
699 s->nsector -= n;
700 /* Allow the guest to read the io_buffer */
701 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
702 ide_set_irq(s->bus);
703 }
704
705 static void ide_sector_read(IDEState *s)
706 {
707 int64_t sector_num;
708 int n;
709
710 s->status = READY_STAT | SEEK_STAT;
711 s->error = 0; /* not needed by IDE spec, but needed by Windows */
712 sector_num = ide_get_sector(s);
713 n = s->nsector;
714
715 if (n == 0) {
716 ide_transfer_stop(s);
717 return;
718 }
719
720 s->status |= BUSY_STAT;
721
722 if (n > s->req_nb_sectors) {
723 n = s->req_nb_sectors;
724 }
725
726 #if defined(DEBUG_IDE)
727 printf("sector=%" PRId64 "\n", sector_num);
728 #endif
729
730 if (!ide_sect_range_ok(s, sector_num, n)) {
731 ide_rw_error(s);
732 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
733 return;
734 }
735
736 s->iov.iov_base = s->io_buffer;
737 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
738 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
739
740 block_acct_start(blk_get_stats(s->blk), &s->acct,
741 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
742 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
743 ide_sector_read_cb, s);
744 }
745
746 void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
747 {
748 if (s->bus->dma->ops->commit_buf) {
749 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
750 }
751 s->io_buffer_offset += tx_bytes;
752 qemu_sglist_destroy(&s->sg);
753 }
754
755 void ide_set_inactive(IDEState *s, bool more)
756 {
757 s->bus->dma->aiocb = NULL;
758 s->bus->retry_unit = -1;
759 s->bus->retry_sector_num = 0;
760 s->bus->retry_nsector = 0;
761 if (s->bus->dma->ops->set_inactive) {
762 s->bus->dma->ops->set_inactive(s->bus->dma, more);
763 }
764 ide_cmd_done(s);
765 }
766
767 void ide_dma_error(IDEState *s)
768 {
769 dma_buf_commit(s, 0);
770 ide_abort_command(s);
771 ide_set_inactive(s, false);
772 ide_set_irq(s->bus);
773 }
774
775 int ide_handle_rw_error(IDEState *s, int error, int op)
776 {
777 bool is_read = (op & IDE_RETRY_READ) != 0;
778 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
779
780 if (action == BLOCK_ERROR_ACTION_STOP) {
781 assert(s->bus->retry_unit == s->unit);
782 s->bus->error_status = op;
783 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
784 block_acct_failed(blk_get_stats(s->blk), &s->acct);
785 if (IS_IDE_RETRY_DMA(op)) {
786 ide_dma_error(s);
787 } else if (IS_IDE_RETRY_ATAPI(op)) {
788 ide_atapi_io_error(s, -error);
789 } else {
790 ide_rw_error(s);
791 }
792 }
793 blk_error_action(s->blk, action, is_read, error);
794 return action != BLOCK_ERROR_ACTION_IGNORE;
795 }
796
797 static void ide_dma_cb(void *opaque, int ret)
798 {
799 IDEState *s = opaque;
800 int n;
801 int64_t sector_num;
802 uint64_t offset;
803 bool stay_active = false;
804
805 if (ret == -ECANCELED) {
806 return;
807 }
808 if (ret < 0) {
809 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
810 return;
811 }
812 }
813
814 n = s->io_buffer_size >> 9;
815 if (n > s->nsector) {
816 /* The PRDs were longer than needed for this request. Shorten them so
817 * we don't get a negative remainder. The Active bit must remain set
818 * after the request completes. */
819 n = s->nsector;
820 stay_active = true;
821 }
822
823 sector_num = ide_get_sector(s);
824 if (n > 0) {
825 assert(n * 512 == s->sg.size);
826 dma_buf_commit(s, s->sg.size);
827 sector_num += n;
828 ide_set_sector(s, sector_num);
829 s->nsector -= n;
830 }
831
832 /* end of transfer ? */
833 if (s->nsector == 0) {
834 s->status = READY_STAT | SEEK_STAT;
835 ide_set_irq(s->bus);
836 goto eot;
837 }
838
839 /* launch next transfer */
840 n = s->nsector;
841 s->io_buffer_index = 0;
842 s->io_buffer_size = n * 512;
843 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
844 /* The PRDs were too short. Reset the Active bit, but don't raise an
845 * interrupt. */
846 s->status = READY_STAT | SEEK_STAT;
847 dma_buf_commit(s, 0);
848 goto eot;
849 }
850
851 #ifdef DEBUG_AIO
852 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
853 sector_num, n, s->dma_cmd);
854 #endif
855
856 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
857 !ide_sect_range_ok(s, sector_num, n)) {
858 ide_dma_error(s);
859 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
860 return;
861 }
862
863 offset = sector_num << BDRV_SECTOR_BITS;
864 switch (s->dma_cmd) {
865 case IDE_DMA_READ:
866 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset,
867 ide_dma_cb, s);
868 break;
869 case IDE_DMA_WRITE:
870 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset,
871 ide_dma_cb, s);
872 break;
873 case IDE_DMA_TRIM:
874 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, offset,
875 ide_issue_trim, ide_dma_cb, s,
876 DMA_DIRECTION_TO_DEVICE);
877 break;
878 default:
879 abort();
880 }
881 return;
882
883 eot:
884 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
885 block_acct_done(blk_get_stats(s->blk), &s->acct);
886 }
887 ide_set_inactive(s, stay_active);
888 }
889
890 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
891 {
892 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
893 s->io_buffer_size = 0;
894 s->dma_cmd = dma_cmd;
895
896 switch (dma_cmd) {
897 case IDE_DMA_READ:
898 block_acct_start(blk_get_stats(s->blk), &s->acct,
899 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
900 break;
901 case IDE_DMA_WRITE:
902 block_acct_start(blk_get_stats(s->blk), &s->acct,
903 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
904 break;
905 default:
906 break;
907 }
908
909 ide_start_dma(s, ide_dma_cb);
910 }
911
912 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
913 {
914 s->io_buffer_index = 0;
915 s->bus->retry_unit = s->unit;
916 s->bus->retry_sector_num = ide_get_sector(s);
917 s->bus->retry_nsector = s->nsector;
918 if (s->bus->dma->ops->start_dma) {
919 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
920 }
921 }
922
923 static void ide_sector_write(IDEState *s);
924
925 static void ide_sector_write_timer_cb(void *opaque)
926 {
927 IDEState *s = opaque;
928 ide_set_irq(s->bus);
929 }
930
931 static void ide_sector_write_cb(void *opaque, int ret)
932 {
933 IDEState *s = opaque;
934 int n;
935
936 if (ret == -ECANCELED) {
937 return;
938 }
939
940 s->pio_aiocb = NULL;
941 s->status &= ~BUSY_STAT;
942
943 if (ret != 0) {
944 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
945 return;
946 }
947 }
948
949 block_acct_done(blk_get_stats(s->blk), &s->acct);
950
951 n = s->nsector;
952 if (n > s->req_nb_sectors) {
953 n = s->req_nb_sectors;
954 }
955 s->nsector -= n;
956
957 ide_set_sector(s, ide_get_sector(s) + n);
958 if (s->nsector == 0) {
959 /* no more sectors to write */
960 ide_transfer_stop(s);
961 } else {
962 int n1 = s->nsector;
963 if (n1 > s->req_nb_sectors) {
964 n1 = s->req_nb_sectors;
965 }
966 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
967 ide_sector_write);
968 }
969
970 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
971 /* It seems there is a bug in the Windows 2000 installer HDD
972 IDE driver which fills the disk with empty logs when the
973 IDE write IRQ comes too early. This hack tries to correct
974 that at the expense of slower write performances. Use this
975 option _only_ to install Windows 2000. You must disable it
976 for normal use. */
977 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
978 (NANOSECONDS_PER_SECOND / 1000));
979 } else {
980 ide_set_irq(s->bus);
981 }
982 }
983
984 static void ide_sector_write(IDEState *s)
985 {
986 int64_t sector_num;
987 int n;
988
989 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
990 sector_num = ide_get_sector(s);
991 #if defined(DEBUG_IDE)
992 printf("sector=%" PRId64 "\n", sector_num);
993 #endif
994 n = s->nsector;
995 if (n > s->req_nb_sectors) {
996 n = s->req_nb_sectors;
997 }
998
999 if (!ide_sect_range_ok(s, sector_num, n)) {
1000 ide_rw_error(s);
1001 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
1002 return;
1003 }
1004
1005 s->iov.iov_base = s->io_buffer;
1006 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1007 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1008
1009 block_acct_start(blk_get_stats(s->blk), &s->acct,
1010 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
1011 s->pio_aiocb = blk_aio_pwritev(s->blk, sector_num << BDRV_SECTOR_BITS,
1012 &s->qiov, 0, ide_sector_write_cb, s);
1013 }
1014
1015 static void ide_flush_cb(void *opaque, int ret)
1016 {
1017 IDEState *s = opaque;
1018
1019 s->pio_aiocb = NULL;
1020
1021 if (ret == -ECANCELED) {
1022 return;
1023 }
1024 if (ret < 0) {
1025 /* XXX: What sector number to set here? */
1026 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
1027 return;
1028 }
1029 }
1030
1031 if (s->blk) {
1032 block_acct_done(blk_get_stats(s->blk), &s->acct);
1033 }
1034 s->status = READY_STAT | SEEK_STAT;
1035 ide_cmd_done(s);
1036 ide_set_irq(s->bus);
1037 }
1038
1039 static void ide_flush_cache(IDEState *s)
1040 {
1041 if (s->blk == NULL) {
1042 ide_flush_cb(s, 0);
1043 return;
1044 }
1045
1046 s->status |= BUSY_STAT;
1047 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1048 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
1049 }
1050
1051 static void ide_cfata_metadata_inquiry(IDEState *s)
1052 {
1053 uint16_t *p;
1054 uint32_t spd;
1055
1056 p = (uint16_t *) s->io_buffer;
1057 memset(p, 0, 0x200);
1058 spd = ((s->mdata_size - 1) >> 9) + 1;
1059
1060 put_le16(p + 0, 0x0001); /* Data format revision */
1061 put_le16(p + 1, 0x0000); /* Media property: silicon */
1062 put_le16(p + 2, s->media_changed); /* Media status */
1063 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1064 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1065 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1066 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1067 }
1068
1069 static void ide_cfata_metadata_read(IDEState *s)
1070 {
1071 uint16_t *p;
1072
1073 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1074 s->status = ERR_STAT;
1075 s->error = ABRT_ERR;
1076 return;
1077 }
1078
1079 p = (uint16_t *) s->io_buffer;
1080 memset(p, 0, 0x200);
1081
1082 put_le16(p + 0, s->media_changed); /* Media status */
1083 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1084 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1085 s->nsector << 9), 0x200 - 2));
1086 }
1087
1088 static void ide_cfata_metadata_write(IDEState *s)
1089 {
1090 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1091 s->status = ERR_STAT;
1092 s->error = ABRT_ERR;
1093 return;
1094 }
1095
1096 s->media_changed = 0;
1097
1098 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1099 s->io_buffer + 2,
1100 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1101 s->nsector << 9), 0x200 - 2));
1102 }
1103
1104 /* called when the inserted state of the media has changed */
1105 static void ide_cd_change_cb(void *opaque, bool load)
1106 {
1107 IDEState *s = opaque;
1108 uint64_t nb_sectors;
1109
1110 s->tray_open = !load;
1111 blk_get_geometry(s->blk, &nb_sectors);
1112 s->nb_sectors = nb_sectors;
1113
1114 /*
1115 * First indicate to the guest that a CD has been removed. That's
1116 * done on the next command the guest sends us.
1117 *
1118 * Then we set UNIT_ATTENTION, by which the guest will
1119 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1120 */
1121 s->cdrom_changed = 1;
1122 s->events.new_media = true;
1123 s->events.eject_request = false;
1124 ide_set_irq(s->bus);
1125 }
1126
1127 static void ide_cd_eject_request_cb(void *opaque, bool force)
1128 {
1129 IDEState *s = opaque;
1130
1131 s->events.eject_request = true;
1132 if (force) {
1133 s->tray_locked = false;
1134 }
1135 ide_set_irq(s->bus);
1136 }
1137
1138 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1139 {
1140 s->lba48 = lba48;
1141
1142 /* handle the 'magic' 0 nsector count conversion here. to avoid
1143 * fiddling with the rest of the read logic, we just store the
1144 * full sector count in ->nsector and ignore ->hob_nsector from now
1145 */
1146 if (!s->lba48) {
1147 if (!s->nsector)
1148 s->nsector = 256;
1149 } else {
1150 if (!s->nsector && !s->hob_nsector)
1151 s->nsector = 65536;
1152 else {
1153 int lo = s->nsector;
1154 int hi = s->hob_nsector;
1155
1156 s->nsector = (hi << 8) | lo;
1157 }
1158 }
1159 }
1160
1161 static void ide_clear_hob(IDEBus *bus)
1162 {
1163 /* any write clears HOB high bit of device control register */
1164 bus->ifs[0].select &= ~(1 << 7);
1165 bus->ifs[1].select &= ~(1 << 7);
1166 }
1167
1168 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1169 {
1170 IDEBus *bus = opaque;
1171
1172 #ifdef DEBUG_IDE
1173 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1174 #endif
1175
1176 addr &= 7;
1177
1178 /* ignore writes to command block while busy with previous command */
1179 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1180 return;
1181
1182 switch(addr) {
1183 case 0:
1184 break;
1185 case 1:
1186 ide_clear_hob(bus);
1187 /* NOTE: data is written to the two drives */
1188 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1189 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1190 bus->ifs[0].feature = val;
1191 bus->ifs[1].feature = val;
1192 break;
1193 case 2:
1194 ide_clear_hob(bus);
1195 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1196 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1197 bus->ifs[0].nsector = val;
1198 bus->ifs[1].nsector = val;
1199 break;
1200 case 3:
1201 ide_clear_hob(bus);
1202 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1203 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1204 bus->ifs[0].sector = val;
1205 bus->ifs[1].sector = val;
1206 break;
1207 case 4:
1208 ide_clear_hob(bus);
1209 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1210 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1211 bus->ifs[0].lcyl = val;
1212 bus->ifs[1].lcyl = val;
1213 break;
1214 case 5:
1215 ide_clear_hob(bus);
1216 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1217 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1218 bus->ifs[0].hcyl = val;
1219 bus->ifs[1].hcyl = val;
1220 break;
1221 case 6:
1222 /* FIXME: HOB readback uses bit 7 */
1223 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1224 bus->ifs[1].select = (val | 0x10) | 0xa0;
1225 /* select drive */
1226 bus->unit = (val >> 4) & 1;
1227 break;
1228 default:
1229 case 7:
1230 /* command */
1231 ide_exec_cmd(bus, val);
1232 break;
1233 }
1234 }
1235
1236 static void ide_reset(IDEState *s)
1237 {
1238 #ifdef DEBUG_IDE
1239 printf("ide: reset\n");
1240 #endif
1241
1242 if (s->pio_aiocb) {
1243 blk_aio_cancel(s->pio_aiocb);
1244 s->pio_aiocb = NULL;
1245 }
1246
1247 if (s->drive_kind == IDE_CFATA)
1248 s->mult_sectors = 0;
1249 else
1250 s->mult_sectors = MAX_MULT_SECTORS;
1251 /* ide regs */
1252 s->feature = 0;
1253 s->error = 0;
1254 s->nsector = 0;
1255 s->sector = 0;
1256 s->lcyl = 0;
1257 s->hcyl = 0;
1258
1259 /* lba48 */
1260 s->hob_feature = 0;
1261 s->hob_sector = 0;
1262 s->hob_nsector = 0;
1263 s->hob_lcyl = 0;
1264 s->hob_hcyl = 0;
1265
1266 s->select = 0xa0;
1267 s->status = READY_STAT | SEEK_STAT;
1268
1269 s->lba48 = 0;
1270
1271 /* ATAPI specific */
1272 s->sense_key = 0;
1273 s->asc = 0;
1274 s->cdrom_changed = 0;
1275 s->packet_transfer_size = 0;
1276 s->elementary_transfer_size = 0;
1277 s->io_buffer_index = 0;
1278 s->cd_sector_size = 0;
1279 s->atapi_dma = 0;
1280 s->tray_locked = 0;
1281 s->tray_open = 0;
1282 /* ATA DMA state */
1283 s->io_buffer_size = 0;
1284 s->req_nb_sectors = 0;
1285
1286 ide_set_signature(s);
1287 /* init the transfer handler so that 0xffff is returned on data
1288 accesses */
1289 s->end_transfer_func = ide_dummy_transfer_stop;
1290 ide_dummy_transfer_stop(s);
1291 s->media_changed = 0;
1292 }
1293
1294 static bool cmd_nop(IDEState *s, uint8_t cmd)
1295 {
1296 return true;
1297 }
1298
1299 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1300 {
1301 /* Halt PIO (in the DRQ phase), then DMA */
1302 ide_transfer_cancel(s);
1303 ide_cancel_dma_sync(s);
1304
1305 /* Reset any PIO commands, reset signature, etc */
1306 ide_reset(s);
1307
1308 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1309 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1310 s->status = 0x00;
1311
1312 /* Do not overwrite status register */
1313 return false;
1314 }
1315
1316 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1317 {
1318 switch (s->feature) {
1319 case DSM_TRIM:
1320 if (s->blk) {
1321 ide_sector_start_dma(s, IDE_DMA_TRIM);
1322 return false;
1323 }
1324 break;
1325 }
1326
1327 ide_abort_command(s);
1328 return true;
1329 }
1330
1331 static bool cmd_identify(IDEState *s, uint8_t cmd)
1332 {
1333 if (s->blk && s->drive_kind != IDE_CD) {
1334 if (s->drive_kind != IDE_CFATA) {
1335 ide_identify(s);
1336 } else {
1337 ide_cfata_identify(s);
1338 }
1339 s->status = READY_STAT | SEEK_STAT;
1340 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1341 ide_set_irq(s->bus);
1342 return false;
1343 } else {
1344 if (s->drive_kind == IDE_CD) {
1345 ide_set_signature(s);
1346 }
1347 ide_abort_command(s);
1348 }
1349
1350 return true;
1351 }
1352
1353 static bool cmd_verify(IDEState *s, uint8_t cmd)
1354 {
1355 bool lba48 = (cmd == WIN_VERIFY_EXT);
1356
1357 /* do sector number check ? */
1358 ide_cmd_lba48_transform(s, lba48);
1359
1360 return true;
1361 }
1362
1363 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1364 {
1365 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1366 /* Disable Read and Write Multiple */
1367 s->mult_sectors = 0;
1368 } else if ((s->nsector & 0xff) != 0 &&
1369 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1370 (s->nsector & (s->nsector - 1)) != 0)) {
1371 ide_abort_command(s);
1372 } else {
1373 s->mult_sectors = s->nsector & 0xff;
1374 }
1375
1376 return true;
1377 }
1378
1379 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1380 {
1381 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1382
1383 if (!s->blk || !s->mult_sectors) {
1384 ide_abort_command(s);
1385 return true;
1386 }
1387
1388 ide_cmd_lba48_transform(s, lba48);
1389 s->req_nb_sectors = s->mult_sectors;
1390 ide_sector_read(s);
1391 return false;
1392 }
1393
1394 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1395 {
1396 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1397 int n;
1398
1399 if (!s->blk || !s->mult_sectors) {
1400 ide_abort_command(s);
1401 return true;
1402 }
1403
1404 ide_cmd_lba48_transform(s, lba48);
1405
1406 s->req_nb_sectors = s->mult_sectors;
1407 n = MIN(s->nsector, s->req_nb_sectors);
1408
1409 s->status = SEEK_STAT | READY_STAT;
1410 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1411
1412 s->media_changed = 1;
1413
1414 return false;
1415 }
1416
1417 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1418 {
1419 bool lba48 = (cmd == WIN_READ_EXT);
1420
1421 if (s->drive_kind == IDE_CD) {
1422 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1423 ide_abort_command(s);
1424 return true;
1425 }
1426
1427 if (!s->blk) {
1428 ide_abort_command(s);
1429 return true;
1430 }
1431
1432 ide_cmd_lba48_transform(s, lba48);
1433 s->req_nb_sectors = 1;
1434 ide_sector_read(s);
1435
1436 return false;
1437 }
1438
1439 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1440 {
1441 bool lba48 = (cmd == WIN_WRITE_EXT);
1442
1443 if (!s->blk) {
1444 ide_abort_command(s);
1445 return true;
1446 }
1447
1448 ide_cmd_lba48_transform(s, lba48);
1449
1450 s->req_nb_sectors = 1;
1451 s->status = SEEK_STAT | READY_STAT;
1452 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1453
1454 s->media_changed = 1;
1455
1456 return false;
1457 }
1458
1459 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1460 {
1461 bool lba48 = (cmd == WIN_READDMA_EXT);
1462
1463 if (!s->blk) {
1464 ide_abort_command(s);
1465 return true;
1466 }
1467
1468 ide_cmd_lba48_transform(s, lba48);
1469 ide_sector_start_dma(s, IDE_DMA_READ);
1470
1471 return false;
1472 }
1473
1474 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1475 {
1476 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1477
1478 if (!s->blk) {
1479 ide_abort_command(s);
1480 return true;
1481 }
1482
1483 ide_cmd_lba48_transform(s, lba48);
1484 ide_sector_start_dma(s, IDE_DMA_WRITE);
1485
1486 s->media_changed = 1;
1487
1488 return false;
1489 }
1490
1491 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1492 {
1493 ide_flush_cache(s);
1494 return false;
1495 }
1496
1497 static bool cmd_seek(IDEState *s, uint8_t cmd)
1498 {
1499 /* XXX: Check that seek is within bounds */
1500 return true;
1501 }
1502
1503 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1504 {
1505 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1506
1507 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1508 if (s->nb_sectors == 0) {
1509 ide_abort_command(s);
1510 return true;
1511 }
1512
1513 ide_cmd_lba48_transform(s, lba48);
1514 ide_set_sector(s, s->nb_sectors - 1);
1515
1516 return true;
1517 }
1518
1519 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1520 {
1521 s->nsector = 0xff; /* device active or idle */
1522 return true;
1523 }
1524
1525 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1526 {
1527 uint16_t *identify_data;
1528
1529 if (!s->blk) {
1530 ide_abort_command(s);
1531 return true;
1532 }
1533
1534 /* XXX: valid for CDROM ? */
1535 switch (s->feature) {
1536 case 0x02: /* write cache enable */
1537 blk_set_enable_write_cache(s->blk, true);
1538 identify_data = (uint16_t *)s->identify_data;
1539 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1540 return true;
1541 case 0x82: /* write cache disable */
1542 blk_set_enable_write_cache(s->blk, false);
1543 identify_data = (uint16_t *)s->identify_data;
1544 put_le16(identify_data + 85, (1 << 14) | 1);
1545 ide_flush_cache(s);
1546 return false;
1547 case 0xcc: /* reverting to power-on defaults enable */
1548 case 0x66: /* reverting to power-on defaults disable */
1549 case 0xaa: /* read look-ahead enable */
1550 case 0x55: /* read look-ahead disable */
1551 case 0x05: /* set advanced power management mode */
1552 case 0x85: /* disable advanced power management mode */
1553 case 0x69: /* NOP */
1554 case 0x67: /* NOP */
1555 case 0x96: /* NOP */
1556 case 0x9a: /* NOP */
1557 case 0x42: /* enable Automatic Acoustic Mode */
1558 case 0xc2: /* disable Automatic Acoustic Mode */
1559 return true;
1560 case 0x03: /* set transfer mode */
1561 {
1562 uint8_t val = s->nsector & 0x07;
1563 identify_data = (uint16_t *)s->identify_data;
1564
1565 switch (s->nsector >> 3) {
1566 case 0x00: /* pio default */
1567 case 0x01: /* pio mode */
1568 put_le16(identify_data + 62, 0x07);
1569 put_le16(identify_data + 63, 0x07);
1570 put_le16(identify_data + 88, 0x3f);
1571 break;
1572 case 0x02: /* sigle word dma mode*/
1573 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1574 put_le16(identify_data + 63, 0x07);
1575 put_le16(identify_data + 88, 0x3f);
1576 break;
1577 case 0x04: /* mdma mode */
1578 put_le16(identify_data + 62, 0x07);
1579 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1580 put_le16(identify_data + 88, 0x3f);
1581 break;
1582 case 0x08: /* udma mode */
1583 put_le16(identify_data + 62, 0x07);
1584 put_le16(identify_data + 63, 0x07);
1585 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1586 break;
1587 default:
1588 goto abort_cmd;
1589 }
1590 return true;
1591 }
1592 }
1593
1594 abort_cmd:
1595 ide_abort_command(s);
1596 return true;
1597 }
1598
1599
1600 /*** ATAPI commands ***/
1601
1602 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1603 {
1604 ide_atapi_identify(s);
1605 s->status = READY_STAT | SEEK_STAT;
1606 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1607 ide_set_irq(s->bus);
1608 return false;
1609 }
1610
1611 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1612 {
1613 ide_set_signature(s);
1614
1615 if (s->drive_kind == IDE_CD) {
1616 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1617 * devices to return a clear status register
1618 * with READY_STAT *not* set. */
1619 s->error = 0x01;
1620 } else {
1621 s->status = READY_STAT | SEEK_STAT;
1622 /* The bits of the error register are not as usual for this command!
1623 * They are part of the regular output (this is why ERR_STAT isn't set)
1624 * Device 0 passed, Device 1 passed or not present. */
1625 s->error = 0x01;
1626 ide_set_irq(s->bus);
1627 }
1628
1629 return false;
1630 }
1631
1632 static bool cmd_packet(IDEState *s, uint8_t cmd)
1633 {
1634 /* overlapping commands not supported */
1635 if (s->feature & 0x02) {
1636 ide_abort_command(s);
1637 return true;
1638 }
1639
1640 s->status = READY_STAT | SEEK_STAT;
1641 s->atapi_dma = s->feature & 1;
1642 if (s->atapi_dma) {
1643 s->dma_cmd = IDE_DMA_ATAPI;
1644 }
1645 s->nsector = 1;
1646 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1647 ide_atapi_cmd);
1648 return false;
1649 }
1650
1651
1652 /*** CF-ATA commands ***/
1653
1654 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1655 {
1656 s->error = 0x09; /* miscellaneous error */
1657 s->status = READY_STAT | SEEK_STAT;
1658 ide_set_irq(s->bus);
1659
1660 return false;
1661 }
1662
1663 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1664 {
1665 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1666 * required for Windows 8 to work with AHCI */
1667
1668 if (cmd == CFA_WEAR_LEVEL) {
1669 s->nsector = 0;
1670 }
1671
1672 if (cmd == CFA_ERASE_SECTORS) {
1673 s->media_changed = 1;
1674 }
1675
1676 return true;
1677 }
1678
1679 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1680 {
1681 s->status = READY_STAT | SEEK_STAT;
1682
1683 memset(s->io_buffer, 0, 0x200);
1684 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1685 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1686 s->io_buffer[0x02] = s->select; /* Head */
1687 s->io_buffer[0x03] = s->sector; /* Sector */
1688 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1689 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1690 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1691 s->io_buffer[0x13] = 0x00; /* Erase flag */
1692 s->io_buffer[0x18] = 0x00; /* Hot count */
1693 s->io_buffer[0x19] = 0x00; /* Hot count */
1694 s->io_buffer[0x1a] = 0x01; /* Hot count */
1695
1696 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1697 ide_set_irq(s->bus);
1698
1699 return false;
1700 }
1701
1702 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1703 {
1704 switch (s->feature) {
1705 case 0x02: /* Inquiry Metadata Storage */
1706 ide_cfata_metadata_inquiry(s);
1707 break;
1708 case 0x03: /* Read Metadata Storage */
1709 ide_cfata_metadata_read(s);
1710 break;
1711 case 0x04: /* Write Metadata Storage */
1712 ide_cfata_metadata_write(s);
1713 break;
1714 default:
1715 ide_abort_command(s);
1716 return true;
1717 }
1718
1719 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1720 s->status = 0x00; /* NOTE: READY is _not_ set */
1721 ide_set_irq(s->bus);
1722
1723 return false;
1724 }
1725
1726 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1727 {
1728 switch (s->feature) {
1729 case 0x01: /* sense temperature in device */
1730 s->nsector = 0x50; /* +20 C */
1731 break;
1732 default:
1733 ide_abort_command(s);
1734 return true;
1735 }
1736
1737 return true;
1738 }
1739
1740
1741 /*** SMART commands ***/
1742
1743 static bool cmd_smart(IDEState *s, uint8_t cmd)
1744 {
1745 int n;
1746
1747 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1748 goto abort_cmd;
1749 }
1750
1751 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1752 goto abort_cmd;
1753 }
1754
1755 switch (s->feature) {
1756 case SMART_DISABLE:
1757 s->smart_enabled = 0;
1758 return true;
1759
1760 case SMART_ENABLE:
1761 s->smart_enabled = 1;
1762 return true;
1763
1764 case SMART_ATTR_AUTOSAVE:
1765 switch (s->sector) {
1766 case 0x00:
1767 s->smart_autosave = 0;
1768 break;
1769 case 0xf1:
1770 s->smart_autosave = 1;
1771 break;
1772 default:
1773 goto abort_cmd;
1774 }
1775 return true;
1776
1777 case SMART_STATUS:
1778 if (!s->smart_errors) {
1779 s->hcyl = 0xc2;
1780 s->lcyl = 0x4f;
1781 } else {
1782 s->hcyl = 0x2c;
1783 s->lcyl = 0xf4;
1784 }
1785 return true;
1786
1787 case SMART_READ_THRESH:
1788 memset(s->io_buffer, 0, 0x200);
1789 s->io_buffer[0] = 0x01; /* smart struct version */
1790
1791 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1792 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1793 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1794 }
1795
1796 /* checksum */
1797 for (n = 0; n < 511; n++) {
1798 s->io_buffer[511] += s->io_buffer[n];
1799 }
1800 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1801
1802 s->status = READY_STAT | SEEK_STAT;
1803 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1804 ide_set_irq(s->bus);
1805 return false;
1806
1807 case SMART_READ_DATA:
1808 memset(s->io_buffer, 0, 0x200);
1809 s->io_buffer[0] = 0x01; /* smart struct version */
1810
1811 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1812 int i;
1813 for (i = 0; i < 11; i++) {
1814 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1815 }
1816 }
1817
1818 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1819 if (s->smart_selftest_count == 0) {
1820 s->io_buffer[363] = 0;
1821 } else {
1822 s->io_buffer[363] =
1823 s->smart_selftest_data[3 +
1824 (s->smart_selftest_count - 1) *
1825 24];
1826 }
1827 s->io_buffer[364] = 0x20;
1828 s->io_buffer[365] = 0x01;
1829 /* offline data collection capacity: execute + self-test*/
1830 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1831 s->io_buffer[368] = 0x03; /* smart capability (1) */
1832 s->io_buffer[369] = 0x00; /* smart capability (2) */
1833 s->io_buffer[370] = 0x01; /* error logging supported */
1834 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1835 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1836 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1837
1838 for (n = 0; n < 511; n++) {
1839 s->io_buffer[511] += s->io_buffer[n];
1840 }
1841 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1842
1843 s->status = READY_STAT | SEEK_STAT;
1844 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1845 ide_set_irq(s->bus);
1846 return false;
1847
1848 case SMART_READ_LOG:
1849 switch (s->sector) {
1850 case 0x01: /* summary smart error log */
1851 memset(s->io_buffer, 0, 0x200);
1852 s->io_buffer[0] = 0x01;
1853 s->io_buffer[1] = 0x00; /* no error entries */
1854 s->io_buffer[452] = s->smart_errors & 0xff;
1855 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1856
1857 for (n = 0; n < 511; n++) {
1858 s->io_buffer[511] += s->io_buffer[n];
1859 }
1860 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1861 break;
1862 case 0x06: /* smart self test log */
1863 memset(s->io_buffer, 0, 0x200);
1864 s->io_buffer[0] = 0x01;
1865 if (s->smart_selftest_count == 0) {
1866 s->io_buffer[508] = 0;
1867 } else {
1868 s->io_buffer[508] = s->smart_selftest_count;
1869 for (n = 2; n < 506; n++) {
1870 s->io_buffer[n] = s->smart_selftest_data[n];
1871 }
1872 }
1873
1874 for (n = 0; n < 511; n++) {
1875 s->io_buffer[511] += s->io_buffer[n];
1876 }
1877 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1878 break;
1879 default:
1880 goto abort_cmd;
1881 }
1882 s->status = READY_STAT | SEEK_STAT;
1883 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1884 ide_set_irq(s->bus);
1885 return false;
1886
1887 case SMART_EXECUTE_OFFLINE:
1888 switch (s->sector) {
1889 case 0: /* off-line routine */
1890 case 1: /* short self test */
1891 case 2: /* extended self test */
1892 s->smart_selftest_count++;
1893 if (s->smart_selftest_count > 21) {
1894 s->smart_selftest_count = 1;
1895 }
1896 n = 2 + (s->smart_selftest_count - 1) * 24;
1897 s->smart_selftest_data[n] = s->sector;
1898 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1899 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1900 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1901 break;
1902 default:
1903 goto abort_cmd;
1904 }
1905 return true;
1906 }
1907
1908 abort_cmd:
1909 ide_abort_command(s);
1910 return true;
1911 }
1912
1913 #define HD_OK (1u << IDE_HD)
1914 #define CD_OK (1u << IDE_CD)
1915 #define CFA_OK (1u << IDE_CFATA)
1916 #define HD_CFA_OK (HD_OK | CFA_OK)
1917 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1918
1919 /* Set the Disk Seek Completed status bit during completion */
1920 #define SET_DSC (1u << 8)
1921
1922 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1923 static const struct {
1924 /* Returns true if the completion code should be run */
1925 bool (*handler)(IDEState *s, uint8_t cmd);
1926 int flags;
1927 } ide_cmd_table[0x100] = {
1928 /* NOP not implemented, mandatory for CD */
1929 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1930 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
1931 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1932 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1933 [WIN_READ] = { cmd_read_pio, ALL_OK },
1934 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
1935 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1936 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1937 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1938 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1939 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1940 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1941 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1942 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1943 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1944 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1945 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1946 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1947 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1948 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1949 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1950 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1951 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1952 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1953 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1954 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1955 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1956 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1957 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1958 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
1959 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1960 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1961 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1962 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1963 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1964 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1965 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1966 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1967 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1968 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1969 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1970 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1971 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1972 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1973 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1974 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1975 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1976 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1977 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
1978 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1979 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1980 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1981 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1982 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1983 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1984 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1985 };
1986
1987 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1988 {
1989 return cmd < ARRAY_SIZE(ide_cmd_table)
1990 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1991 }
1992
1993 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1994 {
1995 IDEState *s;
1996 bool complete;
1997
1998 #if defined(DEBUG_IDE)
1999 printf("ide: CMD=%02x\n", val);
2000 #endif
2001 s = idebus_active_if(bus);
2002 /* ignore commands to non existent slave */
2003 if (s != bus->ifs && !s->blk) {
2004 return;
2005 }
2006
2007 /* Only RESET is allowed while BSY and/or DRQ are set,
2008 * and only to ATAPI devices. */
2009 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2010 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2011 return;
2012 }
2013 }
2014
2015 if (!ide_cmd_permitted(s, val)) {
2016 ide_abort_command(s);
2017 ide_set_irq(s->bus);
2018 return;
2019 }
2020
2021 s->status = READY_STAT | BUSY_STAT;
2022 s->error = 0;
2023 s->io_buffer_offset = 0;
2024
2025 complete = ide_cmd_table[val].handler(s, val);
2026 if (complete) {
2027 s->status &= ~BUSY_STAT;
2028 assert(!!s->error == !!(s->status & ERR_STAT));
2029
2030 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2031 s->status |= SEEK_STAT;
2032 }
2033
2034 ide_cmd_done(s);
2035 ide_set_irq(s->bus);
2036 }
2037 }
2038
2039 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2040 {
2041 IDEBus *bus = opaque;
2042 IDEState *s = idebus_active_if(bus);
2043 uint32_t addr;
2044 int ret, hob;
2045
2046 addr = addr1 & 7;
2047 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2048 //hob = s->select & (1 << 7);
2049 hob = 0;
2050 switch(addr) {
2051 case 0:
2052 ret = 0xff;
2053 break;
2054 case 1:
2055 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2056 (s != bus->ifs && !s->blk)) {
2057 ret = 0;
2058 } else if (!hob) {
2059 ret = s->error;
2060 } else {
2061 ret = s->hob_feature;
2062 }
2063 break;
2064 case 2:
2065 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2066 ret = 0;
2067 } else if (!hob) {
2068 ret = s->nsector & 0xff;
2069 } else {
2070 ret = s->hob_nsector;
2071 }
2072 break;
2073 case 3:
2074 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2075 ret = 0;
2076 } else if (!hob) {
2077 ret = s->sector;
2078 } else {
2079 ret = s->hob_sector;
2080 }
2081 break;
2082 case 4:
2083 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2084 ret = 0;
2085 } else if (!hob) {
2086 ret = s->lcyl;
2087 } else {
2088 ret = s->hob_lcyl;
2089 }
2090 break;
2091 case 5:
2092 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2093 ret = 0;
2094 } else if (!hob) {
2095 ret = s->hcyl;
2096 } else {
2097 ret = s->hob_hcyl;
2098 }
2099 break;
2100 case 6:
2101 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2102 ret = 0;
2103 } else {
2104 ret = s->select;
2105 }
2106 break;
2107 default:
2108 case 7:
2109 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2110 (s != bus->ifs && !s->blk)) {
2111 ret = 0;
2112 } else {
2113 ret = s->status;
2114 }
2115 qemu_irq_lower(bus->irq);
2116 break;
2117 }
2118 #ifdef DEBUG_IDE
2119 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2120 #endif
2121 return ret;
2122 }
2123
2124 uint32_t ide_status_read(void *opaque, uint32_t addr)
2125 {
2126 IDEBus *bus = opaque;
2127 IDEState *s = idebus_active_if(bus);
2128 int ret;
2129
2130 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2131 (s != bus->ifs && !s->blk)) {
2132 ret = 0;
2133 } else {
2134 ret = s->status;
2135 }
2136 #ifdef DEBUG_IDE
2137 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2138 #endif
2139 return ret;
2140 }
2141
2142 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2143 {
2144 IDEBus *bus = opaque;
2145 IDEState *s;
2146 int i;
2147
2148 #ifdef DEBUG_IDE
2149 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2150 #endif
2151 /* common for both drives */
2152 if (!(bus->cmd & IDE_CMD_RESET) &&
2153 (val & IDE_CMD_RESET)) {
2154 /* reset low to high */
2155 for(i = 0;i < 2; i++) {
2156 s = &bus->ifs[i];
2157 s->status = BUSY_STAT | SEEK_STAT;
2158 s->error = 0x01;
2159 }
2160 } else if ((bus->cmd & IDE_CMD_RESET) &&
2161 !(val & IDE_CMD_RESET)) {
2162 /* high to low */
2163 for(i = 0;i < 2; i++) {
2164 s = &bus->ifs[i];
2165 if (s->drive_kind == IDE_CD)
2166 s->status = 0x00; /* NOTE: READY is _not_ set */
2167 else
2168 s->status = READY_STAT | SEEK_STAT;
2169 ide_set_signature(s);
2170 }
2171 }
2172
2173 bus->cmd = val;
2174 }
2175
2176 /*
2177 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2178 * transferred from the device to the guest), false if it's a PIO in
2179 */
2180 static bool ide_is_pio_out(IDEState *s)
2181 {
2182 if (s->end_transfer_func == ide_sector_write ||
2183 s->end_transfer_func == ide_atapi_cmd) {
2184 return false;
2185 } else if (s->end_transfer_func == ide_sector_read ||
2186 s->end_transfer_func == ide_transfer_stop ||
2187 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2188 s->end_transfer_func == ide_dummy_transfer_stop) {
2189 return true;
2190 }
2191
2192 abort();
2193 }
2194
2195 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2196 {
2197 IDEBus *bus = opaque;
2198 IDEState *s = idebus_active_if(bus);
2199 uint8_t *p;
2200
2201 /* PIO data access allowed only when DRQ bit is set. The result of a write
2202 * during PIO out is indeterminate, just ignore it. */
2203 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2204 return;
2205 }
2206
2207 p = s->data_ptr;
2208 if (p + 2 > s->data_end) {
2209 return;
2210 }
2211
2212 *(uint16_t *)p = le16_to_cpu(val);
2213 p += 2;
2214 s->data_ptr = p;
2215 if (p >= s->data_end) {
2216 s->status &= ~DRQ_STAT;
2217 s->end_transfer_func(s);
2218 }
2219 }
2220
2221 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2222 {
2223 IDEBus *bus = opaque;
2224 IDEState *s = idebus_active_if(bus);
2225 uint8_t *p;
2226 int ret;
2227
2228 /* PIO data access allowed only when DRQ bit is set. The result of a read
2229 * during PIO in is indeterminate, return 0 and don't move forward. */
2230 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2231 return 0;
2232 }
2233
2234 p = s->data_ptr;
2235 if (p + 2 > s->data_end) {
2236 return 0;
2237 }
2238
2239 ret = cpu_to_le16(*(uint16_t *)p);
2240 p += 2;
2241 s->data_ptr = p;
2242 if (p >= s->data_end) {
2243 s->status &= ~DRQ_STAT;
2244 s->end_transfer_func(s);
2245 }
2246 return ret;
2247 }
2248
2249 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2250 {
2251 IDEBus *bus = opaque;
2252 IDEState *s = idebus_active_if(bus);
2253 uint8_t *p;
2254
2255 /* PIO data access allowed only when DRQ bit is set. The result of a write
2256 * during PIO out is indeterminate, just ignore it. */
2257 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2258 return;
2259 }
2260
2261 p = s->data_ptr;
2262 if (p + 4 > s->data_end) {
2263 return;
2264 }
2265
2266 *(uint32_t *)p = le32_to_cpu(val);
2267 p += 4;
2268 s->data_ptr = p;
2269 if (p >= s->data_end) {
2270 s->status &= ~DRQ_STAT;
2271 s->end_transfer_func(s);
2272 }
2273 }
2274
2275 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2276 {
2277 IDEBus *bus = opaque;
2278 IDEState *s = idebus_active_if(bus);
2279 uint8_t *p;
2280 int ret;
2281
2282 /* PIO data access allowed only when DRQ bit is set. The result of a read
2283 * during PIO in is indeterminate, return 0 and don't move forward. */
2284 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2285 return 0;
2286 }
2287
2288 p = s->data_ptr;
2289 if (p + 4 > s->data_end) {
2290 return 0;
2291 }
2292
2293 ret = cpu_to_le32(*(uint32_t *)p);
2294 p += 4;
2295 s->data_ptr = p;
2296 if (p >= s->data_end) {
2297 s->status &= ~DRQ_STAT;
2298 s->end_transfer_func(s);
2299 }
2300 return ret;
2301 }
2302
2303 static void ide_dummy_transfer_stop(IDEState *s)
2304 {
2305 s->data_ptr = s->io_buffer;
2306 s->data_end = s->io_buffer;
2307 s->io_buffer[0] = 0xff;
2308 s->io_buffer[1] = 0xff;
2309 s->io_buffer[2] = 0xff;
2310 s->io_buffer[3] = 0xff;
2311 }
2312
2313 void ide_bus_reset(IDEBus *bus)
2314 {
2315 bus->unit = 0;
2316 bus->cmd = 0;
2317 ide_reset(&bus->ifs[0]);
2318 ide_reset(&bus->ifs[1]);
2319 ide_clear_hob(bus);
2320
2321 /* pending async DMA */
2322 if (bus->dma->aiocb) {
2323 #ifdef DEBUG_AIO
2324 printf("aio_cancel\n");
2325 #endif
2326 blk_aio_cancel(bus->dma->aiocb);
2327 bus->dma->aiocb = NULL;
2328 }
2329
2330 /* reset dma provider too */
2331 if (bus->dma->ops->reset) {
2332 bus->dma->ops->reset(bus->dma);
2333 }
2334 }
2335
2336 static bool ide_cd_is_tray_open(void *opaque)
2337 {
2338 return ((IDEState *)opaque)->tray_open;
2339 }
2340
2341 static bool ide_cd_is_medium_locked(void *opaque)
2342 {
2343 return ((IDEState *)opaque)->tray_locked;
2344 }
2345
2346 static void ide_resize_cb(void *opaque)
2347 {
2348 IDEState *s = opaque;
2349 uint64_t nb_sectors;
2350
2351 if (!s->identify_set) {
2352 return;
2353 }
2354
2355 blk_get_geometry(s->blk, &nb_sectors);
2356 s->nb_sectors = nb_sectors;
2357
2358 /* Update the identify data buffer. */
2359 if (s->drive_kind == IDE_CFATA) {
2360 ide_cfata_identify_size(s);
2361 } else {
2362 /* IDE_CD uses a different set of callbacks entirely. */
2363 assert(s->drive_kind != IDE_CD);
2364 ide_identify_size(s);
2365 }
2366 }
2367
2368 static const BlockDevOps ide_cd_block_ops = {
2369 .change_media_cb = ide_cd_change_cb,
2370 .eject_request_cb = ide_cd_eject_request_cb,
2371 .is_tray_open = ide_cd_is_tray_open,
2372 .is_medium_locked = ide_cd_is_medium_locked,
2373 };
2374
2375 static const BlockDevOps ide_hd_block_ops = {
2376 .resize_cb = ide_resize_cb,
2377 };
2378
2379 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2380 const char *version, const char *serial, const char *model,
2381 uint64_t wwn,
2382 uint32_t cylinders, uint32_t heads, uint32_t secs,
2383 int chs_trans)
2384 {
2385 uint64_t nb_sectors;
2386
2387 s->blk = blk;
2388 s->drive_kind = kind;
2389
2390 blk_get_geometry(blk, &nb_sectors);
2391 s->cylinders = cylinders;
2392 s->heads = heads;
2393 s->sectors = secs;
2394 s->chs_trans = chs_trans;
2395 s->nb_sectors = nb_sectors;
2396 s->wwn = wwn;
2397 /* The SMART values should be preserved across power cycles
2398 but they aren't. */
2399 s->smart_enabled = 1;
2400 s->smart_autosave = 1;
2401 s->smart_errors = 0;
2402 s->smart_selftest_count = 0;
2403 if (kind == IDE_CD) {
2404 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2405 blk_set_guest_block_size(blk, 2048);
2406 } else {
2407 if (!blk_is_inserted(s->blk)) {
2408 error_report("Device needs media, but drive is empty");
2409 return -1;
2410 }
2411 if (blk_is_read_only(blk)) {
2412 error_report("Can't use a read-only drive");
2413 return -1;
2414 }
2415 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2416 }
2417 if (serial) {
2418 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2419 } else {
2420 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2421 "QM%05d", s->drive_serial);
2422 }
2423 if (model) {
2424 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2425 } else {
2426 switch (kind) {
2427 case IDE_CD:
2428 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2429 break;
2430 case IDE_CFATA:
2431 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2432 break;
2433 default:
2434 strcpy(s->drive_model_str, "QEMU HARDDISK");
2435 break;
2436 }
2437 }
2438
2439 if (version) {
2440 pstrcpy(s->version, sizeof(s->version), version);
2441 } else {
2442 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
2443 }
2444
2445 ide_reset(s);
2446 blk_iostatus_enable(blk);
2447 return 0;
2448 }
2449
2450 static void ide_init1(IDEBus *bus, int unit)
2451 {
2452 static int drive_serial = 1;
2453 IDEState *s = &bus->ifs[unit];
2454
2455 s->bus = bus;
2456 s->unit = unit;
2457 s->drive_serial = drive_serial++;
2458 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2459 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2460 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2461 memset(s->io_buffer, 0, s->io_buffer_total_len);
2462
2463 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2464 memset(s->smart_selftest_data, 0, 512);
2465
2466 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2467 ide_sector_write_timer_cb, s);
2468 }
2469
2470 static int ide_nop_int(IDEDMA *dma, int x)
2471 {
2472 return 0;
2473 }
2474
2475 static void ide_nop(IDEDMA *dma)
2476 {
2477 }
2478
2479 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
2480 {
2481 return 0;
2482 }
2483
2484 static const IDEDMAOps ide_dma_nop_ops = {
2485 .prepare_buf = ide_nop_int32,
2486 .restart_dma = ide_nop,
2487 .rw_buf = ide_nop_int,
2488 };
2489
2490 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2491 {
2492 s->unit = s->bus->retry_unit;
2493 ide_set_sector(s, s->bus->retry_sector_num);
2494 s->nsector = s->bus->retry_nsector;
2495 s->bus->dma->ops->restart_dma(s->bus->dma);
2496 s->io_buffer_size = 0;
2497 s->dma_cmd = dma_cmd;
2498 ide_start_dma(s, ide_dma_cb);
2499 }
2500
2501 static void ide_restart_bh(void *opaque)
2502 {
2503 IDEBus *bus = opaque;
2504 IDEState *s;
2505 bool is_read;
2506 int error_status;
2507
2508 qemu_bh_delete(bus->bh);
2509 bus->bh = NULL;
2510
2511 error_status = bus->error_status;
2512 if (bus->error_status == 0) {
2513 return;
2514 }
2515
2516 s = idebus_active_if(bus);
2517 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2518
2519 /* The error status must be cleared before resubmitting the request: The
2520 * request may fail again, and this case can only be distinguished if the
2521 * called function can set a new error status. */
2522 bus->error_status = 0;
2523
2524 /* The HBA has generically asked to be kicked on retry */
2525 if (error_status & IDE_RETRY_HBA) {
2526 if (s->bus->dma->ops->restart) {
2527 s->bus->dma->ops->restart(s->bus->dma);
2528 }
2529 } else if (IS_IDE_RETRY_DMA(error_status)) {
2530 if (error_status & IDE_RETRY_TRIM) {
2531 ide_restart_dma(s, IDE_DMA_TRIM);
2532 } else {
2533 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2534 }
2535 } else if (IS_IDE_RETRY_PIO(error_status)) {
2536 if (is_read) {
2537 ide_sector_read(s);
2538 } else {
2539 ide_sector_write(s);
2540 }
2541 } else if (error_status & IDE_RETRY_FLUSH) {
2542 ide_flush_cache(s);
2543 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2544 assert(s->end_transfer_func == ide_atapi_cmd);
2545 ide_atapi_dma_restart(s);
2546 } else {
2547 abort();
2548 }
2549 }
2550
2551 static void ide_restart_cb(void *opaque, int running, RunState state)
2552 {
2553 IDEBus *bus = opaque;
2554
2555 if (!running)
2556 return;
2557
2558 if (!bus->bh) {
2559 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2560 qemu_bh_schedule(bus->bh);
2561 }
2562 }
2563
2564 void ide_register_restart_cb(IDEBus *bus)
2565 {
2566 if (bus->dma->ops->restart_dma) {
2567 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2568 }
2569 }
2570
2571 static IDEDMA ide_dma_nop = {
2572 .ops = &ide_dma_nop_ops,
2573 .aiocb = NULL,
2574 };
2575
2576 void ide_init2(IDEBus *bus, qemu_irq irq)
2577 {
2578 int i;
2579
2580 for(i = 0; i < 2; i++) {
2581 ide_init1(bus, i);
2582 ide_reset(&bus->ifs[i]);
2583 }
2584 bus->irq = irq;
2585 bus->dma = &ide_dma_nop;
2586 }
2587
2588 static const MemoryRegionPortio ide_portio_list[] = {
2589 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2590 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2591 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
2592 PORTIO_END_OF_LIST(),
2593 };
2594
2595 static const MemoryRegionPortio ide_portio2_list[] = {
2596 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2597 PORTIO_END_OF_LIST(),
2598 };
2599
2600 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2601 {
2602 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2603 bridge has been setup properly to always register with ISA. */
2604 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2605
2606 if (iobase2) {
2607 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2608 }
2609 }
2610
2611 static bool is_identify_set(void *opaque, int version_id)
2612 {
2613 IDEState *s = opaque;
2614
2615 return s->identify_set != 0;
2616 }
2617
2618 static EndTransferFunc* transfer_end_table[] = {
2619 ide_sector_read,
2620 ide_sector_write,
2621 ide_transfer_stop,
2622 ide_atapi_cmd_reply_end,
2623 ide_atapi_cmd,
2624 ide_dummy_transfer_stop,
2625 };
2626
2627 static int transfer_end_table_idx(EndTransferFunc *fn)
2628 {
2629 int i;
2630
2631 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2632 if (transfer_end_table[i] == fn)
2633 return i;
2634
2635 return -1;
2636 }
2637
2638 static int ide_drive_post_load(void *opaque, int version_id)
2639 {
2640 IDEState *s = opaque;
2641
2642 if (s->blk && s->identify_set) {
2643 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2644 }
2645 return 0;
2646 }
2647
2648 static int ide_drive_pio_post_load(void *opaque, int version_id)
2649 {
2650 IDEState *s = opaque;
2651
2652 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2653 return -EINVAL;
2654 }
2655 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2656 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2657 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2658 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
2659
2660 return 0;
2661 }
2662
2663 static void ide_drive_pio_pre_save(void *opaque)
2664 {
2665 IDEState *s = opaque;
2666 int idx;
2667
2668 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2669 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2670
2671 idx = transfer_end_table_idx(s->end_transfer_func);
2672 if (idx == -1) {
2673 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2674 __func__);
2675 s->end_transfer_fn_idx = 2;
2676 } else {
2677 s->end_transfer_fn_idx = idx;
2678 }
2679 }
2680
2681 static bool ide_drive_pio_state_needed(void *opaque)
2682 {
2683 IDEState *s = opaque;
2684
2685 return ((s->status & DRQ_STAT) != 0)
2686 || (s->bus->error_status & IDE_RETRY_PIO);
2687 }
2688
2689 static bool ide_tray_state_needed(void *opaque)
2690 {
2691 IDEState *s = opaque;
2692
2693 return s->tray_open || s->tray_locked;
2694 }
2695
2696 static bool ide_atapi_gesn_needed(void *opaque)
2697 {
2698 IDEState *s = opaque;
2699
2700 return s->events.new_media || s->events.eject_request;
2701 }
2702
2703 static bool ide_error_needed(void *opaque)
2704 {
2705 IDEBus *bus = opaque;
2706
2707 return (bus->error_status != 0);
2708 }
2709
2710 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2711 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2712 .name ="ide_drive/atapi/gesn_state",
2713 .version_id = 1,
2714 .minimum_version_id = 1,
2715 .needed = ide_atapi_gesn_needed,
2716 .fields = (VMStateField[]) {
2717 VMSTATE_BOOL(events.new_media, IDEState),
2718 VMSTATE_BOOL(events.eject_request, IDEState),
2719 VMSTATE_END_OF_LIST()
2720 }
2721 };
2722
2723 static const VMStateDescription vmstate_ide_tray_state = {
2724 .name = "ide_drive/tray_state",
2725 .version_id = 1,
2726 .minimum_version_id = 1,
2727 .needed = ide_tray_state_needed,
2728 .fields = (VMStateField[]) {
2729 VMSTATE_BOOL(tray_open, IDEState),
2730 VMSTATE_BOOL(tray_locked, IDEState),
2731 VMSTATE_END_OF_LIST()
2732 }
2733 };
2734
2735 static const VMStateDescription vmstate_ide_drive_pio_state = {
2736 .name = "ide_drive/pio_state",
2737 .version_id = 1,
2738 .minimum_version_id = 1,
2739 .pre_save = ide_drive_pio_pre_save,
2740 .post_load = ide_drive_pio_post_load,
2741 .needed = ide_drive_pio_state_needed,
2742 .fields = (VMStateField[]) {
2743 VMSTATE_INT32(req_nb_sectors, IDEState),
2744 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2745 vmstate_info_uint8, uint8_t),
2746 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2747 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2748 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2749 VMSTATE_INT32(elementary_transfer_size, IDEState),
2750 VMSTATE_INT32(packet_transfer_size, IDEState),
2751 VMSTATE_END_OF_LIST()
2752 }
2753 };
2754
2755 const VMStateDescription vmstate_ide_drive = {
2756 .name = "ide_drive",
2757 .version_id = 3,
2758 .minimum_version_id = 0,
2759 .post_load = ide_drive_post_load,
2760 .fields = (VMStateField[]) {
2761 VMSTATE_INT32(mult_sectors, IDEState),
2762 VMSTATE_INT32(identify_set, IDEState),
2763 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2764 VMSTATE_UINT8(feature, IDEState),
2765 VMSTATE_UINT8(error, IDEState),
2766 VMSTATE_UINT32(nsector, IDEState),
2767 VMSTATE_UINT8(sector, IDEState),
2768 VMSTATE_UINT8(lcyl, IDEState),
2769 VMSTATE_UINT8(hcyl, IDEState),
2770 VMSTATE_UINT8(hob_feature, IDEState),
2771 VMSTATE_UINT8(hob_sector, IDEState),
2772 VMSTATE_UINT8(hob_nsector, IDEState),
2773 VMSTATE_UINT8(hob_lcyl, IDEState),
2774 VMSTATE_UINT8(hob_hcyl, IDEState),
2775 VMSTATE_UINT8(select, IDEState),
2776 VMSTATE_UINT8(status, IDEState),
2777 VMSTATE_UINT8(lba48, IDEState),
2778 VMSTATE_UINT8(sense_key, IDEState),
2779 VMSTATE_UINT8(asc, IDEState),
2780 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2781 VMSTATE_END_OF_LIST()
2782 },
2783 .subsections = (const VMStateDescription*[]) {
2784 &vmstate_ide_drive_pio_state,
2785 &vmstate_ide_tray_state,
2786 &vmstate_ide_atapi_gesn_state,
2787 NULL
2788 }
2789 };
2790
2791 static const VMStateDescription vmstate_ide_error_status = {
2792 .name ="ide_bus/error",
2793 .version_id = 2,
2794 .minimum_version_id = 1,
2795 .needed = ide_error_needed,
2796 .fields = (VMStateField[]) {
2797 VMSTATE_INT32(error_status, IDEBus),
2798 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2799 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2800 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
2801 VMSTATE_END_OF_LIST()
2802 }
2803 };
2804
2805 const VMStateDescription vmstate_ide_bus = {
2806 .name = "ide_bus",
2807 .version_id = 1,
2808 .minimum_version_id = 1,
2809 .fields = (VMStateField[]) {
2810 VMSTATE_UINT8(cmd, IDEBus),
2811 VMSTATE_UINT8(unit, IDEBus),
2812 VMSTATE_END_OF_LIST()
2813 },
2814 .subsections = (const VMStateDescription*[]) {
2815 &vmstate_ide_error_status,
2816 NULL
2817 }
2818 };
2819
2820 void ide_drive_get(DriveInfo **hd, int n)
2821 {
2822 int i;
2823 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2824 int max_devs = drive_get_max_devs(IF_IDE);
2825 int n_buses = max_devs ? (n / max_devs) : n;
2826
2827 /*
2828 * Note: The number of actual buses available is not known.
2829 * We compute this based on the size of the DriveInfo* array, n.
2830 * If it is less than max_devs * <num_real_buses>,
2831 * We will stop looking for drives prematurely instead of overfilling
2832 * the array.
2833 */
2834
2835 if (highest_bus > n_buses) {
2836 error_report("Too many IDE buses defined (%d > %d)",
2837 highest_bus, n_buses);
2838 exit(1);
2839 }
2840
2841 for (i = 0; i < n; i++) {
2842 hd[i] = drive_get_by_index(IF_IDE, i);
2843 }
2844 }
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