]> git.proxmox.com Git - mirror_qemu.git/blob - hw/ide/core.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20160413-1' into staging
[mirror_qemu.git] / hw / ide / core.c
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include <hw/hw.h>
27 #include <hw/i386/pc.h>
28 #include <hw/pci/pci.h>
29 #include <hw/isa/isa.h>
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/dma.h"
34 #include "hw/block/block.h"
35 #include "sysemu/block-backend.h"
36 #include "qemu/cutils.h"
37
38 #include <hw/ide/internal.h>
39
40 /* These values were based on a Seagate ST3500418AS but have been modified
41 to make more sense in QEMU */
42 static const int smart_attributes[][12] = {
43 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
44 /* raw read error rate*/
45 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
46 /* spin up */
47 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
48 /* start stop count */
49 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
50 /* remapped sectors */
51 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
52 /* power on hours */
53 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* power cycle count */
55 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
56 /* airflow-temperature-celsius */
57 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
58 };
59
60 static void ide_dummy_transfer_stop(IDEState *s);
61
62 static void padstr(char *str, const char *src, int len)
63 {
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
70 str[i^1] = v;
71 }
72 }
73
74 static void put_le16(uint16_t *p, unsigned int v)
75 {
76 *p = cpu_to_le16(v);
77 }
78
79 static void ide_identify_size(IDEState *s)
80 {
81 uint16_t *p = (uint16_t *)s->identify_data;
82 put_le16(p + 60, s->nb_sectors);
83 put_le16(p + 61, s->nb_sectors >> 16);
84 put_le16(p + 100, s->nb_sectors);
85 put_le16(p + 101, s->nb_sectors >> 16);
86 put_le16(p + 102, s->nb_sectors >> 32);
87 put_le16(p + 103, s->nb_sectors >> 48);
88 }
89
90 static void ide_identify(IDEState *s)
91 {
92 uint16_t *p;
93 unsigned int oldsize;
94 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
95
96 p = (uint16_t *)s->identify_data;
97 if (s->identify_set) {
98 goto fill_buffer;
99 }
100 memset(p, 0, sizeof(s->identify_data));
101
102 put_le16(p + 0, 0x0040);
103 put_le16(p + 1, s->cylinders);
104 put_le16(p + 3, s->heads);
105 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
106 put_le16(p + 5, 512); /* XXX: retired, remove ? */
107 put_le16(p + 6, s->sectors);
108 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
109 put_le16(p + 20, 3); /* XXX: retired, remove ? */
110 put_le16(p + 21, 512); /* cache size in sectors */
111 put_le16(p + 22, 4); /* ecc bytes */
112 padstr((char *)(p + 23), s->version, 8); /* firmware version */
113 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
114 #if MAX_MULT_SECTORS > 1
115 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
116 #endif
117 put_le16(p + 48, 1); /* dword I/O */
118 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
119 put_le16(p + 51, 0x200); /* PIO transfer cycle */
120 put_le16(p + 52, 0x200); /* DMA transfer cycle */
121 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
122 put_le16(p + 54, s->cylinders);
123 put_le16(p + 55, s->heads);
124 put_le16(p + 56, s->sectors);
125 oldsize = s->cylinders * s->heads * s->sectors;
126 put_le16(p + 57, oldsize);
127 put_le16(p + 58, oldsize >> 16);
128 if (s->mult_sectors)
129 put_le16(p + 59, 0x100 | s->mult_sectors);
130 /* *(p + 60) := nb_sectors -- see ide_identify_size */
131 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
132 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
133 put_le16(p + 63, 0x07); /* mdma0-2 supported */
134 put_le16(p + 64, 0x03); /* pio3-4 supported */
135 put_le16(p + 65, 120);
136 put_le16(p + 66, 120);
137 put_le16(p + 67, 120);
138 put_le16(p + 68, 120);
139 if (dev && dev->conf.discard_granularity) {
140 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
141 }
142
143 if (s->ncq_queues) {
144 put_le16(p + 75, s->ncq_queues - 1);
145 /* NCQ supported */
146 put_le16(p + 76, (1 << 8));
147 }
148
149 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
150 put_le16(p + 81, 0x16); /* conforms to ata5 */
151 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
152 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
153 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
154 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
155 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
156 if (s->wwn) {
157 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
158 } else {
159 put_le16(p + 84, (1 << 14) | 0);
160 }
161 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
162 if (blk_enable_write_cache(s->blk)) {
163 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
164 } else {
165 put_le16(p + 85, (1 << 14) | 1);
166 }
167 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
168 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
169 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
170 if (s->wwn) {
171 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
172 } else {
173 put_le16(p + 87, (1 << 14) | 0);
174 }
175 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
176 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
177 /* *(p + 100) := nb_sectors -- see ide_identify_size */
178 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
179 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
180 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
181
182 if (dev && dev->conf.physical_block_size)
183 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
184 if (s->wwn) {
185 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
186 put_le16(p + 108, s->wwn >> 48);
187 put_le16(p + 109, s->wwn >> 32);
188 put_le16(p + 110, s->wwn >> 16);
189 put_le16(p + 111, s->wwn);
190 }
191 if (dev && dev->conf.discard_granularity) {
192 put_le16(p + 169, 1); /* TRIM support */
193 }
194
195 ide_identify_size(s);
196 s->identify_set = 1;
197
198 fill_buffer:
199 memcpy(s->io_buffer, p, sizeof(s->identify_data));
200 }
201
202 static void ide_atapi_identify(IDEState *s)
203 {
204 uint16_t *p;
205
206 p = (uint16_t *)s->identify_data;
207 if (s->identify_set) {
208 goto fill_buffer;
209 }
210 memset(p, 0, sizeof(s->identify_data));
211
212 /* Removable CDROM, 50us response, 12 byte packets */
213 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
214 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
215 put_le16(p + 20, 3); /* buffer type */
216 put_le16(p + 21, 512); /* cache size in sectors */
217 put_le16(p + 22, 4); /* ecc bytes */
218 padstr((char *)(p + 23), s->version, 8); /* firmware version */
219 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
220 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
221 #ifdef USE_DMA_CDROM
222 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
223 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
224 put_le16(p + 62, 7); /* single word dma0-2 supported */
225 put_le16(p + 63, 7); /* mdma0-2 supported */
226 #else
227 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
228 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
229 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
230 #endif
231 put_le16(p + 64, 3); /* pio3-4 supported */
232 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
233 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
234 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
235 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
236
237 put_le16(p + 71, 30); /* in ns */
238 put_le16(p + 72, 30); /* in ns */
239
240 if (s->ncq_queues) {
241 put_le16(p + 75, s->ncq_queues - 1);
242 /* NCQ supported */
243 put_le16(p + 76, (1 << 8));
244 }
245
246 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
247 if (s->wwn) {
248 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
249 put_le16(p + 87, (1 << 8)); /* WWN enabled */
250 }
251
252 #ifdef USE_DMA_CDROM
253 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
254 #endif
255
256 if (s->wwn) {
257 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
258 put_le16(p + 108, s->wwn >> 48);
259 put_le16(p + 109, s->wwn >> 32);
260 put_le16(p + 110, s->wwn >> 16);
261 put_le16(p + 111, s->wwn);
262 }
263
264 s->identify_set = 1;
265
266 fill_buffer:
267 memcpy(s->io_buffer, p, sizeof(s->identify_data));
268 }
269
270 static void ide_cfata_identify_size(IDEState *s)
271 {
272 uint16_t *p = (uint16_t *)s->identify_data;
273 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
274 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
275 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
276 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
277 }
278
279 static void ide_cfata_identify(IDEState *s)
280 {
281 uint16_t *p;
282 uint32_t cur_sec;
283
284 p = (uint16_t *)s->identify_data;
285 if (s->identify_set) {
286 goto fill_buffer;
287 }
288 memset(p, 0, sizeof(s->identify_data));
289
290 cur_sec = s->cylinders * s->heads * s->sectors;
291
292 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
293 put_le16(p + 1, s->cylinders); /* Default cylinders */
294 put_le16(p + 3, s->heads); /* Default heads */
295 put_le16(p + 6, s->sectors); /* Default sectors per track */
296 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
297 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
298 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
299 put_le16(p + 22, 0x0004); /* ECC bytes */
300 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
301 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
302 #if MAX_MULT_SECTORS > 1
303 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
304 #else
305 put_le16(p + 47, 0x0000);
306 #endif
307 put_le16(p + 49, 0x0f00); /* Capabilities */
308 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
309 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
310 put_le16(p + 53, 0x0003); /* Translation params valid */
311 put_le16(p + 54, s->cylinders); /* Current cylinders */
312 put_le16(p + 55, s->heads); /* Current heads */
313 put_le16(p + 56, s->sectors); /* Current sectors */
314 put_le16(p + 57, cur_sec); /* Current capacity */
315 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
316 if (s->mult_sectors) /* Multiple sector setting */
317 put_le16(p + 59, 0x100 | s->mult_sectors);
318 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
319 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
320 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
321 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
322 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
323 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
324 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
325 put_le16(p + 82, 0x400c); /* Command Set supported */
326 put_le16(p + 83, 0x7068); /* Command Set supported */
327 put_le16(p + 84, 0x4000); /* Features supported */
328 put_le16(p + 85, 0x000c); /* Command Set enabled */
329 put_le16(p + 86, 0x7044); /* Command Set enabled */
330 put_le16(p + 87, 0x4000); /* Features enabled */
331 put_le16(p + 91, 0x4060); /* Current APM level */
332 put_le16(p + 129, 0x0002); /* Current features option */
333 put_le16(p + 130, 0x0005); /* Reassigned sectors */
334 put_le16(p + 131, 0x0001); /* Initial power mode */
335 put_le16(p + 132, 0x0000); /* User signature */
336 put_le16(p + 160, 0x8100); /* Power requirement */
337 put_le16(p + 161, 0x8001); /* CF command set */
338
339 ide_cfata_identify_size(s);
340 s->identify_set = 1;
341
342 fill_buffer:
343 memcpy(s->io_buffer, p, sizeof(s->identify_data));
344 }
345
346 static void ide_set_signature(IDEState *s)
347 {
348 s->select &= 0xf0; /* clear head */
349 /* put signature */
350 s->nsector = 1;
351 s->sector = 1;
352 if (s->drive_kind == IDE_CD) {
353 s->lcyl = 0x14;
354 s->hcyl = 0xeb;
355 } else if (s->blk) {
356 s->lcyl = 0;
357 s->hcyl = 0;
358 } else {
359 s->lcyl = 0xff;
360 s->hcyl = 0xff;
361 }
362 }
363
364 typedef struct TrimAIOCB {
365 BlockAIOCB common;
366 BlockBackend *blk;
367 QEMUBH *bh;
368 int ret;
369 QEMUIOVector *qiov;
370 BlockAIOCB *aiocb;
371 int i, j;
372 } TrimAIOCB;
373
374 static void trim_aio_cancel(BlockAIOCB *acb)
375 {
376 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
377
378 /* Exit the loop so ide_issue_trim_cb will not continue */
379 iocb->j = iocb->qiov->niov - 1;
380 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
381
382 iocb->ret = -ECANCELED;
383
384 if (iocb->aiocb) {
385 blk_aio_cancel_async(iocb->aiocb);
386 iocb->aiocb = NULL;
387 }
388 }
389
390 static const AIOCBInfo trim_aiocb_info = {
391 .aiocb_size = sizeof(TrimAIOCB),
392 .cancel_async = trim_aio_cancel,
393 };
394
395 static void ide_trim_bh_cb(void *opaque)
396 {
397 TrimAIOCB *iocb = opaque;
398
399 iocb->common.cb(iocb->common.opaque, iocb->ret);
400
401 qemu_bh_delete(iocb->bh);
402 iocb->bh = NULL;
403 qemu_aio_unref(iocb);
404 }
405
406 static void ide_issue_trim_cb(void *opaque, int ret)
407 {
408 TrimAIOCB *iocb = opaque;
409 if (ret >= 0) {
410 while (iocb->j < iocb->qiov->niov) {
411 int j = iocb->j;
412 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
413 int i = iocb->i;
414 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
415
416 /* 6-byte LBA + 2-byte range per entry */
417 uint64_t entry = le64_to_cpu(buffer[i]);
418 uint64_t sector = entry & 0x0000ffffffffffffULL;
419 uint16_t count = entry >> 48;
420
421 if (count == 0) {
422 continue;
423 }
424
425 /* Got an entry! Submit and exit. */
426 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
427 ide_issue_trim_cb, opaque);
428 return;
429 }
430
431 iocb->j++;
432 iocb->i = -1;
433 }
434 } else {
435 iocb->ret = ret;
436 }
437
438 iocb->aiocb = NULL;
439 if (iocb->bh) {
440 qemu_bh_schedule(iocb->bh);
441 }
442 }
443
444 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
445 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
446 BlockCompletionFunc *cb, void *opaque)
447 {
448 TrimAIOCB *iocb;
449
450 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
451 iocb->blk = blk;
452 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
453 iocb->ret = 0;
454 iocb->qiov = qiov;
455 iocb->i = -1;
456 iocb->j = 0;
457 ide_issue_trim_cb(iocb, 0);
458 return &iocb->common;
459 }
460
461 void ide_abort_command(IDEState *s)
462 {
463 ide_transfer_stop(s);
464 s->status = READY_STAT | ERR_STAT;
465 s->error = ABRT_ERR;
466 }
467
468 /* prepare data transfer and tell what to do after */
469 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
470 EndTransferFunc *end_transfer_func)
471 {
472 s->end_transfer_func = end_transfer_func;
473 s->data_ptr = buf;
474 s->data_end = buf + size;
475 if (!(s->status & ERR_STAT)) {
476 s->status |= DRQ_STAT;
477 }
478 if (s->bus->dma->ops->start_transfer) {
479 s->bus->dma->ops->start_transfer(s->bus->dma);
480 }
481 }
482
483 static void ide_cmd_done(IDEState *s)
484 {
485 if (s->bus->dma->ops->cmd_done) {
486 s->bus->dma->ops->cmd_done(s->bus->dma);
487 }
488 }
489
490 static void ide_transfer_halt(IDEState *s,
491 void(*end_transfer_func)(IDEState *),
492 bool notify)
493 {
494 s->end_transfer_func = end_transfer_func;
495 s->data_ptr = s->io_buffer;
496 s->data_end = s->io_buffer;
497 s->status &= ~DRQ_STAT;
498 if (notify) {
499 ide_cmd_done(s);
500 }
501 }
502
503 void ide_transfer_stop(IDEState *s)
504 {
505 ide_transfer_halt(s, ide_transfer_stop, true);
506 }
507
508 static void ide_transfer_cancel(IDEState *s)
509 {
510 ide_transfer_halt(s, ide_transfer_cancel, false);
511 }
512
513 int64_t ide_get_sector(IDEState *s)
514 {
515 int64_t sector_num;
516 if (s->select & 0x40) {
517 /* lba */
518 if (!s->lba48) {
519 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
520 (s->lcyl << 8) | s->sector;
521 } else {
522 sector_num = ((int64_t)s->hob_hcyl << 40) |
523 ((int64_t) s->hob_lcyl << 32) |
524 ((int64_t) s->hob_sector << 24) |
525 ((int64_t) s->hcyl << 16) |
526 ((int64_t) s->lcyl << 8) | s->sector;
527 }
528 } else {
529 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
530 (s->select & 0x0f) * s->sectors + (s->sector - 1);
531 }
532 return sector_num;
533 }
534
535 void ide_set_sector(IDEState *s, int64_t sector_num)
536 {
537 unsigned int cyl, r;
538 if (s->select & 0x40) {
539 if (!s->lba48) {
540 s->select = (s->select & 0xf0) | (sector_num >> 24);
541 s->hcyl = (sector_num >> 16);
542 s->lcyl = (sector_num >> 8);
543 s->sector = (sector_num);
544 } else {
545 s->sector = sector_num;
546 s->lcyl = sector_num >> 8;
547 s->hcyl = sector_num >> 16;
548 s->hob_sector = sector_num >> 24;
549 s->hob_lcyl = sector_num >> 32;
550 s->hob_hcyl = sector_num >> 40;
551 }
552 } else {
553 cyl = sector_num / (s->heads * s->sectors);
554 r = sector_num % (s->heads * s->sectors);
555 s->hcyl = cyl >> 8;
556 s->lcyl = cyl;
557 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
558 s->sector = (r % s->sectors) + 1;
559 }
560 }
561
562 static void ide_rw_error(IDEState *s) {
563 ide_abort_command(s);
564 ide_set_irq(s->bus);
565 }
566
567 static bool ide_sect_range_ok(IDEState *s,
568 uint64_t sector, uint64_t nb_sectors)
569 {
570 uint64_t total_sectors;
571
572 blk_get_geometry(s->blk, &total_sectors);
573 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
574 return false;
575 }
576 return true;
577 }
578
579 static void ide_buffered_readv_cb(void *opaque, int ret)
580 {
581 IDEBufferedRequest *req = opaque;
582 if (!req->orphaned) {
583 if (!ret) {
584 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
585 req->original_qiov->size);
586 }
587 req->original_cb(req->original_opaque, ret);
588 }
589 QLIST_REMOVE(req, list);
590 qemu_vfree(req->iov.iov_base);
591 g_free(req);
592 }
593
594 #define MAX_BUFFERED_REQS 16
595
596 BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
597 QEMUIOVector *iov, int nb_sectors,
598 BlockCompletionFunc *cb, void *opaque)
599 {
600 BlockAIOCB *aioreq;
601 IDEBufferedRequest *req;
602 int c = 0;
603
604 QLIST_FOREACH(req, &s->buffered_requests, list) {
605 c++;
606 }
607 if (c > MAX_BUFFERED_REQS) {
608 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
609 }
610
611 req = g_new0(IDEBufferedRequest, 1);
612 req->original_qiov = iov;
613 req->original_cb = cb;
614 req->original_opaque = opaque;
615 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
616 req->iov.iov_len = iov->size;
617 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
618
619 aioreq = blk_aio_readv(s->blk, sector_num, &req->qiov, nb_sectors,
620 ide_buffered_readv_cb, req);
621
622 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
623 return aioreq;
624 }
625
626 /**
627 * Cancel all pending DMA requests.
628 * Any buffered DMA requests are instantly canceled,
629 * but any pending unbuffered DMA requests must be waited on.
630 */
631 void ide_cancel_dma_sync(IDEState *s)
632 {
633 IDEBufferedRequest *req;
634
635 /* First invoke the callbacks of all buffered requests
636 * and flag those requests as orphaned. Ideally there
637 * are no unbuffered (Scatter Gather DMA Requests or
638 * write requests) pending and we can avoid to drain. */
639 QLIST_FOREACH(req, &s->buffered_requests, list) {
640 if (!req->orphaned) {
641 #ifdef DEBUG_IDE
642 printf("%s: invoking cb %p of buffered request %p with"
643 " -ECANCELED\n", __func__, req->original_cb, req);
644 #endif
645 req->original_cb(req->original_opaque, -ECANCELED);
646 }
647 req->orphaned = true;
648 }
649
650 /*
651 * We can't cancel Scatter Gather DMA in the middle of the
652 * operation or a partial (not full) DMA transfer would reach
653 * the storage so we wait for completion instead (we beahve
654 * like if the DMA was completed by the time the guest trying
655 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
656 * set).
657 *
658 * In the future we'll be able to safely cancel the I/O if the
659 * whole DMA operation will be submitted to disk with a single
660 * aio operation with preadv/pwritev.
661 */
662 if (s->bus->dma->aiocb) {
663 #ifdef DEBUG_IDE
664 printf("%s: draining all remaining requests", __func__);
665 #endif
666 blk_drain(s->blk);
667 assert(s->bus->dma->aiocb == NULL);
668 }
669 }
670
671 static void ide_sector_read(IDEState *s);
672
673 static void ide_sector_read_cb(void *opaque, int ret)
674 {
675 IDEState *s = opaque;
676 int n;
677
678 s->pio_aiocb = NULL;
679 s->status &= ~BUSY_STAT;
680
681 if (ret == -ECANCELED) {
682 return;
683 }
684 if (ret != 0) {
685 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
686 IDE_RETRY_READ)) {
687 return;
688 }
689 }
690
691 block_acct_done(blk_get_stats(s->blk), &s->acct);
692
693 n = s->nsector;
694 if (n > s->req_nb_sectors) {
695 n = s->req_nb_sectors;
696 }
697
698 ide_set_sector(s, ide_get_sector(s) + n);
699 s->nsector -= n;
700 /* Allow the guest to read the io_buffer */
701 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
702 ide_set_irq(s->bus);
703 }
704
705 static void ide_sector_read(IDEState *s)
706 {
707 int64_t sector_num;
708 int n;
709
710 s->status = READY_STAT | SEEK_STAT;
711 s->error = 0; /* not needed by IDE spec, but needed by Windows */
712 sector_num = ide_get_sector(s);
713 n = s->nsector;
714
715 if (n == 0) {
716 ide_transfer_stop(s);
717 return;
718 }
719
720 s->status |= BUSY_STAT;
721
722 if (n > s->req_nb_sectors) {
723 n = s->req_nb_sectors;
724 }
725
726 #if defined(DEBUG_IDE)
727 printf("sector=%" PRId64 "\n", sector_num);
728 #endif
729
730 if (!ide_sect_range_ok(s, sector_num, n)) {
731 ide_rw_error(s);
732 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
733 return;
734 }
735
736 s->iov.iov_base = s->io_buffer;
737 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
738 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
739
740 block_acct_start(blk_get_stats(s->blk), &s->acct,
741 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
742 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
743 ide_sector_read_cb, s);
744 }
745
746 void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
747 {
748 if (s->bus->dma->ops->commit_buf) {
749 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
750 }
751 s->io_buffer_offset += tx_bytes;
752 qemu_sglist_destroy(&s->sg);
753 }
754
755 void ide_set_inactive(IDEState *s, bool more)
756 {
757 s->bus->dma->aiocb = NULL;
758 s->bus->retry_unit = -1;
759 s->bus->retry_sector_num = 0;
760 s->bus->retry_nsector = 0;
761 if (s->bus->dma->ops->set_inactive) {
762 s->bus->dma->ops->set_inactive(s->bus->dma, more);
763 }
764 ide_cmd_done(s);
765 }
766
767 void ide_dma_error(IDEState *s)
768 {
769 dma_buf_commit(s, 0);
770 ide_abort_command(s);
771 ide_set_inactive(s, false);
772 ide_set_irq(s->bus);
773 }
774
775 int ide_handle_rw_error(IDEState *s, int error, int op)
776 {
777 bool is_read = (op & IDE_RETRY_READ) != 0;
778 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
779
780 if (action == BLOCK_ERROR_ACTION_STOP) {
781 assert(s->bus->retry_unit == s->unit);
782 s->bus->error_status = op;
783 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
784 block_acct_failed(blk_get_stats(s->blk), &s->acct);
785 if (IS_IDE_RETRY_DMA(op)) {
786 ide_dma_error(s);
787 } else if (IS_IDE_RETRY_ATAPI(op)) {
788 ide_atapi_io_error(s, -error);
789 } else {
790 ide_rw_error(s);
791 }
792 }
793 blk_error_action(s->blk, action, is_read, error);
794 return action != BLOCK_ERROR_ACTION_IGNORE;
795 }
796
797 static void ide_dma_cb(void *opaque, int ret)
798 {
799 IDEState *s = opaque;
800 int n;
801 int64_t sector_num;
802 bool stay_active = false;
803
804 if (ret == -ECANCELED) {
805 return;
806 }
807 if (ret < 0) {
808 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
809 return;
810 }
811 }
812
813 n = s->io_buffer_size >> 9;
814 if (n > s->nsector) {
815 /* The PRDs were longer than needed for this request. Shorten them so
816 * we don't get a negative remainder. The Active bit must remain set
817 * after the request completes. */
818 n = s->nsector;
819 stay_active = true;
820 }
821
822 sector_num = ide_get_sector(s);
823 if (n > 0) {
824 assert(n * 512 == s->sg.size);
825 dma_buf_commit(s, s->sg.size);
826 sector_num += n;
827 ide_set_sector(s, sector_num);
828 s->nsector -= n;
829 }
830
831 /* end of transfer ? */
832 if (s->nsector == 0) {
833 s->status = READY_STAT | SEEK_STAT;
834 ide_set_irq(s->bus);
835 goto eot;
836 }
837
838 /* launch next transfer */
839 n = s->nsector;
840 s->io_buffer_index = 0;
841 s->io_buffer_size = n * 512;
842 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
843 /* The PRDs were too short. Reset the Active bit, but don't raise an
844 * interrupt. */
845 s->status = READY_STAT | SEEK_STAT;
846 dma_buf_commit(s, 0);
847 goto eot;
848 }
849
850 #ifdef DEBUG_AIO
851 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
852 sector_num, n, s->dma_cmd);
853 #endif
854
855 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
856 !ide_sect_range_ok(s, sector_num, n)) {
857 ide_dma_error(s);
858 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
859 return;
860 }
861
862 switch (s->dma_cmd) {
863 case IDE_DMA_READ:
864 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
865 ide_dma_cb, s);
866 break;
867 case IDE_DMA_WRITE:
868 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
869 ide_dma_cb, s);
870 break;
871 case IDE_DMA_TRIM:
872 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
873 ide_issue_trim, ide_dma_cb, s,
874 DMA_DIRECTION_TO_DEVICE);
875 break;
876 default:
877 abort();
878 }
879 return;
880
881 eot:
882 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
883 block_acct_done(blk_get_stats(s->blk), &s->acct);
884 }
885 ide_set_inactive(s, stay_active);
886 }
887
888 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
889 {
890 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
891 s->io_buffer_size = 0;
892 s->dma_cmd = dma_cmd;
893
894 switch (dma_cmd) {
895 case IDE_DMA_READ:
896 block_acct_start(blk_get_stats(s->blk), &s->acct,
897 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
898 break;
899 case IDE_DMA_WRITE:
900 block_acct_start(blk_get_stats(s->blk), &s->acct,
901 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
902 break;
903 default:
904 break;
905 }
906
907 ide_start_dma(s, ide_dma_cb);
908 }
909
910 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
911 {
912 s->io_buffer_index = 0;
913 s->bus->retry_unit = s->unit;
914 s->bus->retry_sector_num = ide_get_sector(s);
915 s->bus->retry_nsector = s->nsector;
916 if (s->bus->dma->ops->start_dma) {
917 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
918 }
919 }
920
921 static void ide_sector_write(IDEState *s);
922
923 static void ide_sector_write_timer_cb(void *opaque)
924 {
925 IDEState *s = opaque;
926 ide_set_irq(s->bus);
927 }
928
929 static void ide_sector_write_cb(void *opaque, int ret)
930 {
931 IDEState *s = opaque;
932 int n;
933
934 if (ret == -ECANCELED) {
935 return;
936 }
937
938 s->pio_aiocb = NULL;
939 s->status &= ~BUSY_STAT;
940
941 if (ret != 0) {
942 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
943 return;
944 }
945 }
946
947 block_acct_done(blk_get_stats(s->blk), &s->acct);
948
949 n = s->nsector;
950 if (n > s->req_nb_sectors) {
951 n = s->req_nb_sectors;
952 }
953 s->nsector -= n;
954
955 ide_set_sector(s, ide_get_sector(s) + n);
956 if (s->nsector == 0) {
957 /* no more sectors to write */
958 ide_transfer_stop(s);
959 } else {
960 int n1 = s->nsector;
961 if (n1 > s->req_nb_sectors) {
962 n1 = s->req_nb_sectors;
963 }
964 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
965 ide_sector_write);
966 }
967
968 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
969 /* It seems there is a bug in the Windows 2000 installer HDD
970 IDE driver which fills the disk with empty logs when the
971 IDE write IRQ comes too early. This hack tries to correct
972 that at the expense of slower write performances. Use this
973 option _only_ to install Windows 2000. You must disable it
974 for normal use. */
975 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
976 (NANOSECONDS_PER_SECOND / 1000));
977 } else {
978 ide_set_irq(s->bus);
979 }
980 }
981
982 static void ide_sector_write(IDEState *s)
983 {
984 int64_t sector_num;
985 int n;
986
987 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
988 sector_num = ide_get_sector(s);
989 #if defined(DEBUG_IDE)
990 printf("sector=%" PRId64 "\n", sector_num);
991 #endif
992 n = s->nsector;
993 if (n > s->req_nb_sectors) {
994 n = s->req_nb_sectors;
995 }
996
997 if (!ide_sect_range_ok(s, sector_num, n)) {
998 ide_rw_error(s);
999 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
1000 return;
1001 }
1002
1003 s->iov.iov_base = s->io_buffer;
1004 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1005 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1006
1007 block_acct_start(blk_get_stats(s->blk), &s->acct,
1008 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
1009 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
1010 ide_sector_write_cb, s);
1011 }
1012
1013 static void ide_flush_cb(void *opaque, int ret)
1014 {
1015 IDEState *s = opaque;
1016
1017 s->pio_aiocb = NULL;
1018
1019 if (ret == -ECANCELED) {
1020 return;
1021 }
1022 if (ret < 0) {
1023 /* XXX: What sector number to set here? */
1024 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
1025 return;
1026 }
1027 }
1028
1029 if (s->blk) {
1030 block_acct_done(blk_get_stats(s->blk), &s->acct);
1031 }
1032 s->status = READY_STAT | SEEK_STAT;
1033 ide_cmd_done(s);
1034 ide_set_irq(s->bus);
1035 }
1036
1037 static void ide_flush_cache(IDEState *s)
1038 {
1039 if (s->blk == NULL) {
1040 ide_flush_cb(s, 0);
1041 return;
1042 }
1043
1044 s->status |= BUSY_STAT;
1045 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1046 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
1047 }
1048
1049 static void ide_cfata_metadata_inquiry(IDEState *s)
1050 {
1051 uint16_t *p;
1052 uint32_t spd;
1053
1054 p = (uint16_t *) s->io_buffer;
1055 memset(p, 0, 0x200);
1056 spd = ((s->mdata_size - 1) >> 9) + 1;
1057
1058 put_le16(p + 0, 0x0001); /* Data format revision */
1059 put_le16(p + 1, 0x0000); /* Media property: silicon */
1060 put_le16(p + 2, s->media_changed); /* Media status */
1061 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1062 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1063 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1064 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1065 }
1066
1067 static void ide_cfata_metadata_read(IDEState *s)
1068 {
1069 uint16_t *p;
1070
1071 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1072 s->status = ERR_STAT;
1073 s->error = ABRT_ERR;
1074 return;
1075 }
1076
1077 p = (uint16_t *) s->io_buffer;
1078 memset(p, 0, 0x200);
1079
1080 put_le16(p + 0, s->media_changed); /* Media status */
1081 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1082 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1083 s->nsector << 9), 0x200 - 2));
1084 }
1085
1086 static void ide_cfata_metadata_write(IDEState *s)
1087 {
1088 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1089 s->status = ERR_STAT;
1090 s->error = ABRT_ERR;
1091 return;
1092 }
1093
1094 s->media_changed = 0;
1095
1096 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1097 s->io_buffer + 2,
1098 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1099 s->nsector << 9), 0x200 - 2));
1100 }
1101
1102 /* called when the inserted state of the media has changed */
1103 static void ide_cd_change_cb(void *opaque, bool load)
1104 {
1105 IDEState *s = opaque;
1106 uint64_t nb_sectors;
1107
1108 s->tray_open = !load;
1109 blk_get_geometry(s->blk, &nb_sectors);
1110 s->nb_sectors = nb_sectors;
1111
1112 /*
1113 * First indicate to the guest that a CD has been removed. That's
1114 * done on the next command the guest sends us.
1115 *
1116 * Then we set UNIT_ATTENTION, by which the guest will
1117 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1118 */
1119 s->cdrom_changed = 1;
1120 s->events.new_media = true;
1121 s->events.eject_request = false;
1122 ide_set_irq(s->bus);
1123 }
1124
1125 static void ide_cd_eject_request_cb(void *opaque, bool force)
1126 {
1127 IDEState *s = opaque;
1128
1129 s->events.eject_request = true;
1130 if (force) {
1131 s->tray_locked = false;
1132 }
1133 ide_set_irq(s->bus);
1134 }
1135
1136 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1137 {
1138 s->lba48 = lba48;
1139
1140 /* handle the 'magic' 0 nsector count conversion here. to avoid
1141 * fiddling with the rest of the read logic, we just store the
1142 * full sector count in ->nsector and ignore ->hob_nsector from now
1143 */
1144 if (!s->lba48) {
1145 if (!s->nsector)
1146 s->nsector = 256;
1147 } else {
1148 if (!s->nsector && !s->hob_nsector)
1149 s->nsector = 65536;
1150 else {
1151 int lo = s->nsector;
1152 int hi = s->hob_nsector;
1153
1154 s->nsector = (hi << 8) | lo;
1155 }
1156 }
1157 }
1158
1159 static void ide_clear_hob(IDEBus *bus)
1160 {
1161 /* any write clears HOB high bit of device control register */
1162 bus->ifs[0].select &= ~(1 << 7);
1163 bus->ifs[1].select &= ~(1 << 7);
1164 }
1165
1166 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1167 {
1168 IDEBus *bus = opaque;
1169
1170 #ifdef DEBUG_IDE
1171 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1172 #endif
1173
1174 addr &= 7;
1175
1176 /* ignore writes to command block while busy with previous command */
1177 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1178 return;
1179
1180 switch(addr) {
1181 case 0:
1182 break;
1183 case 1:
1184 ide_clear_hob(bus);
1185 /* NOTE: data is written to the two drives */
1186 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1187 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1188 bus->ifs[0].feature = val;
1189 bus->ifs[1].feature = val;
1190 break;
1191 case 2:
1192 ide_clear_hob(bus);
1193 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1194 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1195 bus->ifs[0].nsector = val;
1196 bus->ifs[1].nsector = val;
1197 break;
1198 case 3:
1199 ide_clear_hob(bus);
1200 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1201 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1202 bus->ifs[0].sector = val;
1203 bus->ifs[1].sector = val;
1204 break;
1205 case 4:
1206 ide_clear_hob(bus);
1207 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1208 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1209 bus->ifs[0].lcyl = val;
1210 bus->ifs[1].lcyl = val;
1211 break;
1212 case 5:
1213 ide_clear_hob(bus);
1214 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1215 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1216 bus->ifs[0].hcyl = val;
1217 bus->ifs[1].hcyl = val;
1218 break;
1219 case 6:
1220 /* FIXME: HOB readback uses bit 7 */
1221 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1222 bus->ifs[1].select = (val | 0x10) | 0xa0;
1223 /* select drive */
1224 bus->unit = (val >> 4) & 1;
1225 break;
1226 default:
1227 case 7:
1228 /* command */
1229 ide_exec_cmd(bus, val);
1230 break;
1231 }
1232 }
1233
1234 static void ide_reset(IDEState *s)
1235 {
1236 #ifdef DEBUG_IDE
1237 printf("ide: reset\n");
1238 #endif
1239
1240 if (s->pio_aiocb) {
1241 blk_aio_cancel(s->pio_aiocb);
1242 s->pio_aiocb = NULL;
1243 }
1244
1245 if (s->drive_kind == IDE_CFATA)
1246 s->mult_sectors = 0;
1247 else
1248 s->mult_sectors = MAX_MULT_SECTORS;
1249 /* ide regs */
1250 s->feature = 0;
1251 s->error = 0;
1252 s->nsector = 0;
1253 s->sector = 0;
1254 s->lcyl = 0;
1255 s->hcyl = 0;
1256
1257 /* lba48 */
1258 s->hob_feature = 0;
1259 s->hob_sector = 0;
1260 s->hob_nsector = 0;
1261 s->hob_lcyl = 0;
1262 s->hob_hcyl = 0;
1263
1264 s->select = 0xa0;
1265 s->status = READY_STAT | SEEK_STAT;
1266
1267 s->lba48 = 0;
1268
1269 /* ATAPI specific */
1270 s->sense_key = 0;
1271 s->asc = 0;
1272 s->cdrom_changed = 0;
1273 s->packet_transfer_size = 0;
1274 s->elementary_transfer_size = 0;
1275 s->io_buffer_index = 0;
1276 s->cd_sector_size = 0;
1277 s->atapi_dma = 0;
1278 s->tray_locked = 0;
1279 s->tray_open = 0;
1280 /* ATA DMA state */
1281 s->io_buffer_size = 0;
1282 s->req_nb_sectors = 0;
1283
1284 ide_set_signature(s);
1285 /* init the transfer handler so that 0xffff is returned on data
1286 accesses */
1287 s->end_transfer_func = ide_dummy_transfer_stop;
1288 ide_dummy_transfer_stop(s);
1289 s->media_changed = 0;
1290 }
1291
1292 static bool cmd_nop(IDEState *s, uint8_t cmd)
1293 {
1294 return true;
1295 }
1296
1297 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1298 {
1299 /* Halt PIO (in the DRQ phase), then DMA */
1300 ide_transfer_cancel(s);
1301 ide_cancel_dma_sync(s);
1302
1303 /* Reset any PIO commands, reset signature, etc */
1304 ide_reset(s);
1305
1306 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1307 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1308 s->status = 0x00;
1309
1310 /* Do not overwrite status register */
1311 return false;
1312 }
1313
1314 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1315 {
1316 switch (s->feature) {
1317 case DSM_TRIM:
1318 if (s->blk) {
1319 ide_sector_start_dma(s, IDE_DMA_TRIM);
1320 return false;
1321 }
1322 break;
1323 }
1324
1325 ide_abort_command(s);
1326 return true;
1327 }
1328
1329 static bool cmd_identify(IDEState *s, uint8_t cmd)
1330 {
1331 if (s->blk && s->drive_kind != IDE_CD) {
1332 if (s->drive_kind != IDE_CFATA) {
1333 ide_identify(s);
1334 } else {
1335 ide_cfata_identify(s);
1336 }
1337 s->status = READY_STAT | SEEK_STAT;
1338 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1339 ide_set_irq(s->bus);
1340 return false;
1341 } else {
1342 if (s->drive_kind == IDE_CD) {
1343 ide_set_signature(s);
1344 }
1345 ide_abort_command(s);
1346 }
1347
1348 return true;
1349 }
1350
1351 static bool cmd_verify(IDEState *s, uint8_t cmd)
1352 {
1353 bool lba48 = (cmd == WIN_VERIFY_EXT);
1354
1355 /* do sector number check ? */
1356 ide_cmd_lba48_transform(s, lba48);
1357
1358 return true;
1359 }
1360
1361 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1362 {
1363 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1364 /* Disable Read and Write Multiple */
1365 s->mult_sectors = 0;
1366 } else if ((s->nsector & 0xff) != 0 &&
1367 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1368 (s->nsector & (s->nsector - 1)) != 0)) {
1369 ide_abort_command(s);
1370 } else {
1371 s->mult_sectors = s->nsector & 0xff;
1372 }
1373
1374 return true;
1375 }
1376
1377 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1378 {
1379 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1380
1381 if (!s->blk || !s->mult_sectors) {
1382 ide_abort_command(s);
1383 return true;
1384 }
1385
1386 ide_cmd_lba48_transform(s, lba48);
1387 s->req_nb_sectors = s->mult_sectors;
1388 ide_sector_read(s);
1389 return false;
1390 }
1391
1392 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1393 {
1394 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1395 int n;
1396
1397 if (!s->blk || !s->mult_sectors) {
1398 ide_abort_command(s);
1399 return true;
1400 }
1401
1402 ide_cmd_lba48_transform(s, lba48);
1403
1404 s->req_nb_sectors = s->mult_sectors;
1405 n = MIN(s->nsector, s->req_nb_sectors);
1406
1407 s->status = SEEK_STAT | READY_STAT;
1408 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1409
1410 s->media_changed = 1;
1411
1412 return false;
1413 }
1414
1415 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1416 {
1417 bool lba48 = (cmd == WIN_READ_EXT);
1418
1419 if (s->drive_kind == IDE_CD) {
1420 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1421 ide_abort_command(s);
1422 return true;
1423 }
1424
1425 if (!s->blk) {
1426 ide_abort_command(s);
1427 return true;
1428 }
1429
1430 ide_cmd_lba48_transform(s, lba48);
1431 s->req_nb_sectors = 1;
1432 ide_sector_read(s);
1433
1434 return false;
1435 }
1436
1437 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1438 {
1439 bool lba48 = (cmd == WIN_WRITE_EXT);
1440
1441 if (!s->blk) {
1442 ide_abort_command(s);
1443 return true;
1444 }
1445
1446 ide_cmd_lba48_transform(s, lba48);
1447
1448 s->req_nb_sectors = 1;
1449 s->status = SEEK_STAT | READY_STAT;
1450 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1451
1452 s->media_changed = 1;
1453
1454 return false;
1455 }
1456
1457 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1458 {
1459 bool lba48 = (cmd == WIN_READDMA_EXT);
1460
1461 if (!s->blk) {
1462 ide_abort_command(s);
1463 return true;
1464 }
1465
1466 ide_cmd_lba48_transform(s, lba48);
1467 ide_sector_start_dma(s, IDE_DMA_READ);
1468
1469 return false;
1470 }
1471
1472 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1473 {
1474 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1475
1476 if (!s->blk) {
1477 ide_abort_command(s);
1478 return true;
1479 }
1480
1481 ide_cmd_lba48_transform(s, lba48);
1482 ide_sector_start_dma(s, IDE_DMA_WRITE);
1483
1484 s->media_changed = 1;
1485
1486 return false;
1487 }
1488
1489 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1490 {
1491 ide_flush_cache(s);
1492 return false;
1493 }
1494
1495 static bool cmd_seek(IDEState *s, uint8_t cmd)
1496 {
1497 /* XXX: Check that seek is within bounds */
1498 return true;
1499 }
1500
1501 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1502 {
1503 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1504
1505 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1506 if (s->nb_sectors == 0) {
1507 ide_abort_command(s);
1508 return true;
1509 }
1510
1511 ide_cmd_lba48_transform(s, lba48);
1512 ide_set_sector(s, s->nb_sectors - 1);
1513
1514 return true;
1515 }
1516
1517 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1518 {
1519 s->nsector = 0xff; /* device active or idle */
1520 return true;
1521 }
1522
1523 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1524 {
1525 uint16_t *identify_data;
1526
1527 if (!s->blk) {
1528 ide_abort_command(s);
1529 return true;
1530 }
1531
1532 /* XXX: valid for CDROM ? */
1533 switch (s->feature) {
1534 case 0x02: /* write cache enable */
1535 blk_set_enable_write_cache(s->blk, true);
1536 identify_data = (uint16_t *)s->identify_data;
1537 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1538 return true;
1539 case 0x82: /* write cache disable */
1540 blk_set_enable_write_cache(s->blk, false);
1541 identify_data = (uint16_t *)s->identify_data;
1542 put_le16(identify_data + 85, (1 << 14) | 1);
1543 ide_flush_cache(s);
1544 return false;
1545 case 0xcc: /* reverting to power-on defaults enable */
1546 case 0x66: /* reverting to power-on defaults disable */
1547 case 0xaa: /* read look-ahead enable */
1548 case 0x55: /* read look-ahead disable */
1549 case 0x05: /* set advanced power management mode */
1550 case 0x85: /* disable advanced power management mode */
1551 case 0x69: /* NOP */
1552 case 0x67: /* NOP */
1553 case 0x96: /* NOP */
1554 case 0x9a: /* NOP */
1555 case 0x42: /* enable Automatic Acoustic Mode */
1556 case 0xc2: /* disable Automatic Acoustic Mode */
1557 return true;
1558 case 0x03: /* set transfer mode */
1559 {
1560 uint8_t val = s->nsector & 0x07;
1561 identify_data = (uint16_t *)s->identify_data;
1562
1563 switch (s->nsector >> 3) {
1564 case 0x00: /* pio default */
1565 case 0x01: /* pio mode */
1566 put_le16(identify_data + 62, 0x07);
1567 put_le16(identify_data + 63, 0x07);
1568 put_le16(identify_data + 88, 0x3f);
1569 break;
1570 case 0x02: /* sigle word dma mode*/
1571 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1572 put_le16(identify_data + 63, 0x07);
1573 put_le16(identify_data + 88, 0x3f);
1574 break;
1575 case 0x04: /* mdma mode */
1576 put_le16(identify_data + 62, 0x07);
1577 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1578 put_le16(identify_data + 88, 0x3f);
1579 break;
1580 case 0x08: /* udma mode */
1581 put_le16(identify_data + 62, 0x07);
1582 put_le16(identify_data + 63, 0x07);
1583 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1584 break;
1585 default:
1586 goto abort_cmd;
1587 }
1588 return true;
1589 }
1590 }
1591
1592 abort_cmd:
1593 ide_abort_command(s);
1594 return true;
1595 }
1596
1597
1598 /*** ATAPI commands ***/
1599
1600 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1601 {
1602 ide_atapi_identify(s);
1603 s->status = READY_STAT | SEEK_STAT;
1604 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1605 ide_set_irq(s->bus);
1606 return false;
1607 }
1608
1609 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1610 {
1611 ide_set_signature(s);
1612
1613 if (s->drive_kind == IDE_CD) {
1614 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1615 * devices to return a clear status register
1616 * with READY_STAT *not* set. */
1617 s->error = 0x01;
1618 } else {
1619 s->status = READY_STAT | SEEK_STAT;
1620 /* The bits of the error register are not as usual for this command!
1621 * They are part of the regular output (this is why ERR_STAT isn't set)
1622 * Device 0 passed, Device 1 passed or not present. */
1623 s->error = 0x01;
1624 ide_set_irq(s->bus);
1625 }
1626
1627 return false;
1628 }
1629
1630 static bool cmd_packet(IDEState *s, uint8_t cmd)
1631 {
1632 /* overlapping commands not supported */
1633 if (s->feature & 0x02) {
1634 ide_abort_command(s);
1635 return true;
1636 }
1637
1638 s->status = READY_STAT | SEEK_STAT;
1639 s->atapi_dma = s->feature & 1;
1640 if (s->atapi_dma) {
1641 s->dma_cmd = IDE_DMA_ATAPI;
1642 }
1643 s->nsector = 1;
1644 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1645 ide_atapi_cmd);
1646 return false;
1647 }
1648
1649
1650 /*** CF-ATA commands ***/
1651
1652 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1653 {
1654 s->error = 0x09; /* miscellaneous error */
1655 s->status = READY_STAT | SEEK_STAT;
1656 ide_set_irq(s->bus);
1657
1658 return false;
1659 }
1660
1661 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1662 {
1663 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1664 * required for Windows 8 to work with AHCI */
1665
1666 if (cmd == CFA_WEAR_LEVEL) {
1667 s->nsector = 0;
1668 }
1669
1670 if (cmd == CFA_ERASE_SECTORS) {
1671 s->media_changed = 1;
1672 }
1673
1674 return true;
1675 }
1676
1677 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1678 {
1679 s->status = READY_STAT | SEEK_STAT;
1680
1681 memset(s->io_buffer, 0, 0x200);
1682 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1683 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1684 s->io_buffer[0x02] = s->select; /* Head */
1685 s->io_buffer[0x03] = s->sector; /* Sector */
1686 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1687 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1688 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1689 s->io_buffer[0x13] = 0x00; /* Erase flag */
1690 s->io_buffer[0x18] = 0x00; /* Hot count */
1691 s->io_buffer[0x19] = 0x00; /* Hot count */
1692 s->io_buffer[0x1a] = 0x01; /* Hot count */
1693
1694 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1695 ide_set_irq(s->bus);
1696
1697 return false;
1698 }
1699
1700 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1701 {
1702 switch (s->feature) {
1703 case 0x02: /* Inquiry Metadata Storage */
1704 ide_cfata_metadata_inquiry(s);
1705 break;
1706 case 0x03: /* Read Metadata Storage */
1707 ide_cfata_metadata_read(s);
1708 break;
1709 case 0x04: /* Write Metadata Storage */
1710 ide_cfata_metadata_write(s);
1711 break;
1712 default:
1713 ide_abort_command(s);
1714 return true;
1715 }
1716
1717 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1718 s->status = 0x00; /* NOTE: READY is _not_ set */
1719 ide_set_irq(s->bus);
1720
1721 return false;
1722 }
1723
1724 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1725 {
1726 switch (s->feature) {
1727 case 0x01: /* sense temperature in device */
1728 s->nsector = 0x50; /* +20 C */
1729 break;
1730 default:
1731 ide_abort_command(s);
1732 return true;
1733 }
1734
1735 return true;
1736 }
1737
1738
1739 /*** SMART commands ***/
1740
1741 static bool cmd_smart(IDEState *s, uint8_t cmd)
1742 {
1743 int n;
1744
1745 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1746 goto abort_cmd;
1747 }
1748
1749 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1750 goto abort_cmd;
1751 }
1752
1753 switch (s->feature) {
1754 case SMART_DISABLE:
1755 s->smart_enabled = 0;
1756 return true;
1757
1758 case SMART_ENABLE:
1759 s->smart_enabled = 1;
1760 return true;
1761
1762 case SMART_ATTR_AUTOSAVE:
1763 switch (s->sector) {
1764 case 0x00:
1765 s->smart_autosave = 0;
1766 break;
1767 case 0xf1:
1768 s->smart_autosave = 1;
1769 break;
1770 default:
1771 goto abort_cmd;
1772 }
1773 return true;
1774
1775 case SMART_STATUS:
1776 if (!s->smart_errors) {
1777 s->hcyl = 0xc2;
1778 s->lcyl = 0x4f;
1779 } else {
1780 s->hcyl = 0x2c;
1781 s->lcyl = 0xf4;
1782 }
1783 return true;
1784
1785 case SMART_READ_THRESH:
1786 memset(s->io_buffer, 0, 0x200);
1787 s->io_buffer[0] = 0x01; /* smart struct version */
1788
1789 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1790 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1791 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1792 }
1793
1794 /* checksum */
1795 for (n = 0; n < 511; n++) {
1796 s->io_buffer[511] += s->io_buffer[n];
1797 }
1798 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1799
1800 s->status = READY_STAT | SEEK_STAT;
1801 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1802 ide_set_irq(s->bus);
1803 return false;
1804
1805 case SMART_READ_DATA:
1806 memset(s->io_buffer, 0, 0x200);
1807 s->io_buffer[0] = 0x01; /* smart struct version */
1808
1809 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1810 int i;
1811 for (i = 0; i < 11; i++) {
1812 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1813 }
1814 }
1815
1816 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1817 if (s->smart_selftest_count == 0) {
1818 s->io_buffer[363] = 0;
1819 } else {
1820 s->io_buffer[363] =
1821 s->smart_selftest_data[3 +
1822 (s->smart_selftest_count - 1) *
1823 24];
1824 }
1825 s->io_buffer[364] = 0x20;
1826 s->io_buffer[365] = 0x01;
1827 /* offline data collection capacity: execute + self-test*/
1828 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1829 s->io_buffer[368] = 0x03; /* smart capability (1) */
1830 s->io_buffer[369] = 0x00; /* smart capability (2) */
1831 s->io_buffer[370] = 0x01; /* error logging supported */
1832 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1833 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1834 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1835
1836 for (n = 0; n < 511; n++) {
1837 s->io_buffer[511] += s->io_buffer[n];
1838 }
1839 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1840
1841 s->status = READY_STAT | SEEK_STAT;
1842 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1843 ide_set_irq(s->bus);
1844 return false;
1845
1846 case SMART_READ_LOG:
1847 switch (s->sector) {
1848 case 0x01: /* summary smart error log */
1849 memset(s->io_buffer, 0, 0x200);
1850 s->io_buffer[0] = 0x01;
1851 s->io_buffer[1] = 0x00; /* no error entries */
1852 s->io_buffer[452] = s->smart_errors & 0xff;
1853 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1854
1855 for (n = 0; n < 511; n++) {
1856 s->io_buffer[511] += s->io_buffer[n];
1857 }
1858 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1859 break;
1860 case 0x06: /* smart self test log */
1861 memset(s->io_buffer, 0, 0x200);
1862 s->io_buffer[0] = 0x01;
1863 if (s->smart_selftest_count == 0) {
1864 s->io_buffer[508] = 0;
1865 } else {
1866 s->io_buffer[508] = s->smart_selftest_count;
1867 for (n = 2; n < 506; n++) {
1868 s->io_buffer[n] = s->smart_selftest_data[n];
1869 }
1870 }
1871
1872 for (n = 0; n < 511; n++) {
1873 s->io_buffer[511] += s->io_buffer[n];
1874 }
1875 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1876 break;
1877 default:
1878 goto abort_cmd;
1879 }
1880 s->status = READY_STAT | SEEK_STAT;
1881 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1882 ide_set_irq(s->bus);
1883 return false;
1884
1885 case SMART_EXECUTE_OFFLINE:
1886 switch (s->sector) {
1887 case 0: /* off-line routine */
1888 case 1: /* short self test */
1889 case 2: /* extended self test */
1890 s->smart_selftest_count++;
1891 if (s->smart_selftest_count > 21) {
1892 s->smart_selftest_count = 1;
1893 }
1894 n = 2 + (s->smart_selftest_count - 1) * 24;
1895 s->smart_selftest_data[n] = s->sector;
1896 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1897 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1898 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1899 break;
1900 default:
1901 goto abort_cmd;
1902 }
1903 return true;
1904 }
1905
1906 abort_cmd:
1907 ide_abort_command(s);
1908 return true;
1909 }
1910
1911 #define HD_OK (1u << IDE_HD)
1912 #define CD_OK (1u << IDE_CD)
1913 #define CFA_OK (1u << IDE_CFATA)
1914 #define HD_CFA_OK (HD_OK | CFA_OK)
1915 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1916
1917 /* Set the Disk Seek Completed status bit during completion */
1918 #define SET_DSC (1u << 8)
1919
1920 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1921 static const struct {
1922 /* Returns true if the completion code should be run */
1923 bool (*handler)(IDEState *s, uint8_t cmd);
1924 int flags;
1925 } ide_cmd_table[0x100] = {
1926 /* NOP not implemented, mandatory for CD */
1927 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1928 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
1929 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1930 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1931 [WIN_READ] = { cmd_read_pio, ALL_OK },
1932 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
1933 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1934 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1935 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1936 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1937 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1938 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1939 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1940 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1941 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1942 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1943 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1944 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1945 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1946 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1947 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1948 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1949 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1950 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1951 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1952 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1953 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1954 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1955 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1956 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
1957 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1958 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1959 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1960 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1961 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1962 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1963 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1964 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1965 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1966 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1967 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1968 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1969 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1970 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1971 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1972 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1973 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1974 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1975 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
1976 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1977 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1978 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1979 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1980 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1981 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1982 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1983 };
1984
1985 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1986 {
1987 return cmd < ARRAY_SIZE(ide_cmd_table)
1988 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1989 }
1990
1991 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1992 {
1993 IDEState *s;
1994 bool complete;
1995
1996 #if defined(DEBUG_IDE)
1997 printf("ide: CMD=%02x\n", val);
1998 #endif
1999 s = idebus_active_if(bus);
2000 /* ignore commands to non existent slave */
2001 if (s != bus->ifs && !s->blk) {
2002 return;
2003 }
2004
2005 /* Only RESET is allowed while BSY and/or DRQ are set,
2006 * and only to ATAPI devices. */
2007 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2008 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2009 return;
2010 }
2011 }
2012
2013 if (!ide_cmd_permitted(s, val)) {
2014 ide_abort_command(s);
2015 ide_set_irq(s->bus);
2016 return;
2017 }
2018
2019 s->status = READY_STAT | BUSY_STAT;
2020 s->error = 0;
2021 s->io_buffer_offset = 0;
2022
2023 complete = ide_cmd_table[val].handler(s, val);
2024 if (complete) {
2025 s->status &= ~BUSY_STAT;
2026 assert(!!s->error == !!(s->status & ERR_STAT));
2027
2028 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2029 s->status |= SEEK_STAT;
2030 }
2031
2032 ide_cmd_done(s);
2033 ide_set_irq(s->bus);
2034 }
2035 }
2036
2037 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2038 {
2039 IDEBus *bus = opaque;
2040 IDEState *s = idebus_active_if(bus);
2041 uint32_t addr;
2042 int ret, hob;
2043
2044 addr = addr1 & 7;
2045 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2046 //hob = s->select & (1 << 7);
2047 hob = 0;
2048 switch(addr) {
2049 case 0:
2050 ret = 0xff;
2051 break;
2052 case 1:
2053 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2054 (s != bus->ifs && !s->blk)) {
2055 ret = 0;
2056 } else if (!hob) {
2057 ret = s->error;
2058 } else {
2059 ret = s->hob_feature;
2060 }
2061 break;
2062 case 2:
2063 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2064 ret = 0;
2065 } else if (!hob) {
2066 ret = s->nsector & 0xff;
2067 } else {
2068 ret = s->hob_nsector;
2069 }
2070 break;
2071 case 3:
2072 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2073 ret = 0;
2074 } else if (!hob) {
2075 ret = s->sector;
2076 } else {
2077 ret = s->hob_sector;
2078 }
2079 break;
2080 case 4:
2081 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2082 ret = 0;
2083 } else if (!hob) {
2084 ret = s->lcyl;
2085 } else {
2086 ret = s->hob_lcyl;
2087 }
2088 break;
2089 case 5:
2090 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2091 ret = 0;
2092 } else if (!hob) {
2093 ret = s->hcyl;
2094 } else {
2095 ret = s->hob_hcyl;
2096 }
2097 break;
2098 case 6:
2099 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2100 ret = 0;
2101 } else {
2102 ret = s->select;
2103 }
2104 break;
2105 default:
2106 case 7:
2107 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2108 (s != bus->ifs && !s->blk)) {
2109 ret = 0;
2110 } else {
2111 ret = s->status;
2112 }
2113 qemu_irq_lower(bus->irq);
2114 break;
2115 }
2116 #ifdef DEBUG_IDE
2117 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2118 #endif
2119 return ret;
2120 }
2121
2122 uint32_t ide_status_read(void *opaque, uint32_t addr)
2123 {
2124 IDEBus *bus = opaque;
2125 IDEState *s = idebus_active_if(bus);
2126 int ret;
2127
2128 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2129 (s != bus->ifs && !s->blk)) {
2130 ret = 0;
2131 } else {
2132 ret = s->status;
2133 }
2134 #ifdef DEBUG_IDE
2135 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2136 #endif
2137 return ret;
2138 }
2139
2140 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2141 {
2142 IDEBus *bus = opaque;
2143 IDEState *s;
2144 int i;
2145
2146 #ifdef DEBUG_IDE
2147 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2148 #endif
2149 /* common for both drives */
2150 if (!(bus->cmd & IDE_CMD_RESET) &&
2151 (val & IDE_CMD_RESET)) {
2152 /* reset low to high */
2153 for(i = 0;i < 2; i++) {
2154 s = &bus->ifs[i];
2155 s->status = BUSY_STAT | SEEK_STAT;
2156 s->error = 0x01;
2157 }
2158 } else if ((bus->cmd & IDE_CMD_RESET) &&
2159 !(val & IDE_CMD_RESET)) {
2160 /* high to low */
2161 for(i = 0;i < 2; i++) {
2162 s = &bus->ifs[i];
2163 if (s->drive_kind == IDE_CD)
2164 s->status = 0x00; /* NOTE: READY is _not_ set */
2165 else
2166 s->status = READY_STAT | SEEK_STAT;
2167 ide_set_signature(s);
2168 }
2169 }
2170
2171 bus->cmd = val;
2172 }
2173
2174 /*
2175 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2176 * transferred from the device to the guest), false if it's a PIO in
2177 */
2178 static bool ide_is_pio_out(IDEState *s)
2179 {
2180 if (s->end_transfer_func == ide_sector_write ||
2181 s->end_transfer_func == ide_atapi_cmd) {
2182 return false;
2183 } else if (s->end_transfer_func == ide_sector_read ||
2184 s->end_transfer_func == ide_transfer_stop ||
2185 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2186 s->end_transfer_func == ide_dummy_transfer_stop) {
2187 return true;
2188 }
2189
2190 abort();
2191 }
2192
2193 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2194 {
2195 IDEBus *bus = opaque;
2196 IDEState *s = idebus_active_if(bus);
2197 uint8_t *p;
2198
2199 /* PIO data access allowed only when DRQ bit is set. The result of a write
2200 * during PIO out is indeterminate, just ignore it. */
2201 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2202 return;
2203 }
2204
2205 p = s->data_ptr;
2206 if (p + 2 > s->data_end) {
2207 return;
2208 }
2209
2210 *(uint16_t *)p = le16_to_cpu(val);
2211 p += 2;
2212 s->data_ptr = p;
2213 if (p >= s->data_end) {
2214 s->status &= ~DRQ_STAT;
2215 s->end_transfer_func(s);
2216 }
2217 }
2218
2219 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2220 {
2221 IDEBus *bus = opaque;
2222 IDEState *s = idebus_active_if(bus);
2223 uint8_t *p;
2224 int ret;
2225
2226 /* PIO data access allowed only when DRQ bit is set. The result of a read
2227 * during PIO in is indeterminate, return 0 and don't move forward. */
2228 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2229 return 0;
2230 }
2231
2232 p = s->data_ptr;
2233 if (p + 2 > s->data_end) {
2234 return 0;
2235 }
2236
2237 ret = cpu_to_le16(*(uint16_t *)p);
2238 p += 2;
2239 s->data_ptr = p;
2240 if (p >= s->data_end) {
2241 s->status &= ~DRQ_STAT;
2242 s->end_transfer_func(s);
2243 }
2244 return ret;
2245 }
2246
2247 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2248 {
2249 IDEBus *bus = opaque;
2250 IDEState *s = idebus_active_if(bus);
2251 uint8_t *p;
2252
2253 /* PIO data access allowed only when DRQ bit is set. The result of a write
2254 * during PIO out is indeterminate, just ignore it. */
2255 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2256 return;
2257 }
2258
2259 p = s->data_ptr;
2260 if (p + 4 > s->data_end) {
2261 return;
2262 }
2263
2264 *(uint32_t *)p = le32_to_cpu(val);
2265 p += 4;
2266 s->data_ptr = p;
2267 if (p >= s->data_end) {
2268 s->status &= ~DRQ_STAT;
2269 s->end_transfer_func(s);
2270 }
2271 }
2272
2273 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2274 {
2275 IDEBus *bus = opaque;
2276 IDEState *s = idebus_active_if(bus);
2277 uint8_t *p;
2278 int ret;
2279
2280 /* PIO data access allowed only when DRQ bit is set. The result of a read
2281 * during PIO in is indeterminate, return 0 and don't move forward. */
2282 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2283 return 0;
2284 }
2285
2286 p = s->data_ptr;
2287 if (p + 4 > s->data_end) {
2288 return 0;
2289 }
2290
2291 ret = cpu_to_le32(*(uint32_t *)p);
2292 p += 4;
2293 s->data_ptr = p;
2294 if (p >= s->data_end) {
2295 s->status &= ~DRQ_STAT;
2296 s->end_transfer_func(s);
2297 }
2298 return ret;
2299 }
2300
2301 static void ide_dummy_transfer_stop(IDEState *s)
2302 {
2303 s->data_ptr = s->io_buffer;
2304 s->data_end = s->io_buffer;
2305 s->io_buffer[0] = 0xff;
2306 s->io_buffer[1] = 0xff;
2307 s->io_buffer[2] = 0xff;
2308 s->io_buffer[3] = 0xff;
2309 }
2310
2311 void ide_bus_reset(IDEBus *bus)
2312 {
2313 bus->unit = 0;
2314 bus->cmd = 0;
2315 ide_reset(&bus->ifs[0]);
2316 ide_reset(&bus->ifs[1]);
2317 ide_clear_hob(bus);
2318
2319 /* pending async DMA */
2320 if (bus->dma->aiocb) {
2321 #ifdef DEBUG_AIO
2322 printf("aio_cancel\n");
2323 #endif
2324 blk_aio_cancel(bus->dma->aiocb);
2325 bus->dma->aiocb = NULL;
2326 }
2327
2328 /* reset dma provider too */
2329 if (bus->dma->ops->reset) {
2330 bus->dma->ops->reset(bus->dma);
2331 }
2332 }
2333
2334 static bool ide_cd_is_tray_open(void *opaque)
2335 {
2336 return ((IDEState *)opaque)->tray_open;
2337 }
2338
2339 static bool ide_cd_is_medium_locked(void *opaque)
2340 {
2341 return ((IDEState *)opaque)->tray_locked;
2342 }
2343
2344 static void ide_resize_cb(void *opaque)
2345 {
2346 IDEState *s = opaque;
2347 uint64_t nb_sectors;
2348
2349 if (!s->identify_set) {
2350 return;
2351 }
2352
2353 blk_get_geometry(s->blk, &nb_sectors);
2354 s->nb_sectors = nb_sectors;
2355
2356 /* Update the identify data buffer. */
2357 if (s->drive_kind == IDE_CFATA) {
2358 ide_cfata_identify_size(s);
2359 } else {
2360 /* IDE_CD uses a different set of callbacks entirely. */
2361 assert(s->drive_kind != IDE_CD);
2362 ide_identify_size(s);
2363 }
2364 }
2365
2366 static const BlockDevOps ide_cd_block_ops = {
2367 .change_media_cb = ide_cd_change_cb,
2368 .eject_request_cb = ide_cd_eject_request_cb,
2369 .is_tray_open = ide_cd_is_tray_open,
2370 .is_medium_locked = ide_cd_is_medium_locked,
2371 };
2372
2373 static const BlockDevOps ide_hd_block_ops = {
2374 .resize_cb = ide_resize_cb,
2375 };
2376
2377 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2378 const char *version, const char *serial, const char *model,
2379 uint64_t wwn,
2380 uint32_t cylinders, uint32_t heads, uint32_t secs,
2381 int chs_trans)
2382 {
2383 uint64_t nb_sectors;
2384
2385 s->blk = blk;
2386 s->drive_kind = kind;
2387
2388 blk_get_geometry(blk, &nb_sectors);
2389 s->cylinders = cylinders;
2390 s->heads = heads;
2391 s->sectors = secs;
2392 s->chs_trans = chs_trans;
2393 s->nb_sectors = nb_sectors;
2394 s->wwn = wwn;
2395 /* The SMART values should be preserved across power cycles
2396 but they aren't. */
2397 s->smart_enabled = 1;
2398 s->smart_autosave = 1;
2399 s->smart_errors = 0;
2400 s->smart_selftest_count = 0;
2401 if (kind == IDE_CD) {
2402 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2403 blk_set_guest_block_size(blk, 2048);
2404 } else {
2405 if (!blk_is_inserted(s->blk)) {
2406 error_report("Device needs media, but drive is empty");
2407 return -1;
2408 }
2409 if (blk_is_read_only(blk)) {
2410 error_report("Can't use a read-only drive");
2411 return -1;
2412 }
2413 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2414 }
2415 if (serial) {
2416 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2417 } else {
2418 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2419 "QM%05d", s->drive_serial);
2420 }
2421 if (model) {
2422 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2423 } else {
2424 switch (kind) {
2425 case IDE_CD:
2426 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2427 break;
2428 case IDE_CFATA:
2429 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2430 break;
2431 default:
2432 strcpy(s->drive_model_str, "QEMU HARDDISK");
2433 break;
2434 }
2435 }
2436
2437 if (version) {
2438 pstrcpy(s->version, sizeof(s->version), version);
2439 } else {
2440 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
2441 }
2442
2443 ide_reset(s);
2444 blk_iostatus_enable(blk);
2445 return 0;
2446 }
2447
2448 static void ide_init1(IDEBus *bus, int unit)
2449 {
2450 static int drive_serial = 1;
2451 IDEState *s = &bus->ifs[unit];
2452
2453 s->bus = bus;
2454 s->unit = unit;
2455 s->drive_serial = drive_serial++;
2456 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2457 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2458 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2459 memset(s->io_buffer, 0, s->io_buffer_total_len);
2460
2461 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2462 memset(s->smart_selftest_data, 0, 512);
2463
2464 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2465 ide_sector_write_timer_cb, s);
2466 }
2467
2468 static int ide_nop_int(IDEDMA *dma, int x)
2469 {
2470 return 0;
2471 }
2472
2473 static void ide_nop(IDEDMA *dma)
2474 {
2475 }
2476
2477 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
2478 {
2479 return 0;
2480 }
2481
2482 static const IDEDMAOps ide_dma_nop_ops = {
2483 .prepare_buf = ide_nop_int32,
2484 .restart_dma = ide_nop,
2485 .rw_buf = ide_nop_int,
2486 };
2487
2488 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2489 {
2490 s->unit = s->bus->retry_unit;
2491 ide_set_sector(s, s->bus->retry_sector_num);
2492 s->nsector = s->bus->retry_nsector;
2493 s->bus->dma->ops->restart_dma(s->bus->dma);
2494 s->io_buffer_size = 0;
2495 s->dma_cmd = dma_cmd;
2496 ide_start_dma(s, ide_dma_cb);
2497 }
2498
2499 static void ide_restart_bh(void *opaque)
2500 {
2501 IDEBus *bus = opaque;
2502 IDEState *s;
2503 bool is_read;
2504 int error_status;
2505
2506 qemu_bh_delete(bus->bh);
2507 bus->bh = NULL;
2508
2509 error_status = bus->error_status;
2510 if (bus->error_status == 0) {
2511 return;
2512 }
2513
2514 s = idebus_active_if(bus);
2515 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2516
2517 /* The error status must be cleared before resubmitting the request: The
2518 * request may fail again, and this case can only be distinguished if the
2519 * called function can set a new error status. */
2520 bus->error_status = 0;
2521
2522 /* The HBA has generically asked to be kicked on retry */
2523 if (error_status & IDE_RETRY_HBA) {
2524 if (s->bus->dma->ops->restart) {
2525 s->bus->dma->ops->restart(s->bus->dma);
2526 }
2527 } else if (IS_IDE_RETRY_DMA(error_status)) {
2528 if (error_status & IDE_RETRY_TRIM) {
2529 ide_restart_dma(s, IDE_DMA_TRIM);
2530 } else {
2531 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2532 }
2533 } else if (IS_IDE_RETRY_PIO(error_status)) {
2534 if (is_read) {
2535 ide_sector_read(s);
2536 } else {
2537 ide_sector_write(s);
2538 }
2539 } else if (error_status & IDE_RETRY_FLUSH) {
2540 ide_flush_cache(s);
2541 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2542 assert(s->end_transfer_func == ide_atapi_cmd);
2543 ide_atapi_dma_restart(s);
2544 } else {
2545 abort();
2546 }
2547 }
2548
2549 static void ide_restart_cb(void *opaque, int running, RunState state)
2550 {
2551 IDEBus *bus = opaque;
2552
2553 if (!running)
2554 return;
2555
2556 if (!bus->bh) {
2557 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2558 qemu_bh_schedule(bus->bh);
2559 }
2560 }
2561
2562 void ide_register_restart_cb(IDEBus *bus)
2563 {
2564 if (bus->dma->ops->restart_dma) {
2565 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2566 }
2567 }
2568
2569 static IDEDMA ide_dma_nop = {
2570 .ops = &ide_dma_nop_ops,
2571 .aiocb = NULL,
2572 };
2573
2574 void ide_init2(IDEBus *bus, qemu_irq irq)
2575 {
2576 int i;
2577
2578 for(i = 0; i < 2; i++) {
2579 ide_init1(bus, i);
2580 ide_reset(&bus->ifs[i]);
2581 }
2582 bus->irq = irq;
2583 bus->dma = &ide_dma_nop;
2584 }
2585
2586 static const MemoryRegionPortio ide_portio_list[] = {
2587 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2588 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2589 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
2590 PORTIO_END_OF_LIST(),
2591 };
2592
2593 static const MemoryRegionPortio ide_portio2_list[] = {
2594 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2595 PORTIO_END_OF_LIST(),
2596 };
2597
2598 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2599 {
2600 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2601 bridge has been setup properly to always register with ISA. */
2602 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2603
2604 if (iobase2) {
2605 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2606 }
2607 }
2608
2609 static bool is_identify_set(void *opaque, int version_id)
2610 {
2611 IDEState *s = opaque;
2612
2613 return s->identify_set != 0;
2614 }
2615
2616 static EndTransferFunc* transfer_end_table[] = {
2617 ide_sector_read,
2618 ide_sector_write,
2619 ide_transfer_stop,
2620 ide_atapi_cmd_reply_end,
2621 ide_atapi_cmd,
2622 ide_dummy_transfer_stop,
2623 };
2624
2625 static int transfer_end_table_idx(EndTransferFunc *fn)
2626 {
2627 int i;
2628
2629 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2630 if (transfer_end_table[i] == fn)
2631 return i;
2632
2633 return -1;
2634 }
2635
2636 static int ide_drive_post_load(void *opaque, int version_id)
2637 {
2638 IDEState *s = opaque;
2639
2640 if (s->blk && s->identify_set) {
2641 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2642 }
2643 return 0;
2644 }
2645
2646 static int ide_drive_pio_post_load(void *opaque, int version_id)
2647 {
2648 IDEState *s = opaque;
2649
2650 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2651 return -EINVAL;
2652 }
2653 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2654 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2655 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2656 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
2657
2658 return 0;
2659 }
2660
2661 static void ide_drive_pio_pre_save(void *opaque)
2662 {
2663 IDEState *s = opaque;
2664 int idx;
2665
2666 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2667 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2668
2669 idx = transfer_end_table_idx(s->end_transfer_func);
2670 if (idx == -1) {
2671 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2672 __func__);
2673 s->end_transfer_fn_idx = 2;
2674 } else {
2675 s->end_transfer_fn_idx = idx;
2676 }
2677 }
2678
2679 static bool ide_drive_pio_state_needed(void *opaque)
2680 {
2681 IDEState *s = opaque;
2682
2683 return ((s->status & DRQ_STAT) != 0)
2684 || (s->bus->error_status & IDE_RETRY_PIO);
2685 }
2686
2687 static bool ide_tray_state_needed(void *opaque)
2688 {
2689 IDEState *s = opaque;
2690
2691 return s->tray_open || s->tray_locked;
2692 }
2693
2694 static bool ide_atapi_gesn_needed(void *opaque)
2695 {
2696 IDEState *s = opaque;
2697
2698 return s->events.new_media || s->events.eject_request;
2699 }
2700
2701 static bool ide_error_needed(void *opaque)
2702 {
2703 IDEBus *bus = opaque;
2704
2705 return (bus->error_status != 0);
2706 }
2707
2708 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2709 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2710 .name ="ide_drive/atapi/gesn_state",
2711 .version_id = 1,
2712 .minimum_version_id = 1,
2713 .needed = ide_atapi_gesn_needed,
2714 .fields = (VMStateField[]) {
2715 VMSTATE_BOOL(events.new_media, IDEState),
2716 VMSTATE_BOOL(events.eject_request, IDEState),
2717 VMSTATE_END_OF_LIST()
2718 }
2719 };
2720
2721 static const VMStateDescription vmstate_ide_tray_state = {
2722 .name = "ide_drive/tray_state",
2723 .version_id = 1,
2724 .minimum_version_id = 1,
2725 .needed = ide_tray_state_needed,
2726 .fields = (VMStateField[]) {
2727 VMSTATE_BOOL(tray_open, IDEState),
2728 VMSTATE_BOOL(tray_locked, IDEState),
2729 VMSTATE_END_OF_LIST()
2730 }
2731 };
2732
2733 static const VMStateDescription vmstate_ide_drive_pio_state = {
2734 .name = "ide_drive/pio_state",
2735 .version_id = 1,
2736 .minimum_version_id = 1,
2737 .pre_save = ide_drive_pio_pre_save,
2738 .post_load = ide_drive_pio_post_load,
2739 .needed = ide_drive_pio_state_needed,
2740 .fields = (VMStateField[]) {
2741 VMSTATE_INT32(req_nb_sectors, IDEState),
2742 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2743 vmstate_info_uint8, uint8_t),
2744 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2745 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2746 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2747 VMSTATE_INT32(elementary_transfer_size, IDEState),
2748 VMSTATE_INT32(packet_transfer_size, IDEState),
2749 VMSTATE_END_OF_LIST()
2750 }
2751 };
2752
2753 const VMStateDescription vmstate_ide_drive = {
2754 .name = "ide_drive",
2755 .version_id = 3,
2756 .minimum_version_id = 0,
2757 .post_load = ide_drive_post_load,
2758 .fields = (VMStateField[]) {
2759 VMSTATE_INT32(mult_sectors, IDEState),
2760 VMSTATE_INT32(identify_set, IDEState),
2761 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2762 VMSTATE_UINT8(feature, IDEState),
2763 VMSTATE_UINT8(error, IDEState),
2764 VMSTATE_UINT32(nsector, IDEState),
2765 VMSTATE_UINT8(sector, IDEState),
2766 VMSTATE_UINT8(lcyl, IDEState),
2767 VMSTATE_UINT8(hcyl, IDEState),
2768 VMSTATE_UINT8(hob_feature, IDEState),
2769 VMSTATE_UINT8(hob_sector, IDEState),
2770 VMSTATE_UINT8(hob_nsector, IDEState),
2771 VMSTATE_UINT8(hob_lcyl, IDEState),
2772 VMSTATE_UINT8(hob_hcyl, IDEState),
2773 VMSTATE_UINT8(select, IDEState),
2774 VMSTATE_UINT8(status, IDEState),
2775 VMSTATE_UINT8(lba48, IDEState),
2776 VMSTATE_UINT8(sense_key, IDEState),
2777 VMSTATE_UINT8(asc, IDEState),
2778 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2779 VMSTATE_END_OF_LIST()
2780 },
2781 .subsections = (const VMStateDescription*[]) {
2782 &vmstate_ide_drive_pio_state,
2783 &vmstate_ide_tray_state,
2784 &vmstate_ide_atapi_gesn_state,
2785 NULL
2786 }
2787 };
2788
2789 static const VMStateDescription vmstate_ide_error_status = {
2790 .name ="ide_bus/error",
2791 .version_id = 2,
2792 .minimum_version_id = 1,
2793 .needed = ide_error_needed,
2794 .fields = (VMStateField[]) {
2795 VMSTATE_INT32(error_status, IDEBus),
2796 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2797 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2798 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
2799 VMSTATE_END_OF_LIST()
2800 }
2801 };
2802
2803 const VMStateDescription vmstate_ide_bus = {
2804 .name = "ide_bus",
2805 .version_id = 1,
2806 .minimum_version_id = 1,
2807 .fields = (VMStateField[]) {
2808 VMSTATE_UINT8(cmd, IDEBus),
2809 VMSTATE_UINT8(unit, IDEBus),
2810 VMSTATE_END_OF_LIST()
2811 },
2812 .subsections = (const VMStateDescription*[]) {
2813 &vmstate_ide_error_status,
2814 NULL
2815 }
2816 };
2817
2818 void ide_drive_get(DriveInfo **hd, int n)
2819 {
2820 int i;
2821 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2822 int max_devs = drive_get_max_devs(IF_IDE);
2823 int n_buses = max_devs ? (n / max_devs) : n;
2824
2825 /*
2826 * Note: The number of actual buses available is not known.
2827 * We compute this based on the size of the DriveInfo* array, n.
2828 * If it is less than max_devs * <num_real_buses>,
2829 * We will stop looking for drives prematurely instead of overfilling
2830 * the array.
2831 */
2832
2833 if (highest_bus > n_buses) {
2834 error_report("Too many IDE buses defined (%d > %d)",
2835 highest_bus, n_buses);
2836 exit(1);
2837 }
2838
2839 for (i = 0; i < n; i++) {
2840 hd[i] = drive_get_by_index(IF_IDE, i);
2841 }
2842 }
QEMU mirror