]> git.proxmox.com Git - mirror_qemu.git/blob - hw/ide/core.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-20151116-1' into staging
[mirror_qemu.git] / hw / ide / core.c
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/block-backend.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify_size(IDEState *s)
79 {
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87 }
88
89 static void ide_identify(IDEState *s)
90 {
91 uint16_t *p;
92 unsigned int oldsize;
93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
94
95 p = (uint16_t *)s->identify_data;
96 if (s->identify_set) {
97 goto fill_buffer;
98 }
99 memset(p, 0, sizeof(s->identify_data));
100
101 put_le16(p + 0, 0x0040);
102 put_le16(p + 1, s->cylinders);
103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
106 put_le16(p + 6, s->sectors);
107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
113 #if MAX_MULT_SECTORS > 1
114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
115 #endif
116 put_le16(p + 48, 1); /* dword I/O */
117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
124 oldsize = s->cylinders * s->heads * s->sectors;
125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
127 if (s->mult_sectors)
128 put_le16(p + 59, 0x100 | s->mult_sectors);
129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
133 put_le16(p + 64, 0x03); /* pio3-4 supported */
134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
161 if (blk_enable_write_cache(s->blk)) {
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 } else {
164 put_le16(p + 85, (1 << 14) | 1);
165 }
166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
169 if (s->wwn) {
170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
171 } else {
172 put_le16(p + 87, (1 << 14) | 0);
173 }
174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
175 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
176 /* *(p + 100) := nb_sectors -- see ide_identify_size */
177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
180
181 if (dev && dev->conf.physical_block_size)
182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
183 if (s->wwn) {
184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
185 put_le16(p + 108, s->wwn >> 48);
186 put_le16(p + 109, s->wwn >> 32);
187 put_le16(p + 110, s->wwn >> 16);
188 put_le16(p + 111, s->wwn);
189 }
190 if (dev && dev->conf.discard_granularity) {
191 put_le16(p + 169, 1); /* TRIM support */
192 }
193
194 ide_identify_size(s);
195 s->identify_set = 1;
196
197 fill_buffer:
198 memcpy(s->io_buffer, p, sizeof(s->identify_data));
199 }
200
201 static void ide_atapi_identify(IDEState *s)
202 {
203 uint16_t *p;
204
205 p = (uint16_t *)s->identify_data;
206 if (s->identify_set) {
207 goto fill_buffer;
208 }
209 memset(p, 0, sizeof(s->identify_data));
210
211 /* Removable CDROM, 50us response, 12 byte packets */
212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
214 put_le16(p + 20, 3); /* buffer type */
215 put_le16(p + 21, 512); /* cache size in sectors */
216 put_le16(p + 22, 4); /* ecc bytes */
217 padstr((char *)(p + 23), s->version, 8); /* firmware version */
218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
220 #ifdef USE_DMA_CDROM
221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
223 put_le16(p + 62, 7); /* single word dma0-2 supported */
224 put_le16(p + 63, 7); /* mdma0-2 supported */
225 #else
226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
229 #endif
230 put_le16(p + 64, 3); /* pio3-4 supported */
231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
235
236 put_le16(p + 71, 30); /* in ns */
237 put_le16(p + 72, 30); /* in ns */
238
239 if (s->ncq_queues) {
240 put_le16(p + 75, s->ncq_queues - 1);
241 /* NCQ supported */
242 put_le16(p + 76, (1 << 8));
243 }
244
245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
246 if (s->wwn) {
247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
248 put_le16(p + 87, (1 << 8)); /* WWN enabled */
249 }
250
251 #ifdef USE_DMA_CDROM
252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
253 #endif
254
255 if (s->wwn) {
256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
257 put_le16(p + 108, s->wwn >> 48);
258 put_le16(p + 109, s->wwn >> 32);
259 put_le16(p + 110, s->wwn >> 16);
260 put_le16(p + 111, s->wwn);
261 }
262
263 s->identify_set = 1;
264
265 fill_buffer:
266 memcpy(s->io_buffer, p, sizeof(s->identify_data));
267 }
268
269 static void ide_cfata_identify_size(IDEState *s)
270 {
271 uint16_t *p = (uint16_t *)s->identify_data;
272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
276 }
277
278 static void ide_cfata_identify(IDEState *s)
279 {
280 uint16_t *p;
281 uint32_t cur_sec;
282
283 p = (uint16_t *)s->identify_data;
284 if (s->identify_set) {
285 goto fill_buffer;
286 }
287 memset(p, 0, sizeof(s->identify_data));
288
289 cur_sec = s->cylinders * s->heads * s->sectors;
290
291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
292 put_le16(p + 1, s->cylinders); /* Default cylinders */
293 put_le16(p + 3, s->heads); /* Default heads */
294 put_le16(p + 6, s->sectors); /* Default sectors per track */
295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
298 put_le16(p + 22, 0x0004); /* ECC bytes */
299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
301 #if MAX_MULT_SECTORS > 1
302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
303 #else
304 put_le16(p + 47, 0x0000);
305 #endif
306 put_le16(p + 49, 0x0f00); /* Capabilities */
307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
309 put_le16(p + 53, 0x0003); /* Translation params valid */
310 put_le16(p + 54, s->cylinders); /* Current cylinders */
311 put_le16(p + 55, s->heads); /* Current heads */
312 put_le16(p + 56, s->sectors); /* Current sectors */
313 put_le16(p + 57, cur_sec); /* Current capacity */
314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
315 if (s->mult_sectors) /* Multiple sector setting */
316 put_le16(p + 59, 0x100 | s->mult_sectors);
317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
324 put_le16(p + 82, 0x400c); /* Command Set supported */
325 put_le16(p + 83, 0x7068); /* Command Set supported */
326 put_le16(p + 84, 0x4000); /* Features supported */
327 put_le16(p + 85, 0x000c); /* Command Set enabled */
328 put_le16(p + 86, 0x7044); /* Command Set enabled */
329 put_le16(p + 87, 0x4000); /* Features enabled */
330 put_le16(p + 91, 0x4060); /* Current APM level */
331 put_le16(p + 129, 0x0002); /* Current features option */
332 put_le16(p + 130, 0x0005); /* Reassigned sectors */
333 put_le16(p + 131, 0x0001); /* Initial power mode */
334 put_le16(p + 132, 0x0000); /* User signature */
335 put_le16(p + 160, 0x8100); /* Power requirement */
336 put_le16(p + 161, 0x8001); /* CF command set */
337
338 ide_cfata_identify_size(s);
339 s->identify_set = 1;
340
341 fill_buffer:
342 memcpy(s->io_buffer, p, sizeof(s->identify_data));
343 }
344
345 static void ide_set_signature(IDEState *s)
346 {
347 s->select &= 0xf0; /* clear head */
348 /* put signature */
349 s->nsector = 1;
350 s->sector = 1;
351 if (s->drive_kind == IDE_CD) {
352 s->lcyl = 0x14;
353 s->hcyl = 0xeb;
354 } else if (s->blk) {
355 s->lcyl = 0;
356 s->hcyl = 0;
357 } else {
358 s->lcyl = 0xff;
359 s->hcyl = 0xff;
360 }
361 }
362
363 typedef struct TrimAIOCB {
364 BlockAIOCB common;
365 BlockBackend *blk;
366 QEMUBH *bh;
367 int ret;
368 QEMUIOVector *qiov;
369 BlockAIOCB *aiocb;
370 int i, j;
371 } TrimAIOCB;
372
373 static void trim_aio_cancel(BlockAIOCB *acb)
374 {
375 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
376
377 /* Exit the loop so ide_issue_trim_cb will not continue */
378 iocb->j = iocb->qiov->niov - 1;
379 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
380
381 iocb->ret = -ECANCELED;
382
383 if (iocb->aiocb) {
384 blk_aio_cancel_async(iocb->aiocb);
385 iocb->aiocb = NULL;
386 }
387 }
388
389 static const AIOCBInfo trim_aiocb_info = {
390 .aiocb_size = sizeof(TrimAIOCB),
391 .cancel_async = trim_aio_cancel,
392 };
393
394 static void ide_trim_bh_cb(void *opaque)
395 {
396 TrimAIOCB *iocb = opaque;
397
398 iocb->common.cb(iocb->common.opaque, iocb->ret);
399
400 qemu_bh_delete(iocb->bh);
401 iocb->bh = NULL;
402 qemu_aio_unref(iocb);
403 }
404
405 static void ide_issue_trim_cb(void *opaque, int ret)
406 {
407 TrimAIOCB *iocb = opaque;
408 if (ret >= 0) {
409 while (iocb->j < iocb->qiov->niov) {
410 int j = iocb->j;
411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
412 int i = iocb->i;
413 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
414
415 /* 6-byte LBA + 2-byte range per entry */
416 uint64_t entry = le64_to_cpu(buffer[i]);
417 uint64_t sector = entry & 0x0000ffffffffffffULL;
418 uint16_t count = entry >> 48;
419
420 if (count == 0) {
421 continue;
422 }
423
424 /* Got an entry! Submit and exit. */
425 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
426 ide_issue_trim_cb, opaque);
427 return;
428 }
429
430 iocb->j++;
431 iocb->i = -1;
432 }
433 } else {
434 iocb->ret = ret;
435 }
436
437 iocb->aiocb = NULL;
438 if (iocb->bh) {
439 qemu_bh_schedule(iocb->bh);
440 }
441 }
442
443 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
445 BlockCompletionFunc *cb, void *opaque)
446 {
447 TrimAIOCB *iocb;
448
449 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
450 iocb->blk = blk;
451 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
452 iocb->ret = 0;
453 iocb->qiov = qiov;
454 iocb->i = -1;
455 iocb->j = 0;
456 ide_issue_trim_cb(iocb, 0);
457 return &iocb->common;
458 }
459
460 void ide_abort_command(IDEState *s)
461 {
462 ide_transfer_stop(s);
463 s->status = READY_STAT | ERR_STAT;
464 s->error = ABRT_ERR;
465 }
466
467 /* prepare data transfer and tell what to do after */
468 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
469 EndTransferFunc *end_transfer_func)
470 {
471 s->end_transfer_func = end_transfer_func;
472 s->data_ptr = buf;
473 s->data_end = buf + size;
474 if (!(s->status & ERR_STAT)) {
475 s->status |= DRQ_STAT;
476 }
477 if (s->bus->dma->ops->start_transfer) {
478 s->bus->dma->ops->start_transfer(s->bus->dma);
479 }
480 }
481
482 static void ide_cmd_done(IDEState *s)
483 {
484 if (s->bus->dma->ops->cmd_done) {
485 s->bus->dma->ops->cmd_done(s->bus->dma);
486 }
487 }
488
489 void ide_transfer_stop(IDEState *s)
490 {
491 s->end_transfer_func = ide_transfer_stop;
492 s->data_ptr = s->io_buffer;
493 s->data_end = s->io_buffer;
494 s->status &= ~DRQ_STAT;
495 ide_cmd_done(s);
496 }
497
498 int64_t ide_get_sector(IDEState *s)
499 {
500 int64_t sector_num;
501 if (s->select & 0x40) {
502 /* lba */
503 if (!s->lba48) {
504 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
505 (s->lcyl << 8) | s->sector;
506 } else {
507 sector_num = ((int64_t)s->hob_hcyl << 40) |
508 ((int64_t) s->hob_lcyl << 32) |
509 ((int64_t) s->hob_sector << 24) |
510 ((int64_t) s->hcyl << 16) |
511 ((int64_t) s->lcyl << 8) | s->sector;
512 }
513 } else {
514 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
515 (s->select & 0x0f) * s->sectors + (s->sector - 1);
516 }
517 return sector_num;
518 }
519
520 void ide_set_sector(IDEState *s, int64_t sector_num)
521 {
522 unsigned int cyl, r;
523 if (s->select & 0x40) {
524 if (!s->lba48) {
525 s->select = (s->select & 0xf0) | (sector_num >> 24);
526 s->hcyl = (sector_num >> 16);
527 s->lcyl = (sector_num >> 8);
528 s->sector = (sector_num);
529 } else {
530 s->sector = sector_num;
531 s->lcyl = sector_num >> 8;
532 s->hcyl = sector_num >> 16;
533 s->hob_sector = sector_num >> 24;
534 s->hob_lcyl = sector_num >> 32;
535 s->hob_hcyl = sector_num >> 40;
536 }
537 } else {
538 cyl = sector_num / (s->heads * s->sectors);
539 r = sector_num % (s->heads * s->sectors);
540 s->hcyl = cyl >> 8;
541 s->lcyl = cyl;
542 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
543 s->sector = (r % s->sectors) + 1;
544 }
545 }
546
547 static void ide_rw_error(IDEState *s) {
548 ide_abort_command(s);
549 ide_set_irq(s->bus);
550 }
551
552 static bool ide_sect_range_ok(IDEState *s,
553 uint64_t sector, uint64_t nb_sectors)
554 {
555 uint64_t total_sectors;
556
557 blk_get_geometry(s->blk, &total_sectors);
558 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
559 return false;
560 }
561 return true;
562 }
563
564 static void ide_sector_read(IDEState *s);
565
566 static void ide_sector_read_cb(void *opaque, int ret)
567 {
568 IDEState *s = opaque;
569 int n;
570
571 s->pio_aiocb = NULL;
572 s->status &= ~BUSY_STAT;
573
574 if (ret == -ECANCELED) {
575 return;
576 }
577 if (ret != 0) {
578 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
579 IDE_RETRY_READ)) {
580 return;
581 }
582 }
583
584 block_acct_done(blk_get_stats(s->blk), &s->acct);
585
586 n = s->nsector;
587 if (n > s->req_nb_sectors) {
588 n = s->req_nb_sectors;
589 }
590
591 ide_set_sector(s, ide_get_sector(s) + n);
592 s->nsector -= n;
593 /* Allow the guest to read the io_buffer */
594 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
595 ide_set_irq(s->bus);
596 }
597
598 static void ide_sector_read(IDEState *s)
599 {
600 int64_t sector_num;
601 int n;
602
603 s->status = READY_STAT | SEEK_STAT;
604 s->error = 0; /* not needed by IDE spec, but needed by Windows */
605 sector_num = ide_get_sector(s);
606 n = s->nsector;
607
608 if (n == 0) {
609 ide_transfer_stop(s);
610 return;
611 }
612
613 s->status |= BUSY_STAT;
614
615 if (n > s->req_nb_sectors) {
616 n = s->req_nb_sectors;
617 }
618
619 #if defined(DEBUG_IDE)
620 printf("sector=%" PRId64 "\n", sector_num);
621 #endif
622
623 if (!ide_sect_range_ok(s, sector_num, n)) {
624 ide_rw_error(s);
625 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
626 return;
627 }
628
629 s->iov.iov_base = s->io_buffer;
630 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
631 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
632
633 block_acct_start(blk_get_stats(s->blk), &s->acct,
634 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
635 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n,
636 ide_sector_read_cb, s);
637 }
638
639 void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
640 {
641 if (s->bus->dma->ops->commit_buf) {
642 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
643 }
644 s->io_buffer_offset += tx_bytes;
645 qemu_sglist_destroy(&s->sg);
646 }
647
648 void ide_set_inactive(IDEState *s, bool more)
649 {
650 s->bus->dma->aiocb = NULL;
651 s->bus->retry_unit = -1;
652 s->bus->retry_sector_num = 0;
653 s->bus->retry_nsector = 0;
654 if (s->bus->dma->ops->set_inactive) {
655 s->bus->dma->ops->set_inactive(s->bus->dma, more);
656 }
657 ide_cmd_done(s);
658 }
659
660 void ide_dma_error(IDEState *s)
661 {
662 dma_buf_commit(s, 0);
663 ide_abort_command(s);
664 ide_set_inactive(s, false);
665 ide_set_irq(s->bus);
666 }
667
668 static int ide_handle_rw_error(IDEState *s, int error, int op)
669 {
670 bool is_read = (op & IDE_RETRY_READ) != 0;
671 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
672
673 if (action == BLOCK_ERROR_ACTION_STOP) {
674 assert(s->bus->retry_unit == s->unit);
675 s->bus->error_status = op;
676 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
677 block_acct_failed(blk_get_stats(s->blk), &s->acct);
678 if (op & IDE_RETRY_DMA) {
679 ide_dma_error(s);
680 } else {
681 ide_rw_error(s);
682 }
683 }
684 blk_error_action(s->blk, action, is_read, error);
685 return action != BLOCK_ERROR_ACTION_IGNORE;
686 }
687
688 static void ide_dma_cb(void *opaque, int ret)
689 {
690 IDEState *s = opaque;
691 int n;
692 int64_t sector_num;
693 bool stay_active = false;
694
695 if (ret == -ECANCELED) {
696 return;
697 }
698 if (ret < 0) {
699 int op = IDE_RETRY_DMA;
700
701 if (s->dma_cmd == IDE_DMA_READ)
702 op |= IDE_RETRY_READ;
703 else if (s->dma_cmd == IDE_DMA_TRIM)
704 op |= IDE_RETRY_TRIM;
705
706 if (ide_handle_rw_error(s, -ret, op)) {
707 return;
708 }
709 }
710
711 n = s->io_buffer_size >> 9;
712 if (n > s->nsector) {
713 /* The PRDs were longer than needed for this request. Shorten them so
714 * we don't get a negative remainder. The Active bit must remain set
715 * after the request completes. */
716 n = s->nsector;
717 stay_active = true;
718 }
719
720 sector_num = ide_get_sector(s);
721 if (n > 0) {
722 assert(n * 512 == s->sg.size);
723 dma_buf_commit(s, s->sg.size);
724 sector_num += n;
725 ide_set_sector(s, sector_num);
726 s->nsector -= n;
727 }
728
729 /* end of transfer ? */
730 if (s->nsector == 0) {
731 s->status = READY_STAT | SEEK_STAT;
732 ide_set_irq(s->bus);
733 goto eot;
734 }
735
736 /* launch next transfer */
737 n = s->nsector;
738 s->io_buffer_index = 0;
739 s->io_buffer_size = n * 512;
740 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
741 /* The PRDs were too short. Reset the Active bit, but don't raise an
742 * interrupt. */
743 s->status = READY_STAT | SEEK_STAT;
744 dma_buf_commit(s, 0);
745 goto eot;
746 }
747
748 #ifdef DEBUG_AIO
749 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
750 sector_num, n, s->dma_cmd);
751 #endif
752
753 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
754 !ide_sect_range_ok(s, sector_num, n)) {
755 ide_dma_error(s);
756 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
757 return;
758 }
759
760 switch (s->dma_cmd) {
761 case IDE_DMA_READ:
762 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
763 ide_dma_cb, s);
764 break;
765 case IDE_DMA_WRITE:
766 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
767 ide_dma_cb, s);
768 break;
769 case IDE_DMA_TRIM:
770 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
771 ide_issue_trim, ide_dma_cb, s,
772 DMA_DIRECTION_TO_DEVICE);
773 break;
774 }
775 return;
776
777 eot:
778 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
779 block_acct_done(blk_get_stats(s->blk), &s->acct);
780 }
781 ide_set_inactive(s, stay_active);
782 }
783
784 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
785 {
786 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
787 s->io_buffer_size = 0;
788 s->dma_cmd = dma_cmd;
789
790 switch (dma_cmd) {
791 case IDE_DMA_READ:
792 block_acct_start(blk_get_stats(s->blk), &s->acct,
793 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
794 break;
795 case IDE_DMA_WRITE:
796 block_acct_start(blk_get_stats(s->blk), &s->acct,
797 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
798 break;
799 default:
800 break;
801 }
802
803 ide_start_dma(s, ide_dma_cb);
804 }
805
806 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
807 {
808 s->io_buffer_index = 0;
809 s->bus->retry_unit = s->unit;
810 s->bus->retry_sector_num = ide_get_sector(s);
811 s->bus->retry_nsector = s->nsector;
812 if (s->bus->dma->ops->start_dma) {
813 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
814 }
815 }
816
817 static void ide_sector_write(IDEState *s);
818
819 static void ide_sector_write_timer_cb(void *opaque)
820 {
821 IDEState *s = opaque;
822 ide_set_irq(s->bus);
823 }
824
825 static void ide_sector_write_cb(void *opaque, int ret)
826 {
827 IDEState *s = opaque;
828 int n;
829
830 if (ret == -ECANCELED) {
831 return;
832 }
833
834 s->pio_aiocb = NULL;
835 s->status &= ~BUSY_STAT;
836
837 if (ret != 0) {
838 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
839 return;
840 }
841 }
842
843 block_acct_done(blk_get_stats(s->blk), &s->acct);
844
845 n = s->nsector;
846 if (n > s->req_nb_sectors) {
847 n = s->req_nb_sectors;
848 }
849 s->nsector -= n;
850
851 ide_set_sector(s, ide_get_sector(s) + n);
852 if (s->nsector == 0) {
853 /* no more sectors to write */
854 ide_transfer_stop(s);
855 } else {
856 int n1 = s->nsector;
857 if (n1 > s->req_nb_sectors) {
858 n1 = s->req_nb_sectors;
859 }
860 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
861 ide_sector_write);
862 }
863
864 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
865 /* It seems there is a bug in the Windows 2000 installer HDD
866 IDE driver which fills the disk with empty logs when the
867 IDE write IRQ comes too early. This hack tries to correct
868 that at the expense of slower write performances. Use this
869 option _only_ to install Windows 2000. You must disable it
870 for normal use. */
871 timer_mod(s->sector_write_timer,
872 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
873 } else {
874 ide_set_irq(s->bus);
875 }
876 }
877
878 static void ide_sector_write(IDEState *s)
879 {
880 int64_t sector_num;
881 int n;
882
883 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
884 sector_num = ide_get_sector(s);
885 #if defined(DEBUG_IDE)
886 printf("sector=%" PRId64 "\n", sector_num);
887 #endif
888 n = s->nsector;
889 if (n > s->req_nb_sectors) {
890 n = s->req_nb_sectors;
891 }
892
893 if (!ide_sect_range_ok(s, sector_num, n)) {
894 ide_rw_error(s);
895 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
896 return;
897 }
898
899 s->iov.iov_base = s->io_buffer;
900 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
901 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
902
903 block_acct_start(blk_get_stats(s->blk), &s->acct,
904 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
905 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
906 ide_sector_write_cb, s);
907 }
908
909 static void ide_flush_cb(void *opaque, int ret)
910 {
911 IDEState *s = opaque;
912
913 s->pio_aiocb = NULL;
914
915 if (ret == -ECANCELED) {
916 return;
917 }
918 if (ret < 0) {
919 /* XXX: What sector number to set here? */
920 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
921 return;
922 }
923 }
924
925 if (s->blk) {
926 block_acct_done(blk_get_stats(s->blk), &s->acct);
927 }
928 s->status = READY_STAT | SEEK_STAT;
929 ide_cmd_done(s);
930 ide_set_irq(s->bus);
931 }
932
933 static void ide_flush_cache(IDEState *s)
934 {
935 if (s->blk == NULL) {
936 ide_flush_cb(s, 0);
937 return;
938 }
939
940 s->status |= BUSY_STAT;
941 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
942 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
943 }
944
945 static void ide_cfata_metadata_inquiry(IDEState *s)
946 {
947 uint16_t *p;
948 uint32_t spd;
949
950 p = (uint16_t *) s->io_buffer;
951 memset(p, 0, 0x200);
952 spd = ((s->mdata_size - 1) >> 9) + 1;
953
954 put_le16(p + 0, 0x0001); /* Data format revision */
955 put_le16(p + 1, 0x0000); /* Media property: silicon */
956 put_le16(p + 2, s->media_changed); /* Media status */
957 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
958 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
959 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
960 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
961 }
962
963 static void ide_cfata_metadata_read(IDEState *s)
964 {
965 uint16_t *p;
966
967 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
968 s->status = ERR_STAT;
969 s->error = ABRT_ERR;
970 return;
971 }
972
973 p = (uint16_t *) s->io_buffer;
974 memset(p, 0, 0x200);
975
976 put_le16(p + 0, s->media_changed); /* Media status */
977 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
978 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
979 s->nsector << 9), 0x200 - 2));
980 }
981
982 static void ide_cfata_metadata_write(IDEState *s)
983 {
984 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
985 s->status = ERR_STAT;
986 s->error = ABRT_ERR;
987 return;
988 }
989
990 s->media_changed = 0;
991
992 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
993 s->io_buffer + 2,
994 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
995 s->nsector << 9), 0x200 - 2));
996 }
997
998 /* called when the inserted state of the media has changed */
999 static void ide_cd_change_cb(void *opaque, bool load)
1000 {
1001 IDEState *s = opaque;
1002 uint64_t nb_sectors;
1003
1004 s->tray_open = !load;
1005 blk_get_geometry(s->blk, &nb_sectors);
1006 s->nb_sectors = nb_sectors;
1007
1008 /*
1009 * First indicate to the guest that a CD has been removed. That's
1010 * done on the next command the guest sends us.
1011 *
1012 * Then we set UNIT_ATTENTION, by which the guest will
1013 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1014 */
1015 s->cdrom_changed = 1;
1016 s->events.new_media = true;
1017 s->events.eject_request = false;
1018 ide_set_irq(s->bus);
1019 }
1020
1021 static void ide_cd_eject_request_cb(void *opaque, bool force)
1022 {
1023 IDEState *s = opaque;
1024
1025 s->events.eject_request = true;
1026 if (force) {
1027 s->tray_locked = false;
1028 }
1029 ide_set_irq(s->bus);
1030 }
1031
1032 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1033 {
1034 s->lba48 = lba48;
1035
1036 /* handle the 'magic' 0 nsector count conversion here. to avoid
1037 * fiddling with the rest of the read logic, we just store the
1038 * full sector count in ->nsector and ignore ->hob_nsector from now
1039 */
1040 if (!s->lba48) {
1041 if (!s->nsector)
1042 s->nsector = 256;
1043 } else {
1044 if (!s->nsector && !s->hob_nsector)
1045 s->nsector = 65536;
1046 else {
1047 int lo = s->nsector;
1048 int hi = s->hob_nsector;
1049
1050 s->nsector = (hi << 8) | lo;
1051 }
1052 }
1053 }
1054
1055 static void ide_clear_hob(IDEBus *bus)
1056 {
1057 /* any write clears HOB high bit of device control register */
1058 bus->ifs[0].select &= ~(1 << 7);
1059 bus->ifs[1].select &= ~(1 << 7);
1060 }
1061
1062 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1063 {
1064 IDEBus *bus = opaque;
1065
1066 #ifdef DEBUG_IDE
1067 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1068 #endif
1069
1070 addr &= 7;
1071
1072 /* ignore writes to command block while busy with previous command */
1073 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1074 return;
1075
1076 switch(addr) {
1077 case 0:
1078 break;
1079 case 1:
1080 ide_clear_hob(bus);
1081 /* NOTE: data is written to the two drives */
1082 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1083 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1084 bus->ifs[0].feature = val;
1085 bus->ifs[1].feature = val;
1086 break;
1087 case 2:
1088 ide_clear_hob(bus);
1089 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1090 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1091 bus->ifs[0].nsector = val;
1092 bus->ifs[1].nsector = val;
1093 break;
1094 case 3:
1095 ide_clear_hob(bus);
1096 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1097 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1098 bus->ifs[0].sector = val;
1099 bus->ifs[1].sector = val;
1100 break;
1101 case 4:
1102 ide_clear_hob(bus);
1103 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1104 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1105 bus->ifs[0].lcyl = val;
1106 bus->ifs[1].lcyl = val;
1107 break;
1108 case 5:
1109 ide_clear_hob(bus);
1110 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1111 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1112 bus->ifs[0].hcyl = val;
1113 bus->ifs[1].hcyl = val;
1114 break;
1115 case 6:
1116 /* FIXME: HOB readback uses bit 7 */
1117 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1118 bus->ifs[1].select = (val | 0x10) | 0xa0;
1119 /* select drive */
1120 bus->unit = (val >> 4) & 1;
1121 break;
1122 default:
1123 case 7:
1124 /* command */
1125 ide_exec_cmd(bus, val);
1126 break;
1127 }
1128 }
1129
1130 static bool cmd_nop(IDEState *s, uint8_t cmd)
1131 {
1132 return true;
1133 }
1134
1135 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1136 {
1137 switch (s->feature) {
1138 case DSM_TRIM:
1139 if (s->blk) {
1140 ide_sector_start_dma(s, IDE_DMA_TRIM);
1141 return false;
1142 }
1143 break;
1144 }
1145
1146 ide_abort_command(s);
1147 return true;
1148 }
1149
1150 static bool cmd_identify(IDEState *s, uint8_t cmd)
1151 {
1152 if (s->blk && s->drive_kind != IDE_CD) {
1153 if (s->drive_kind != IDE_CFATA) {
1154 ide_identify(s);
1155 } else {
1156 ide_cfata_identify(s);
1157 }
1158 s->status = READY_STAT | SEEK_STAT;
1159 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1160 ide_set_irq(s->bus);
1161 return false;
1162 } else {
1163 if (s->drive_kind == IDE_CD) {
1164 ide_set_signature(s);
1165 }
1166 ide_abort_command(s);
1167 }
1168
1169 return true;
1170 }
1171
1172 static bool cmd_verify(IDEState *s, uint8_t cmd)
1173 {
1174 bool lba48 = (cmd == WIN_VERIFY_EXT);
1175
1176 /* do sector number check ? */
1177 ide_cmd_lba48_transform(s, lba48);
1178
1179 return true;
1180 }
1181
1182 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1183 {
1184 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1185 /* Disable Read and Write Multiple */
1186 s->mult_sectors = 0;
1187 } else if ((s->nsector & 0xff) != 0 &&
1188 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1189 (s->nsector & (s->nsector - 1)) != 0)) {
1190 ide_abort_command(s);
1191 } else {
1192 s->mult_sectors = s->nsector & 0xff;
1193 }
1194
1195 return true;
1196 }
1197
1198 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1199 {
1200 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1201
1202 if (!s->blk || !s->mult_sectors) {
1203 ide_abort_command(s);
1204 return true;
1205 }
1206
1207 ide_cmd_lba48_transform(s, lba48);
1208 s->req_nb_sectors = s->mult_sectors;
1209 ide_sector_read(s);
1210 return false;
1211 }
1212
1213 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1214 {
1215 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1216 int n;
1217
1218 if (!s->blk || !s->mult_sectors) {
1219 ide_abort_command(s);
1220 return true;
1221 }
1222
1223 ide_cmd_lba48_transform(s, lba48);
1224
1225 s->req_nb_sectors = s->mult_sectors;
1226 n = MIN(s->nsector, s->req_nb_sectors);
1227
1228 s->status = SEEK_STAT | READY_STAT;
1229 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1230
1231 s->media_changed = 1;
1232
1233 return false;
1234 }
1235
1236 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1237 {
1238 bool lba48 = (cmd == WIN_READ_EXT);
1239
1240 if (s->drive_kind == IDE_CD) {
1241 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1242 ide_abort_command(s);
1243 return true;
1244 }
1245
1246 if (!s->blk) {
1247 ide_abort_command(s);
1248 return true;
1249 }
1250
1251 ide_cmd_lba48_transform(s, lba48);
1252 s->req_nb_sectors = 1;
1253 ide_sector_read(s);
1254
1255 return false;
1256 }
1257
1258 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1259 {
1260 bool lba48 = (cmd == WIN_WRITE_EXT);
1261
1262 if (!s->blk) {
1263 ide_abort_command(s);
1264 return true;
1265 }
1266
1267 ide_cmd_lba48_transform(s, lba48);
1268
1269 s->req_nb_sectors = 1;
1270 s->status = SEEK_STAT | READY_STAT;
1271 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1272
1273 s->media_changed = 1;
1274
1275 return false;
1276 }
1277
1278 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1279 {
1280 bool lba48 = (cmd == WIN_READDMA_EXT);
1281
1282 if (!s->blk) {
1283 ide_abort_command(s);
1284 return true;
1285 }
1286
1287 ide_cmd_lba48_transform(s, lba48);
1288 ide_sector_start_dma(s, IDE_DMA_READ);
1289
1290 return false;
1291 }
1292
1293 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1294 {
1295 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1296
1297 if (!s->blk) {
1298 ide_abort_command(s);
1299 return true;
1300 }
1301
1302 ide_cmd_lba48_transform(s, lba48);
1303 ide_sector_start_dma(s, IDE_DMA_WRITE);
1304
1305 s->media_changed = 1;
1306
1307 return false;
1308 }
1309
1310 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1311 {
1312 ide_flush_cache(s);
1313 return false;
1314 }
1315
1316 static bool cmd_seek(IDEState *s, uint8_t cmd)
1317 {
1318 /* XXX: Check that seek is within bounds */
1319 return true;
1320 }
1321
1322 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1323 {
1324 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1325
1326 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1327 if (s->nb_sectors == 0) {
1328 ide_abort_command(s);
1329 return true;
1330 }
1331
1332 ide_cmd_lba48_transform(s, lba48);
1333 ide_set_sector(s, s->nb_sectors - 1);
1334
1335 return true;
1336 }
1337
1338 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1339 {
1340 s->nsector = 0xff; /* device active or idle */
1341 return true;
1342 }
1343
1344 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1345 {
1346 uint16_t *identify_data;
1347
1348 if (!s->blk) {
1349 ide_abort_command(s);
1350 return true;
1351 }
1352
1353 /* XXX: valid for CDROM ? */
1354 switch (s->feature) {
1355 case 0x02: /* write cache enable */
1356 blk_set_enable_write_cache(s->blk, true);
1357 identify_data = (uint16_t *)s->identify_data;
1358 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1359 return true;
1360 case 0x82: /* write cache disable */
1361 blk_set_enable_write_cache(s->blk, false);
1362 identify_data = (uint16_t *)s->identify_data;
1363 put_le16(identify_data + 85, (1 << 14) | 1);
1364 ide_flush_cache(s);
1365 return false;
1366 case 0xcc: /* reverting to power-on defaults enable */
1367 case 0x66: /* reverting to power-on defaults disable */
1368 case 0xaa: /* read look-ahead enable */
1369 case 0x55: /* read look-ahead disable */
1370 case 0x05: /* set advanced power management mode */
1371 case 0x85: /* disable advanced power management mode */
1372 case 0x69: /* NOP */
1373 case 0x67: /* NOP */
1374 case 0x96: /* NOP */
1375 case 0x9a: /* NOP */
1376 case 0x42: /* enable Automatic Acoustic Mode */
1377 case 0xc2: /* disable Automatic Acoustic Mode */
1378 return true;
1379 case 0x03: /* set transfer mode */
1380 {
1381 uint8_t val = s->nsector & 0x07;
1382 identify_data = (uint16_t *)s->identify_data;
1383
1384 switch (s->nsector >> 3) {
1385 case 0x00: /* pio default */
1386 case 0x01: /* pio mode */
1387 put_le16(identify_data + 62, 0x07);
1388 put_le16(identify_data + 63, 0x07);
1389 put_le16(identify_data + 88, 0x3f);
1390 break;
1391 case 0x02: /* sigle word dma mode*/
1392 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1393 put_le16(identify_data + 63, 0x07);
1394 put_le16(identify_data + 88, 0x3f);
1395 break;
1396 case 0x04: /* mdma mode */
1397 put_le16(identify_data + 62, 0x07);
1398 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1399 put_le16(identify_data + 88, 0x3f);
1400 break;
1401 case 0x08: /* udma mode */
1402 put_le16(identify_data + 62, 0x07);
1403 put_le16(identify_data + 63, 0x07);
1404 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1405 break;
1406 default:
1407 goto abort_cmd;
1408 }
1409 return true;
1410 }
1411 }
1412
1413 abort_cmd:
1414 ide_abort_command(s);
1415 return true;
1416 }
1417
1418
1419 /*** ATAPI commands ***/
1420
1421 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1422 {
1423 ide_atapi_identify(s);
1424 s->status = READY_STAT | SEEK_STAT;
1425 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1426 ide_set_irq(s->bus);
1427 return false;
1428 }
1429
1430 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1431 {
1432 ide_set_signature(s);
1433
1434 if (s->drive_kind == IDE_CD) {
1435 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1436 * devices to return a clear status register
1437 * with READY_STAT *not* set. */
1438 s->error = 0x01;
1439 } else {
1440 s->status = READY_STAT | SEEK_STAT;
1441 /* The bits of the error register are not as usual for this command!
1442 * They are part of the regular output (this is why ERR_STAT isn't set)
1443 * Device 0 passed, Device 1 passed or not present. */
1444 s->error = 0x01;
1445 ide_set_irq(s->bus);
1446 }
1447
1448 return false;
1449 }
1450
1451 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1452 {
1453 ide_set_signature(s);
1454 s->status = 0x00; /* NOTE: READY is _not_ set */
1455 s->error = 0x01;
1456
1457 return false;
1458 }
1459
1460 static bool cmd_packet(IDEState *s, uint8_t cmd)
1461 {
1462 /* overlapping commands not supported */
1463 if (s->feature & 0x02) {
1464 ide_abort_command(s);
1465 return true;
1466 }
1467
1468 s->status = READY_STAT | SEEK_STAT;
1469 s->atapi_dma = s->feature & 1;
1470 s->nsector = 1;
1471 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1472 ide_atapi_cmd);
1473 return false;
1474 }
1475
1476
1477 /*** CF-ATA commands ***/
1478
1479 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1480 {
1481 s->error = 0x09; /* miscellaneous error */
1482 s->status = READY_STAT | SEEK_STAT;
1483 ide_set_irq(s->bus);
1484
1485 return false;
1486 }
1487
1488 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1489 {
1490 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1491 * required for Windows 8 to work with AHCI */
1492
1493 if (cmd == CFA_WEAR_LEVEL) {
1494 s->nsector = 0;
1495 }
1496
1497 if (cmd == CFA_ERASE_SECTORS) {
1498 s->media_changed = 1;
1499 }
1500
1501 return true;
1502 }
1503
1504 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1505 {
1506 s->status = READY_STAT | SEEK_STAT;
1507
1508 memset(s->io_buffer, 0, 0x200);
1509 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1510 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1511 s->io_buffer[0x02] = s->select; /* Head */
1512 s->io_buffer[0x03] = s->sector; /* Sector */
1513 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1514 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1515 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1516 s->io_buffer[0x13] = 0x00; /* Erase flag */
1517 s->io_buffer[0x18] = 0x00; /* Hot count */
1518 s->io_buffer[0x19] = 0x00; /* Hot count */
1519 s->io_buffer[0x1a] = 0x01; /* Hot count */
1520
1521 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1522 ide_set_irq(s->bus);
1523
1524 return false;
1525 }
1526
1527 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1528 {
1529 switch (s->feature) {
1530 case 0x02: /* Inquiry Metadata Storage */
1531 ide_cfata_metadata_inquiry(s);
1532 break;
1533 case 0x03: /* Read Metadata Storage */
1534 ide_cfata_metadata_read(s);
1535 break;
1536 case 0x04: /* Write Metadata Storage */
1537 ide_cfata_metadata_write(s);
1538 break;
1539 default:
1540 ide_abort_command(s);
1541 return true;
1542 }
1543
1544 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1545 s->status = 0x00; /* NOTE: READY is _not_ set */
1546 ide_set_irq(s->bus);
1547
1548 return false;
1549 }
1550
1551 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1552 {
1553 switch (s->feature) {
1554 case 0x01: /* sense temperature in device */
1555 s->nsector = 0x50; /* +20 C */
1556 break;
1557 default:
1558 ide_abort_command(s);
1559 return true;
1560 }
1561
1562 return true;
1563 }
1564
1565
1566 /*** SMART commands ***/
1567
1568 static bool cmd_smart(IDEState *s, uint8_t cmd)
1569 {
1570 int n;
1571
1572 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1573 goto abort_cmd;
1574 }
1575
1576 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1577 goto abort_cmd;
1578 }
1579
1580 switch (s->feature) {
1581 case SMART_DISABLE:
1582 s->smart_enabled = 0;
1583 return true;
1584
1585 case SMART_ENABLE:
1586 s->smart_enabled = 1;
1587 return true;
1588
1589 case SMART_ATTR_AUTOSAVE:
1590 switch (s->sector) {
1591 case 0x00:
1592 s->smart_autosave = 0;
1593 break;
1594 case 0xf1:
1595 s->smart_autosave = 1;
1596 break;
1597 default:
1598 goto abort_cmd;
1599 }
1600 return true;
1601
1602 case SMART_STATUS:
1603 if (!s->smart_errors) {
1604 s->hcyl = 0xc2;
1605 s->lcyl = 0x4f;
1606 } else {
1607 s->hcyl = 0x2c;
1608 s->lcyl = 0xf4;
1609 }
1610 return true;
1611
1612 case SMART_READ_THRESH:
1613 memset(s->io_buffer, 0, 0x200);
1614 s->io_buffer[0] = 0x01; /* smart struct version */
1615
1616 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1617 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1618 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1619 }
1620
1621 /* checksum */
1622 for (n = 0; n < 511; n++) {
1623 s->io_buffer[511] += s->io_buffer[n];
1624 }
1625 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1626
1627 s->status = READY_STAT | SEEK_STAT;
1628 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1629 ide_set_irq(s->bus);
1630 return false;
1631
1632 case SMART_READ_DATA:
1633 memset(s->io_buffer, 0, 0x200);
1634 s->io_buffer[0] = 0x01; /* smart struct version */
1635
1636 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1637 int i;
1638 for (i = 0; i < 11; i++) {
1639 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1640 }
1641 }
1642
1643 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1644 if (s->smart_selftest_count == 0) {
1645 s->io_buffer[363] = 0;
1646 } else {
1647 s->io_buffer[363] =
1648 s->smart_selftest_data[3 +
1649 (s->smart_selftest_count - 1) *
1650 24];
1651 }
1652 s->io_buffer[364] = 0x20;
1653 s->io_buffer[365] = 0x01;
1654 /* offline data collection capacity: execute + self-test*/
1655 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1656 s->io_buffer[368] = 0x03; /* smart capability (1) */
1657 s->io_buffer[369] = 0x00; /* smart capability (2) */
1658 s->io_buffer[370] = 0x01; /* error logging supported */
1659 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1660 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1661 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1662
1663 for (n = 0; n < 511; n++) {
1664 s->io_buffer[511] += s->io_buffer[n];
1665 }
1666 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1667
1668 s->status = READY_STAT | SEEK_STAT;
1669 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1670 ide_set_irq(s->bus);
1671 return false;
1672
1673 case SMART_READ_LOG:
1674 switch (s->sector) {
1675 case 0x01: /* summary smart error log */
1676 memset(s->io_buffer, 0, 0x200);
1677 s->io_buffer[0] = 0x01;
1678 s->io_buffer[1] = 0x00; /* no error entries */
1679 s->io_buffer[452] = s->smart_errors & 0xff;
1680 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1681
1682 for (n = 0; n < 511; n++) {
1683 s->io_buffer[511] += s->io_buffer[n];
1684 }
1685 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1686 break;
1687 case 0x06: /* smart self test log */
1688 memset(s->io_buffer, 0, 0x200);
1689 s->io_buffer[0] = 0x01;
1690 if (s->smart_selftest_count == 0) {
1691 s->io_buffer[508] = 0;
1692 } else {
1693 s->io_buffer[508] = s->smart_selftest_count;
1694 for (n = 2; n < 506; n++) {
1695 s->io_buffer[n] = s->smart_selftest_data[n];
1696 }
1697 }
1698
1699 for (n = 0; n < 511; n++) {
1700 s->io_buffer[511] += s->io_buffer[n];
1701 }
1702 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1703 break;
1704 default:
1705 goto abort_cmd;
1706 }
1707 s->status = READY_STAT | SEEK_STAT;
1708 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1709 ide_set_irq(s->bus);
1710 return false;
1711
1712 case SMART_EXECUTE_OFFLINE:
1713 switch (s->sector) {
1714 case 0: /* off-line routine */
1715 case 1: /* short self test */
1716 case 2: /* extended self test */
1717 s->smart_selftest_count++;
1718 if (s->smart_selftest_count > 21) {
1719 s->smart_selftest_count = 1;
1720 }
1721 n = 2 + (s->smart_selftest_count - 1) * 24;
1722 s->smart_selftest_data[n] = s->sector;
1723 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1724 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1725 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1726 break;
1727 default:
1728 goto abort_cmd;
1729 }
1730 return true;
1731 }
1732
1733 abort_cmd:
1734 ide_abort_command(s);
1735 return true;
1736 }
1737
1738 #define HD_OK (1u << IDE_HD)
1739 #define CD_OK (1u << IDE_CD)
1740 #define CFA_OK (1u << IDE_CFATA)
1741 #define HD_CFA_OK (HD_OK | CFA_OK)
1742 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1743
1744 /* Set the Disk Seek Completed status bit during completion */
1745 #define SET_DSC (1u << 8)
1746
1747 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1748 static const struct {
1749 /* Returns true if the completion code should be run */
1750 bool (*handler)(IDEState *s, uint8_t cmd);
1751 int flags;
1752 } ide_cmd_table[0x100] = {
1753 /* NOP not implemented, mandatory for CD */
1754 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1755 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
1756 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1757 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1758 [WIN_READ] = { cmd_read_pio, ALL_OK },
1759 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
1760 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1761 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1762 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1763 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1764 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1765 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1766 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1767 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1768 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1769 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1770 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1771 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1772 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1773 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1774 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1775 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1776 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1777 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1778 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1779 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1780 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1781 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1782 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1783 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
1784 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1785 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1786 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1787 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1788 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1789 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1790 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1791 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1792 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1793 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1794 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1795 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1796 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1797 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1798 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1799 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1800 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1801 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1802 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
1803 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1804 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1805 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1806 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1807 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1808 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1809 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1810 };
1811
1812 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1813 {
1814 return cmd < ARRAY_SIZE(ide_cmd_table)
1815 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1816 }
1817
1818 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1819 {
1820 IDEState *s;
1821 bool complete;
1822
1823 #if defined(DEBUG_IDE)
1824 printf("ide: CMD=%02x\n", val);
1825 #endif
1826 s = idebus_active_if(bus);
1827 /* ignore commands to non existent slave */
1828 if (s != bus->ifs && !s->blk) {
1829 return;
1830 }
1831
1832 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1833 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1834 return;
1835
1836 if (!ide_cmd_permitted(s, val)) {
1837 ide_abort_command(s);
1838 ide_set_irq(s->bus);
1839 return;
1840 }
1841
1842 s->status = READY_STAT | BUSY_STAT;
1843 s->error = 0;
1844 s->io_buffer_offset = 0;
1845
1846 complete = ide_cmd_table[val].handler(s, val);
1847 if (complete) {
1848 s->status &= ~BUSY_STAT;
1849 assert(!!s->error == !!(s->status & ERR_STAT));
1850
1851 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1852 s->status |= SEEK_STAT;
1853 }
1854
1855 ide_cmd_done(s);
1856 ide_set_irq(s->bus);
1857 }
1858 }
1859
1860 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1861 {
1862 IDEBus *bus = opaque;
1863 IDEState *s = idebus_active_if(bus);
1864 uint32_t addr;
1865 int ret, hob;
1866
1867 addr = addr1 & 7;
1868 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1869 //hob = s->select & (1 << 7);
1870 hob = 0;
1871 switch(addr) {
1872 case 0:
1873 ret = 0xff;
1874 break;
1875 case 1:
1876 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1877 (s != bus->ifs && !s->blk)) {
1878 ret = 0;
1879 } else if (!hob) {
1880 ret = s->error;
1881 } else {
1882 ret = s->hob_feature;
1883 }
1884 break;
1885 case 2:
1886 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1887 ret = 0;
1888 } else if (!hob) {
1889 ret = s->nsector & 0xff;
1890 } else {
1891 ret = s->hob_nsector;
1892 }
1893 break;
1894 case 3:
1895 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1896 ret = 0;
1897 } else if (!hob) {
1898 ret = s->sector;
1899 } else {
1900 ret = s->hob_sector;
1901 }
1902 break;
1903 case 4:
1904 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1905 ret = 0;
1906 } else if (!hob) {
1907 ret = s->lcyl;
1908 } else {
1909 ret = s->hob_lcyl;
1910 }
1911 break;
1912 case 5:
1913 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1914 ret = 0;
1915 } else if (!hob) {
1916 ret = s->hcyl;
1917 } else {
1918 ret = s->hob_hcyl;
1919 }
1920 break;
1921 case 6:
1922 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1923 ret = 0;
1924 } else {
1925 ret = s->select;
1926 }
1927 break;
1928 default:
1929 case 7:
1930 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1931 (s != bus->ifs && !s->blk)) {
1932 ret = 0;
1933 } else {
1934 ret = s->status;
1935 }
1936 qemu_irq_lower(bus->irq);
1937 break;
1938 }
1939 #ifdef DEBUG_IDE
1940 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1941 #endif
1942 return ret;
1943 }
1944
1945 uint32_t ide_status_read(void *opaque, uint32_t addr)
1946 {
1947 IDEBus *bus = opaque;
1948 IDEState *s = idebus_active_if(bus);
1949 int ret;
1950
1951 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1952 (s != bus->ifs && !s->blk)) {
1953 ret = 0;
1954 } else {
1955 ret = s->status;
1956 }
1957 #ifdef DEBUG_IDE
1958 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1959 #endif
1960 return ret;
1961 }
1962
1963 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1964 {
1965 IDEBus *bus = opaque;
1966 IDEState *s;
1967 int i;
1968
1969 #ifdef DEBUG_IDE
1970 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1971 #endif
1972 /* common for both drives */
1973 if (!(bus->cmd & IDE_CMD_RESET) &&
1974 (val & IDE_CMD_RESET)) {
1975 /* reset low to high */
1976 for(i = 0;i < 2; i++) {
1977 s = &bus->ifs[i];
1978 s->status = BUSY_STAT | SEEK_STAT;
1979 s->error = 0x01;
1980 }
1981 } else if ((bus->cmd & IDE_CMD_RESET) &&
1982 !(val & IDE_CMD_RESET)) {
1983 /* high to low */
1984 for(i = 0;i < 2; i++) {
1985 s = &bus->ifs[i];
1986 if (s->drive_kind == IDE_CD)
1987 s->status = 0x00; /* NOTE: READY is _not_ set */
1988 else
1989 s->status = READY_STAT | SEEK_STAT;
1990 ide_set_signature(s);
1991 }
1992 }
1993
1994 bus->cmd = val;
1995 }
1996
1997 /*
1998 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1999 * transferred from the device to the guest), false if it's a PIO in
2000 */
2001 static bool ide_is_pio_out(IDEState *s)
2002 {
2003 if (s->end_transfer_func == ide_sector_write ||
2004 s->end_transfer_func == ide_atapi_cmd) {
2005 return false;
2006 } else if (s->end_transfer_func == ide_sector_read ||
2007 s->end_transfer_func == ide_transfer_stop ||
2008 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2009 s->end_transfer_func == ide_dummy_transfer_stop) {
2010 return true;
2011 }
2012
2013 abort();
2014 }
2015
2016 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2017 {
2018 IDEBus *bus = opaque;
2019 IDEState *s = idebus_active_if(bus);
2020 uint8_t *p;
2021
2022 /* PIO data access allowed only when DRQ bit is set. The result of a write
2023 * during PIO out is indeterminate, just ignore it. */
2024 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2025 return;
2026 }
2027
2028 p = s->data_ptr;
2029 if (p + 2 > s->data_end) {
2030 return;
2031 }
2032
2033 *(uint16_t *)p = le16_to_cpu(val);
2034 p += 2;
2035 s->data_ptr = p;
2036 if (p >= s->data_end) {
2037 s->status &= ~DRQ_STAT;
2038 s->end_transfer_func(s);
2039 }
2040 }
2041
2042 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2043 {
2044 IDEBus *bus = opaque;
2045 IDEState *s = idebus_active_if(bus);
2046 uint8_t *p;
2047 int ret;
2048
2049 /* PIO data access allowed only when DRQ bit is set. The result of a read
2050 * during PIO in is indeterminate, return 0 and don't move forward. */
2051 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2052 return 0;
2053 }
2054
2055 p = s->data_ptr;
2056 if (p + 2 > s->data_end) {
2057 return 0;
2058 }
2059
2060 ret = cpu_to_le16(*(uint16_t *)p);
2061 p += 2;
2062 s->data_ptr = p;
2063 if (p >= s->data_end) {
2064 s->status &= ~DRQ_STAT;
2065 s->end_transfer_func(s);
2066 }
2067 return ret;
2068 }
2069
2070 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2071 {
2072 IDEBus *bus = opaque;
2073 IDEState *s = idebus_active_if(bus);
2074 uint8_t *p;
2075
2076 /* PIO data access allowed only when DRQ bit is set. The result of a write
2077 * during PIO out is indeterminate, just ignore it. */
2078 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2079 return;
2080 }
2081
2082 p = s->data_ptr;
2083 if (p + 4 > s->data_end) {
2084 return;
2085 }
2086
2087 *(uint32_t *)p = le32_to_cpu(val);
2088 p += 4;
2089 s->data_ptr = p;
2090 if (p >= s->data_end) {
2091 s->status &= ~DRQ_STAT;
2092 s->end_transfer_func(s);
2093 }
2094 }
2095
2096 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2097 {
2098 IDEBus *bus = opaque;
2099 IDEState *s = idebus_active_if(bus);
2100 uint8_t *p;
2101 int ret;
2102
2103 /* PIO data access allowed only when DRQ bit is set. The result of a read
2104 * during PIO in is indeterminate, return 0 and don't move forward. */
2105 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2106 return 0;
2107 }
2108
2109 p = s->data_ptr;
2110 if (p + 4 > s->data_end) {
2111 return 0;
2112 }
2113
2114 ret = cpu_to_le32(*(uint32_t *)p);
2115 p += 4;
2116 s->data_ptr = p;
2117 if (p >= s->data_end) {
2118 s->status &= ~DRQ_STAT;
2119 s->end_transfer_func(s);
2120 }
2121 return ret;
2122 }
2123
2124 static void ide_dummy_transfer_stop(IDEState *s)
2125 {
2126 s->data_ptr = s->io_buffer;
2127 s->data_end = s->io_buffer;
2128 s->io_buffer[0] = 0xff;
2129 s->io_buffer[1] = 0xff;
2130 s->io_buffer[2] = 0xff;
2131 s->io_buffer[3] = 0xff;
2132 }
2133
2134 static void ide_reset(IDEState *s)
2135 {
2136 #ifdef DEBUG_IDE
2137 printf("ide: reset\n");
2138 #endif
2139
2140 if (s->pio_aiocb) {
2141 blk_aio_cancel(s->pio_aiocb);
2142 s->pio_aiocb = NULL;
2143 }
2144
2145 if (s->drive_kind == IDE_CFATA)
2146 s->mult_sectors = 0;
2147 else
2148 s->mult_sectors = MAX_MULT_SECTORS;
2149 /* ide regs */
2150 s->feature = 0;
2151 s->error = 0;
2152 s->nsector = 0;
2153 s->sector = 0;
2154 s->lcyl = 0;
2155 s->hcyl = 0;
2156
2157 /* lba48 */
2158 s->hob_feature = 0;
2159 s->hob_sector = 0;
2160 s->hob_nsector = 0;
2161 s->hob_lcyl = 0;
2162 s->hob_hcyl = 0;
2163
2164 s->select = 0xa0;
2165 s->status = READY_STAT | SEEK_STAT;
2166
2167 s->lba48 = 0;
2168
2169 /* ATAPI specific */
2170 s->sense_key = 0;
2171 s->asc = 0;
2172 s->cdrom_changed = 0;
2173 s->packet_transfer_size = 0;
2174 s->elementary_transfer_size = 0;
2175 s->io_buffer_index = 0;
2176 s->cd_sector_size = 0;
2177 s->atapi_dma = 0;
2178 s->tray_locked = 0;
2179 s->tray_open = 0;
2180 /* ATA DMA state */
2181 s->io_buffer_size = 0;
2182 s->req_nb_sectors = 0;
2183
2184 ide_set_signature(s);
2185 /* init the transfer handler so that 0xffff is returned on data
2186 accesses */
2187 s->end_transfer_func = ide_dummy_transfer_stop;
2188 ide_dummy_transfer_stop(s);
2189 s->media_changed = 0;
2190 }
2191
2192 void ide_bus_reset(IDEBus *bus)
2193 {
2194 bus->unit = 0;
2195 bus->cmd = 0;
2196 ide_reset(&bus->ifs[0]);
2197 ide_reset(&bus->ifs[1]);
2198 ide_clear_hob(bus);
2199
2200 /* pending async DMA */
2201 if (bus->dma->aiocb) {
2202 #ifdef DEBUG_AIO
2203 printf("aio_cancel\n");
2204 #endif
2205 blk_aio_cancel(bus->dma->aiocb);
2206 bus->dma->aiocb = NULL;
2207 }
2208
2209 /* reset dma provider too */
2210 if (bus->dma->ops->reset) {
2211 bus->dma->ops->reset(bus->dma);
2212 }
2213 }
2214
2215 static bool ide_cd_is_tray_open(void *opaque)
2216 {
2217 return ((IDEState *)opaque)->tray_open;
2218 }
2219
2220 static bool ide_cd_is_medium_locked(void *opaque)
2221 {
2222 return ((IDEState *)opaque)->tray_locked;
2223 }
2224
2225 static void ide_resize_cb(void *opaque)
2226 {
2227 IDEState *s = opaque;
2228 uint64_t nb_sectors;
2229
2230 if (!s->identify_set) {
2231 return;
2232 }
2233
2234 blk_get_geometry(s->blk, &nb_sectors);
2235 s->nb_sectors = nb_sectors;
2236
2237 /* Update the identify data buffer. */
2238 if (s->drive_kind == IDE_CFATA) {
2239 ide_cfata_identify_size(s);
2240 } else {
2241 /* IDE_CD uses a different set of callbacks entirely. */
2242 assert(s->drive_kind != IDE_CD);
2243 ide_identify_size(s);
2244 }
2245 }
2246
2247 static const BlockDevOps ide_cd_block_ops = {
2248 .change_media_cb = ide_cd_change_cb,
2249 .eject_request_cb = ide_cd_eject_request_cb,
2250 .is_tray_open = ide_cd_is_tray_open,
2251 .is_medium_locked = ide_cd_is_medium_locked,
2252 };
2253
2254 static const BlockDevOps ide_hd_block_ops = {
2255 .resize_cb = ide_resize_cb,
2256 };
2257
2258 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2259 const char *version, const char *serial, const char *model,
2260 uint64_t wwn,
2261 uint32_t cylinders, uint32_t heads, uint32_t secs,
2262 int chs_trans)
2263 {
2264 uint64_t nb_sectors;
2265
2266 s->blk = blk;
2267 s->drive_kind = kind;
2268
2269 blk_get_geometry(blk, &nb_sectors);
2270 s->cylinders = cylinders;
2271 s->heads = heads;
2272 s->sectors = secs;
2273 s->chs_trans = chs_trans;
2274 s->nb_sectors = nb_sectors;
2275 s->wwn = wwn;
2276 /* The SMART values should be preserved across power cycles
2277 but they aren't. */
2278 s->smart_enabled = 1;
2279 s->smart_autosave = 1;
2280 s->smart_errors = 0;
2281 s->smart_selftest_count = 0;
2282 if (kind == IDE_CD) {
2283 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2284 blk_set_guest_block_size(blk, 2048);
2285 } else {
2286 if (!blk_is_inserted(s->blk)) {
2287 error_report("Device needs media, but drive is empty");
2288 return -1;
2289 }
2290 if (blk_is_read_only(blk)) {
2291 error_report("Can't use a read-only drive");
2292 return -1;
2293 }
2294 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2295 }
2296 if (serial) {
2297 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2298 } else {
2299 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2300 "QM%05d", s->drive_serial);
2301 }
2302 if (model) {
2303 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2304 } else {
2305 switch (kind) {
2306 case IDE_CD:
2307 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2308 break;
2309 case IDE_CFATA:
2310 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2311 break;
2312 default:
2313 strcpy(s->drive_model_str, "QEMU HARDDISK");
2314 break;
2315 }
2316 }
2317
2318 if (version) {
2319 pstrcpy(s->version, sizeof(s->version), version);
2320 } else {
2321 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
2322 }
2323
2324 ide_reset(s);
2325 blk_iostatus_enable(blk);
2326 return 0;
2327 }
2328
2329 static void ide_init1(IDEBus *bus, int unit)
2330 {
2331 static int drive_serial = 1;
2332 IDEState *s = &bus->ifs[unit];
2333
2334 s->bus = bus;
2335 s->unit = unit;
2336 s->drive_serial = drive_serial++;
2337 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2338 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2339 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2340 memset(s->io_buffer, 0, s->io_buffer_total_len);
2341
2342 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2343 memset(s->smart_selftest_data, 0, 512);
2344
2345 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2346 ide_sector_write_timer_cb, s);
2347 }
2348
2349 static int ide_nop_int(IDEDMA *dma, int x)
2350 {
2351 return 0;
2352 }
2353
2354 static void ide_nop(IDEDMA *dma)
2355 {
2356 }
2357
2358 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
2359 {
2360 return 0;
2361 }
2362
2363 static const IDEDMAOps ide_dma_nop_ops = {
2364 .prepare_buf = ide_nop_int32,
2365 .restart_dma = ide_nop,
2366 .rw_buf = ide_nop_int,
2367 };
2368
2369 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2370 {
2371 s->unit = s->bus->retry_unit;
2372 ide_set_sector(s, s->bus->retry_sector_num);
2373 s->nsector = s->bus->retry_nsector;
2374 s->bus->dma->ops->restart_dma(s->bus->dma);
2375 s->io_buffer_size = 0;
2376 s->dma_cmd = dma_cmd;
2377 ide_start_dma(s, ide_dma_cb);
2378 }
2379
2380 static void ide_restart_bh(void *opaque)
2381 {
2382 IDEBus *bus = opaque;
2383 IDEState *s;
2384 bool is_read;
2385 int error_status;
2386
2387 qemu_bh_delete(bus->bh);
2388 bus->bh = NULL;
2389
2390 error_status = bus->error_status;
2391 if (bus->error_status == 0) {
2392 return;
2393 }
2394
2395 s = idebus_active_if(bus);
2396 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2397
2398 /* The error status must be cleared before resubmitting the request: The
2399 * request may fail again, and this case can only be distinguished if the
2400 * called function can set a new error status. */
2401 bus->error_status = 0;
2402
2403 /* The HBA has generically asked to be kicked on retry */
2404 if (error_status & IDE_RETRY_HBA) {
2405 if (s->bus->dma->ops->restart) {
2406 s->bus->dma->ops->restart(s->bus->dma);
2407 }
2408 }
2409
2410 if (error_status & IDE_RETRY_DMA) {
2411 if (error_status & IDE_RETRY_TRIM) {
2412 ide_restart_dma(s, IDE_DMA_TRIM);
2413 } else {
2414 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2415 }
2416 } else if (error_status & IDE_RETRY_PIO) {
2417 if (is_read) {
2418 ide_sector_read(s);
2419 } else {
2420 ide_sector_write(s);
2421 }
2422 } else if (error_status & IDE_RETRY_FLUSH) {
2423 ide_flush_cache(s);
2424 } else {
2425 /*
2426 * We've not got any bits to tell us about ATAPI - but
2427 * we do have the end_transfer_func that tells us what
2428 * we're trying to do.
2429 */
2430 if (s->end_transfer_func == ide_atapi_cmd) {
2431 ide_atapi_dma_restart(s);
2432 }
2433 }
2434 }
2435
2436 static void ide_restart_cb(void *opaque, int running, RunState state)
2437 {
2438 IDEBus *bus = opaque;
2439
2440 if (!running)
2441 return;
2442
2443 if (!bus->bh) {
2444 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2445 qemu_bh_schedule(bus->bh);
2446 }
2447 }
2448
2449 void ide_register_restart_cb(IDEBus *bus)
2450 {
2451 if (bus->dma->ops->restart_dma) {
2452 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2453 }
2454 }
2455
2456 static IDEDMA ide_dma_nop = {
2457 .ops = &ide_dma_nop_ops,
2458 .aiocb = NULL,
2459 };
2460
2461 void ide_init2(IDEBus *bus, qemu_irq irq)
2462 {
2463 int i;
2464
2465 for(i = 0; i < 2; i++) {
2466 ide_init1(bus, i);
2467 ide_reset(&bus->ifs[i]);
2468 }
2469 bus->irq = irq;
2470 bus->dma = &ide_dma_nop;
2471 }
2472
2473 static const MemoryRegionPortio ide_portio_list[] = {
2474 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2475 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2476 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
2477 PORTIO_END_OF_LIST(),
2478 };
2479
2480 static const MemoryRegionPortio ide_portio2_list[] = {
2481 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2482 PORTIO_END_OF_LIST(),
2483 };
2484
2485 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2486 {
2487 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2488 bridge has been setup properly to always register with ISA. */
2489 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2490
2491 if (iobase2) {
2492 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2493 }
2494 }
2495
2496 static bool is_identify_set(void *opaque, int version_id)
2497 {
2498 IDEState *s = opaque;
2499
2500 return s->identify_set != 0;
2501 }
2502
2503 static EndTransferFunc* transfer_end_table[] = {
2504 ide_sector_read,
2505 ide_sector_write,
2506 ide_transfer_stop,
2507 ide_atapi_cmd_reply_end,
2508 ide_atapi_cmd,
2509 ide_dummy_transfer_stop,
2510 };
2511
2512 static int transfer_end_table_idx(EndTransferFunc *fn)
2513 {
2514 int i;
2515
2516 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2517 if (transfer_end_table[i] == fn)
2518 return i;
2519
2520 return -1;
2521 }
2522
2523 static int ide_drive_post_load(void *opaque, int version_id)
2524 {
2525 IDEState *s = opaque;
2526
2527 if (s->blk && s->identify_set) {
2528 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2529 }
2530 return 0;
2531 }
2532
2533 static int ide_drive_pio_post_load(void *opaque, int version_id)
2534 {
2535 IDEState *s = opaque;
2536
2537 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2538 return -EINVAL;
2539 }
2540 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2541 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2542 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2543 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
2544
2545 return 0;
2546 }
2547
2548 static void ide_drive_pio_pre_save(void *opaque)
2549 {
2550 IDEState *s = opaque;
2551 int idx;
2552
2553 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2554 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2555
2556 idx = transfer_end_table_idx(s->end_transfer_func);
2557 if (idx == -1) {
2558 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2559 __func__);
2560 s->end_transfer_fn_idx = 2;
2561 } else {
2562 s->end_transfer_fn_idx = idx;
2563 }
2564 }
2565
2566 static bool ide_drive_pio_state_needed(void *opaque)
2567 {
2568 IDEState *s = opaque;
2569
2570 return ((s->status & DRQ_STAT) != 0)
2571 || (s->bus->error_status & IDE_RETRY_PIO);
2572 }
2573
2574 static bool ide_tray_state_needed(void *opaque)
2575 {
2576 IDEState *s = opaque;
2577
2578 return s->tray_open || s->tray_locked;
2579 }
2580
2581 static bool ide_atapi_gesn_needed(void *opaque)
2582 {
2583 IDEState *s = opaque;
2584
2585 return s->events.new_media || s->events.eject_request;
2586 }
2587
2588 static bool ide_error_needed(void *opaque)
2589 {
2590 IDEBus *bus = opaque;
2591
2592 return (bus->error_status != 0);
2593 }
2594
2595 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2596 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2597 .name ="ide_drive/atapi/gesn_state",
2598 .version_id = 1,
2599 .minimum_version_id = 1,
2600 .needed = ide_atapi_gesn_needed,
2601 .fields = (VMStateField[]) {
2602 VMSTATE_BOOL(events.new_media, IDEState),
2603 VMSTATE_BOOL(events.eject_request, IDEState),
2604 VMSTATE_END_OF_LIST()
2605 }
2606 };
2607
2608 static const VMStateDescription vmstate_ide_tray_state = {
2609 .name = "ide_drive/tray_state",
2610 .version_id = 1,
2611 .minimum_version_id = 1,
2612 .needed = ide_tray_state_needed,
2613 .fields = (VMStateField[]) {
2614 VMSTATE_BOOL(tray_open, IDEState),
2615 VMSTATE_BOOL(tray_locked, IDEState),
2616 VMSTATE_END_OF_LIST()
2617 }
2618 };
2619
2620 static const VMStateDescription vmstate_ide_drive_pio_state = {
2621 .name = "ide_drive/pio_state",
2622 .version_id = 1,
2623 .minimum_version_id = 1,
2624 .pre_save = ide_drive_pio_pre_save,
2625 .post_load = ide_drive_pio_post_load,
2626 .needed = ide_drive_pio_state_needed,
2627 .fields = (VMStateField[]) {
2628 VMSTATE_INT32(req_nb_sectors, IDEState),
2629 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2630 vmstate_info_uint8, uint8_t),
2631 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2632 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2633 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2634 VMSTATE_INT32(elementary_transfer_size, IDEState),
2635 VMSTATE_INT32(packet_transfer_size, IDEState),
2636 VMSTATE_END_OF_LIST()
2637 }
2638 };
2639
2640 const VMStateDescription vmstate_ide_drive = {
2641 .name = "ide_drive",
2642 .version_id = 3,
2643 .minimum_version_id = 0,
2644 .post_load = ide_drive_post_load,
2645 .fields = (VMStateField[]) {
2646 VMSTATE_INT32(mult_sectors, IDEState),
2647 VMSTATE_INT32(identify_set, IDEState),
2648 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2649 VMSTATE_UINT8(feature, IDEState),
2650 VMSTATE_UINT8(error, IDEState),
2651 VMSTATE_UINT32(nsector, IDEState),
2652 VMSTATE_UINT8(sector, IDEState),
2653 VMSTATE_UINT8(lcyl, IDEState),
2654 VMSTATE_UINT8(hcyl, IDEState),
2655 VMSTATE_UINT8(hob_feature, IDEState),
2656 VMSTATE_UINT8(hob_sector, IDEState),
2657 VMSTATE_UINT8(hob_nsector, IDEState),
2658 VMSTATE_UINT8(hob_lcyl, IDEState),
2659 VMSTATE_UINT8(hob_hcyl, IDEState),
2660 VMSTATE_UINT8(select, IDEState),
2661 VMSTATE_UINT8(status, IDEState),
2662 VMSTATE_UINT8(lba48, IDEState),
2663 VMSTATE_UINT8(sense_key, IDEState),
2664 VMSTATE_UINT8(asc, IDEState),
2665 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2666 VMSTATE_END_OF_LIST()
2667 },
2668 .subsections = (const VMStateDescription*[]) {
2669 &vmstate_ide_drive_pio_state,
2670 &vmstate_ide_tray_state,
2671 &vmstate_ide_atapi_gesn_state,
2672 NULL
2673 }
2674 };
2675
2676 static const VMStateDescription vmstate_ide_error_status = {
2677 .name ="ide_bus/error",
2678 .version_id = 2,
2679 .minimum_version_id = 1,
2680 .needed = ide_error_needed,
2681 .fields = (VMStateField[]) {
2682 VMSTATE_INT32(error_status, IDEBus),
2683 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2684 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2685 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
2686 VMSTATE_END_OF_LIST()
2687 }
2688 };
2689
2690 const VMStateDescription vmstate_ide_bus = {
2691 .name = "ide_bus",
2692 .version_id = 1,
2693 .minimum_version_id = 1,
2694 .fields = (VMStateField[]) {
2695 VMSTATE_UINT8(cmd, IDEBus),
2696 VMSTATE_UINT8(unit, IDEBus),
2697 VMSTATE_END_OF_LIST()
2698 },
2699 .subsections = (const VMStateDescription*[]) {
2700 &vmstate_ide_error_status,
2701 NULL
2702 }
2703 };
2704
2705 void ide_drive_get(DriveInfo **hd, int n)
2706 {
2707 int i;
2708 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2709 int max_devs = drive_get_max_devs(IF_IDE);
2710 int n_buses = max_devs ? (n / max_devs) : n;
2711
2712 /*
2713 * Note: The number of actual buses available is not known.
2714 * We compute this based on the size of the DriveInfo* array, n.
2715 * If it is less than max_devs * <num_real_buses>,
2716 * We will stop looking for drives prematurely instead of overfilling
2717 * the array.
2718 */
2719
2720 if (highest_bus > n_buses) {
2721 error_report("Too many IDE buses defined (%d > %d)",
2722 highest_bus, n_buses);
2723 exit(1);
2724 }
2725
2726 for (i = 0; i < n; i++) {
2727 hd[i] = drive_get_by_index(IF_IDE, i);
2728 }
2729 }
QEMU mirror