hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/ppc_mac.h>
  27 #include <hw/mac_dbdma.h>
  28 #include "block.h"
  29 #include "dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /***********************************************************/
  34 /* MacIO based PowerPC IDE */
  35
  36 typedef struct MACIOIDEState {
  37     MemoryRegion mem;
  38     IDEBus bus;
  39     BlockDriverAIOCB *aiocb;
  40 } MACIOIDEState;
  41
  42 #define MACIO_PAGE_SIZE 4096
  43
  44 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  45 {
  46     DBDMA_io *io = opaque;
  47     MACIOIDEState *m = io->opaque;
  48     IDEState *s = idebus_active_if(&m->bus);
  49
  50     if (ret < 0) {
  51         m->aiocb = NULL;
  52         qemu_sglist_destroy(&s->sg);
  53         ide_atapi_io_error(s, ret);
  54         goto done;
  55     }
  56
  57     if (s->io_buffer_size > 0) {
  58         m->aiocb = NULL;
  59         qemu_sglist_destroy(&s->sg);
  60
  61         s->packet_transfer_size -= s->io_buffer_size;
  62
  63         s->io_buffer_index += s->io_buffer_size;
  64         s->lba += s->io_buffer_index >> 11;
  65         s->io_buffer_index &= 0x7ff;
  66     }
  67
  68     if (s->packet_transfer_size <= 0)
  69         ide_atapi_cmd_ok(s);
  70
  71     if (io->len == 0) {
  72         goto done;
  73     }
  74
  75     /* launch next transfer */
  76
  77     s->io_buffer_size = io->len;
  78
  79     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1, NULL);
  80     qemu_sglist_add(&s->sg, io->addr, io->len);
  81     io->addr += io->len;
  82     io->len = 0;
  83
  84     m->aiocb = dma_bdrv_read(s->bs, &s->sg,
  85                              (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
  86                              pmac_ide_atapi_transfer_cb, io);
  87     return;
  88
  89 done:
  90     bdrv_acct_done(s->bs, &s->acct);
  91     io->dma_end(opaque);
  92 }
  93
  94 static void pmac_ide_transfer_cb(void *opaque, int ret)
  95 {
  96     DBDMA_io *io = opaque;
  97     MACIOIDEState *m = io->opaque;
  98     IDEState *s = idebus_active_if(&m->bus);
  99     int n;
 100     int64_t sector_num;
 101
 102     if (ret < 0) {
 103         m->aiocb = NULL;
 104         qemu_sglist_destroy(&s->sg);
 105         ide_dma_error(s);
 106         goto done;
 107     }
 108
 109     sector_num = ide_get_sector(s);
 110     if (s->io_buffer_size > 0) {
 111         m->aiocb = NULL;
 112         qemu_sglist_destroy(&s->sg);
 113         n = (s->io_buffer_size + 0x1ff) >> 9;
 114         sector_num += n;
 115         ide_set_sector(s, sector_num);
 116         s->nsector -= n;
 117     }
 118
 119     /* end of transfer ? */
 120     if (s->nsector == 0) {
 121         s->status = READY_STAT | SEEK_STAT;
 122         ide_set_irq(s->bus);
 123     }
 124
 125     /* end of DMA ? */
 126     if (io->len == 0) {
 127         goto done;
 128     }
 129
 130     /* launch next transfer */
 131
 132     s->io_buffer_index = 0;
 133     s->io_buffer_size = io->len;
 134
 135     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1, NULL);
 136     qemu_sglist_add(&s->sg, io->addr, io->len);
 137     io->addr += io->len;
 138     io->len = 0;
 139
 140     switch (s->dma_cmd) {
 141     case IDE_DMA_READ:
 142         m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
 143                                  pmac_ide_transfer_cb, io);
 144         break;
 145     case IDE_DMA_WRITE:
 146         m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
 147                                   pmac_ide_transfer_cb, io);
 148         break;
 149     case IDE_DMA_TRIM:
 150         m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
 151                                ide_issue_trim, pmac_ide_transfer_cb, s,
 152                                DMA_DIRECTION_TO_DEVICE);
 153         break;
 154     }
 155     return;
 156
 157 done:
 158     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 159         bdrv_acct_done(s->bs, &s->acct);
 160     }
 161     io->dma_end(io);
 162 }
 163
 164 static void pmac_ide_transfer(DBDMA_io *io)
 165 {
 166     MACIOIDEState *m = io->opaque;
 167     IDEState *s = idebus_active_if(&m->bus);
 168
 169     s->io_buffer_size = 0;
 170     if (s->drive_kind == IDE_CD) {
 171         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 172         pmac_ide_atapi_transfer_cb(io, 0);
 173         return;
 174     }
 175
 176     switch (s->dma_cmd) {
 177     case IDE_DMA_READ:
 178         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 179         break;
 180     case IDE_DMA_WRITE:
 181         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
 182         break;
 183     default:
 184         break;
 185     }
 186
 187     pmac_ide_transfer_cb(io, 0);
 188 }
 189
 190 static void pmac_ide_flush(DBDMA_io *io)
 191 {
 192     MACIOIDEState *m = io->opaque;
 193
 194     if (m->aiocb) {
 195         bdrv_drain_all();
 196     }
 197 }
 198
 199 /* PowerMac IDE memory IO */
 200 static void pmac_ide_writeb (void *opaque,
 201                              hwaddr addr, uint32_t val)
 202 {
 203     MACIOIDEState *d = opaque;
 204
 205     addr = (addr & 0xFFF) >> 4;
 206     switch (addr) {
 207     case 1 ... 7:
 208         ide_ioport_write(&d->bus, addr, val);
 209         break;
 210     case 8:
 211     case 22:
 212         ide_cmd_write(&d->bus, 0, val);
 213         break;
 214     default:
 215         break;
 216     }
 217 }
 218
 219 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 220 {
 221     uint8_t retval;
 222     MACIOIDEState *d = opaque;
 223
 224     addr = (addr & 0xFFF) >> 4;
 225     switch (addr) {
 226     case 1 ... 7:
 227         retval = ide_ioport_read(&d->bus, addr);
 228         break;
 229     case 8:
 230     case 22:
 231         retval = ide_status_read(&d->bus, 0);
 232         break;
 233     default:
 234         retval = 0xFF;
 235         break;
 236     }
 237     return retval;
 238 }
 239
 240 static void pmac_ide_writew (void *opaque,
 241                              hwaddr addr, uint32_t val)
 242 {
 243     MACIOIDEState *d = opaque;
 244
 245     addr = (addr & 0xFFF) >> 4;
 246     val = bswap16(val);
 247     if (addr == 0) {
 248         ide_data_writew(&d->bus, 0, val);
 249     }
 250 }
 251
 252 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 253 {
 254     uint16_t retval;
 255     MACIOIDEState *d = opaque;
 256
 257     addr = (addr & 0xFFF) >> 4;
 258     if (addr == 0) {
 259         retval = ide_data_readw(&d->bus, 0);
 260     } else {
 261         retval = 0xFFFF;
 262     }
 263     retval = bswap16(retval);
 264     return retval;
 265 }
 266
 267 static void pmac_ide_writel (void *opaque,
 268                              hwaddr addr, uint32_t val)
 269 {
 270     MACIOIDEState *d = opaque;
 271
 272     addr = (addr & 0xFFF) >> 4;
 273     val = bswap32(val);
 274     if (addr == 0) {
 275         ide_data_writel(&d->bus, 0, val);
 276     }
 277 }
 278
 279 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 280 {
 281     uint32_t retval;
 282     MACIOIDEState *d = opaque;
 283
 284     addr = (addr & 0xFFF) >> 4;
 285     if (addr == 0) {
 286         retval = ide_data_readl(&d->bus, 0);
 287     } else {
 288         retval = 0xFFFFFFFF;
 289     }
 290     retval = bswap32(retval);
 291     return retval;
 292 }
 293
 294 static const MemoryRegionOps pmac_ide_ops = {
 295     .old_mmio = {
 296         .write = {
 297             pmac_ide_writeb,
 298             pmac_ide_writew,
 299             pmac_ide_writel,
 300         },
 301         .read = {
 302             pmac_ide_readb,
 303             pmac_ide_readw,
 304             pmac_ide_readl,
 305         },
 306     },
 307     .endianness = DEVICE_NATIVE_ENDIAN,
 308 };
 309
 310 static const VMStateDescription vmstate_pmac = {
 311     .name = "ide",
 312     .version_id = 3,
 313     .minimum_version_id = 0,
 314     .minimum_version_id_old = 0,
 315     .fields      = (VMStateField []) {
 316         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 317         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 318         VMSTATE_END_OF_LIST()
 319     }
 320 };
 321
 322 static void pmac_ide_reset(void *opaque)
 323 {
 324     MACIOIDEState *d = opaque;
 325
 326     ide_bus_reset(&d->bus);
 327 }
 328
 329 /* hd_table must contain 4 block drivers */
 330 /* PowerMac uses memory mapped registers, not I/O. Return the memory
 331    I/O index to access the ide. */
 332 MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
 333                              void *dbdma, int channel, qemu_irq dma_irq)
 334 {
 335     MACIOIDEState *d;
 336
 337     d = g_malloc0(sizeof(MACIOIDEState));
 338     ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
 339
 340     if (dbdma)
 341         DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
 342
 343     memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
 344     vmstate_register(NULL, 0, &vmstate_pmac, d);
 345     qemu_register_reset(pmac_ide_reset, d);
 346
 347     return &d->mem;
 348 }