2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include <hw/ppc_mac.h>
27 #include <hw/mac_dbdma.h>
31 #include <hw/ide/internal.h>
33 /***********************************************************/
34 /* MacIO based PowerPC IDE */
36 typedef struct MACIOIDEState
{
39 BlockDriverAIOCB
*aiocb
;
42 #define MACIO_PAGE_SIZE 4096
44 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
46 DBDMA_io
*io
= opaque
;
47 MACIOIDEState
*m
= io
->opaque
;
48 IDEState
*s
= idebus_active_if(&m
->bus
);
52 qemu_sglist_destroy(&s
->sg
);
53 ide_atapi_io_error(s
, ret
);
57 if (s
->io_buffer_size
> 0) {
59 qemu_sglist_destroy(&s
->sg
);
61 s
->packet_transfer_size
-= s
->io_buffer_size
;
63 s
->io_buffer_index
+= s
->io_buffer_size
;
64 s
->lba
+= s
->io_buffer_index
>> 11;
65 s
->io_buffer_index
&= 0x7ff;
68 if (s
->packet_transfer_size
<= 0)
75 /* launch next transfer */
77 s
->io_buffer_size
= io
->len
;
79 qemu_sglist_init(&s
->sg
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
80 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
84 m
->aiocb
= dma_bdrv_read(s
->bs
, &s
->sg
,
85 (int64_t)(s
->lba
<< 2) + (s
->io_buffer_index
>> 9),
86 pmac_ide_atapi_transfer_cb
, io
);
88 qemu_sglist_destroy(&s
->sg
);
89 /* Note: media not present is the most likely case */
90 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
91 ASC_MEDIUM_NOT_PRESENT
);
97 bdrv_acct_done(s
->bs
, &s
->acct
);
102 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
104 DBDMA_io
*io
= opaque
;
105 MACIOIDEState
*m
= io
->opaque
;
106 IDEState
*s
= idebus_active_if(&m
->bus
);
112 qemu_sglist_destroy(&s
->sg
);
117 sector_num
= ide_get_sector(s
);
118 if (s
->io_buffer_size
> 0) {
120 qemu_sglist_destroy(&s
->sg
);
121 n
= (s
->io_buffer_size
+ 0x1ff) >> 9;
123 ide_set_sector(s
, sector_num
);
127 /* end of transfer ? */
128 if (s
->nsector
== 0) {
129 s
->status
= READY_STAT
| SEEK_STAT
;
138 /* launch next transfer */
140 s
->io_buffer_index
= 0;
141 s
->io_buffer_size
= io
->len
;
143 qemu_sglist_init(&s
->sg
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
144 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
148 switch (s
->dma_cmd
) {
150 m
->aiocb
= dma_bdrv_read(s
->bs
, &s
->sg
, sector_num
,
151 pmac_ide_transfer_cb
, io
);
154 m
->aiocb
= dma_bdrv_write(s
->bs
, &s
->sg
, sector_num
,
155 pmac_ide_transfer_cb
, io
);
158 m
->aiocb
= dma_bdrv_io(s
->bs
, &s
->sg
, sector_num
,
159 ide_issue_trim
, pmac_ide_transfer_cb
, s
, 1);
164 pmac_ide_transfer_cb(io
, -1);
167 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
168 bdrv_acct_done(s
->bs
, &s
->acct
);
173 static void pmac_ide_transfer(DBDMA_io
*io
)
175 MACIOIDEState
*m
= io
->opaque
;
176 IDEState
*s
= idebus_active_if(&m
->bus
);
178 s
->io_buffer_size
= 0;
179 if (s
->drive_kind
== IDE_CD
) {
180 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_READ
);
181 pmac_ide_atapi_transfer_cb(io
, 0);
185 switch (s
->dma_cmd
) {
187 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_READ
);
190 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_WRITE
);
196 pmac_ide_transfer_cb(io
, 0);
199 static void pmac_ide_flush(DBDMA_io
*io
)
201 MACIOIDEState
*m
= io
->opaque
;
207 /* PowerMac IDE memory IO */
208 static void pmac_ide_writeb (void *opaque
,
209 target_phys_addr_t addr
, uint32_t val
)
211 MACIOIDEState
*d
= opaque
;
213 addr
= (addr
& 0xFFF) >> 4;
216 ide_ioport_write(&d
->bus
, addr
, val
);
220 ide_cmd_write(&d
->bus
, 0, val
);
227 static uint32_t pmac_ide_readb (void *opaque
,target_phys_addr_t addr
)
230 MACIOIDEState
*d
= opaque
;
232 addr
= (addr
& 0xFFF) >> 4;
235 retval
= ide_ioport_read(&d
->bus
, addr
);
239 retval
= ide_status_read(&d
->bus
, 0);
248 static void pmac_ide_writew (void *opaque
,
249 target_phys_addr_t addr
, uint32_t val
)
251 MACIOIDEState
*d
= opaque
;
253 addr
= (addr
& 0xFFF) >> 4;
256 ide_data_writew(&d
->bus
, 0, val
);
260 static uint32_t pmac_ide_readw (void *opaque
,target_phys_addr_t addr
)
263 MACIOIDEState
*d
= opaque
;
265 addr
= (addr
& 0xFFF) >> 4;
267 retval
= ide_data_readw(&d
->bus
, 0);
271 retval
= bswap16(retval
);
275 static void pmac_ide_writel (void *opaque
,
276 target_phys_addr_t addr
, uint32_t val
)
278 MACIOIDEState
*d
= opaque
;
280 addr
= (addr
& 0xFFF) >> 4;
283 ide_data_writel(&d
->bus
, 0, val
);
287 static uint32_t pmac_ide_readl (void *opaque
,target_phys_addr_t addr
)
290 MACIOIDEState
*d
= opaque
;
292 addr
= (addr
& 0xFFF) >> 4;
294 retval
= ide_data_readl(&d
->bus
, 0);
298 retval
= bswap32(retval
);
302 static MemoryRegionOps pmac_ide_ops
= {
315 .endianness
= DEVICE_NATIVE_ENDIAN
,
318 static const VMStateDescription vmstate_pmac
= {
321 .minimum_version_id
= 0,
322 .minimum_version_id_old
= 0,
323 .fields
= (VMStateField
[]) {
324 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
325 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
326 VMSTATE_END_OF_LIST()
330 static void pmac_ide_reset(void *opaque
)
332 MACIOIDEState
*d
= opaque
;
334 ide_bus_reset(&d
->bus
);
337 /* hd_table must contain 4 block drivers */
338 /* PowerMac uses memory mapped registers, not I/O. Return the memory
339 I/O index to access the ide. */
340 MemoryRegion
*pmac_ide_init (DriveInfo
**hd_table
, qemu_irq irq
,
341 void *dbdma
, int channel
, qemu_irq dma_irq
)
345 d
= g_malloc0(sizeof(MACIOIDEState
));
346 ide_init2_with_non_qdev_drives(&d
->bus
, hd_table
[0], hd_table
[1], irq
);
349 DBDMA_register_channel(dbdma
, channel
, dma_irq
, pmac_ide_transfer
, pmac_ide_flush
, d
);
351 memory_region_init_io(&d
->mem
, &pmac_ide_ops
, d
, "pmac-ide", 0x1000);
352 vmstate_register(NULL
, 0, &vmstate_pmac
, d
);
353 qemu_register_reset(pmac_ide_reset
, d
);