2 * QEMU IDE Emulation: mmio support (for embedded).
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "block_int.h"
31 #include <hw/ide/internal.h>
33 /***********************************************************/
34 /* MMIO based ide port
35 * This emulates IDE device connected directly to the CPU bus without
36 * dedicated ide controller, which is often seen on embedded boards.
44 static uint32_t mmio_ide_read (void *opaque
, a_target_phys_addr addr
)
46 MMIOState
*s
= (MMIOState
*)opaque
;
50 return ide_ioport_read(bus
, addr
);
52 return ide_data_readw(bus
, 0);
55 static void mmio_ide_write (void *opaque
, a_target_phys_addr addr
,
58 MMIOState
*s
= (MMIOState
*)opaque
;
62 ide_ioport_write(bus
, addr
, val
);
64 ide_data_writew(bus
, 0, val
);
67 static CPUReadMemoryFunc
* const mmio_ide_reads
[] = {
73 static CPUWriteMemoryFunc
* const mmio_ide_writes
[] = {
79 static uint32_t mmio_ide_status_read (void *opaque
, a_target_phys_addr addr
)
81 MMIOState
*s
= (MMIOState
*)opaque
;
83 return ide_status_read(bus
, 0);
86 static void mmio_ide_cmd_write (void *opaque
, a_target_phys_addr addr
,
89 MMIOState
*s
= (MMIOState
*)opaque
;
91 ide_cmd_write(bus
, 0, val
);
94 static CPUReadMemoryFunc
* const mmio_ide_status
[] = {
100 static CPUWriteMemoryFunc
* const mmio_ide_cmd
[] = {
106 static void mmio_ide_save(QEMUFile
* f
, void *opaque
)
108 MMIOState
*s
= opaque
;
110 idebus_save(f
, s
->bus
);
111 ide_save(f
, &s
->bus
->ifs
[0]);
112 ide_save(f
, &s
->bus
->ifs
[1]);
115 static int mmio_ide_load(QEMUFile
* f
, void *opaque
, int version_id
)
117 MMIOState
*s
= opaque
;
119 idebus_load(f
, s
->bus
, version_id
);
120 ide_load(f
, &s
->bus
->ifs
[0], version_id
);
121 ide_load(f
, &s
->bus
->ifs
[1], version_id
);
125 void mmio_ide_init (a_target_phys_addr membase
, a_target_phys_addr membase2
,
126 qemu_irq irq
, int shift
,
127 DriveInfo
*hd0
, DriveInfo
*hd1
)
129 MMIOState
*s
= qemu_mallocz(sizeof(MMIOState
));
130 IDEBus
*bus
= qemu_mallocz(sizeof(*bus
));
133 ide_init2(bus
, hd0
, hd1
, irq
);
138 mem1
= cpu_register_io_memory(mmio_ide_reads
, mmio_ide_writes
, s
);
139 mem2
= cpu_register_io_memory(mmio_ide_status
, mmio_ide_cmd
, s
);
140 cpu_register_physical_memory(membase
, 16 << shift
, mem1
);
141 cpu_register_physical_memory(membase2
, 2 << shift
, mem2
);
142 register_savevm("mmio-ide", 0, 3, mmio_ide_save
, mmio_ide_load
, s
);