hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/isa/isa.h>
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/dma.h"
  31
  32 #include <hw/ide/pci.h>
  33
  34 #define BMDMA_PAGE_SIZE 4096
  35
  36 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  37         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  38         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  39
  40 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  41                             BlockCompletionFunc *dma_cb)
  42 {
  43     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  44
  45     bm->unit = s->unit;
  46     bm->dma_cb = dma_cb;
  47     bm->cur_prd_last = 0;
  48     bm->cur_prd_addr = 0;
  49     bm->cur_prd_len = 0;
  50     bm->sector_num = ide_get_sector(s);
  51     bm->nsector = s->nsector;
  52
  53     if (bm->status & BM_STATUS_DMAING) {
  54         bm->dma_cb(bmdma_active_if(bm), 0);
  55     }
  56 }
  57
  58 /* return 0 if buffer completed */
  59 static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
  60 {
  61     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  62     IDEState *s = bmdma_active_if(bm);
  63     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  64     struct {
  65         uint32_t addr;
  66         uint32_t size;
  67     } prd;
  68     int l, len;
  69
  70     pci_dma_sglist_init(&s->sg, pci_dev,
  71                         s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  72     s->io_buffer_size = 0;
  73     for(;;) {
  74         if (bm->cur_prd_len == 0) {
  75             /* end of table (with a fail safe of one page) */
  76             if (bm->cur_prd_last ||
  77                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
  78                 return s->io_buffer_size != 0;
  79             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
  80             bm->cur_addr += 8;
  81             prd.addr = le32_to_cpu(prd.addr);
  82             prd.size = le32_to_cpu(prd.size);
  83             len = prd.size & 0xfffe;
  84             if (len == 0)
  85                 len = 0x10000;
  86             bm->cur_prd_len = len;
  87             bm->cur_prd_addr = prd.addr;
  88             bm->cur_prd_last = (prd.size & 0x80000000);
  89         }
  90         l = bm->cur_prd_len;
  91         if (l > 0) {
  92             qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
  93             bm->cur_prd_addr += l;
  94             bm->cur_prd_len -= l;
  95             s->io_buffer_size += l;
  96         }
  97     }
  98     return 1;
  99 }
 100
 101 /* return 0 if buffer completed */
 102 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
 103 {
 104     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 105     IDEState *s = bmdma_active_if(bm);
 106     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 107     struct {
 108         uint32_t addr;
 109         uint32_t size;
 110     } prd;
 111     int l, len;
 112
 113     for(;;) {
 114         l = s->io_buffer_size - s->io_buffer_index;
 115         if (l <= 0)
 116             break;
 117         if (bm->cur_prd_len == 0) {
 118             /* end of table (with a fail safe of one page) */
 119             if (bm->cur_prd_last ||
 120                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 121                 return 0;
 122             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 123             bm->cur_addr += 8;
 124             prd.addr = le32_to_cpu(prd.addr);
 125             prd.size = le32_to_cpu(prd.size);
 126             len = prd.size & 0xfffe;
 127             if (len == 0)
 128                 len = 0x10000;
 129             bm->cur_prd_len = len;
 130             bm->cur_prd_addr = prd.addr;
 131             bm->cur_prd_last = (prd.size & 0x80000000);
 132         }
 133         if (l > bm->cur_prd_len)
 134             l = bm->cur_prd_len;
 135         if (l > 0) {
 136             if (is_write) {
 137                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 138                               s->io_buffer + s->io_buffer_index, l);
 139             } else {
 140                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 141                              s->io_buffer + s->io_buffer_index, l);
 142             }
 143             bm->cur_prd_addr += l;
 144             bm->cur_prd_len -= l;
 145             s->io_buffer_index += l;
 146         }
 147     }
 148     return 1;
 149 }
 150
 151 static int bmdma_set_unit(IDEDMA *dma, int unit)
 152 {
 153     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 154     bm->unit = unit;
 155
 156     return 0;
 157 }
 158
 159 static void bmdma_set_inactive(IDEDMA *dma, bool more)
 160 {
 161     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 162
 163     bm->dma_cb = NULL;
 164     bm->unit = -1;
 165     if (more) {
 166         bm->status |= BM_STATUS_DMAING;
 167     } else {
 168         bm->status &= ~BM_STATUS_DMAING;
 169     }
 170 }
 171
 172 static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
 173 {
 174     IDEState *s = bmdma_active_if(bm);
 175
 176     ide_set_sector(s, bm->sector_num);
 177     s->io_buffer_index = 0;
 178     s->io_buffer_size = 0;
 179     s->nsector = bm->nsector;
 180     s->dma_cmd = dma_cmd;
 181     bm->cur_addr = bm->addr;
 182     bm->dma_cb = ide_dma_cb;
 183     bmdma_start_dma(&bm->dma, s, bm->dma_cb);
 184 }
 185
 186 /* TODO This should be common IDE code */
 187 static void bmdma_restart_bh(void *opaque)
 188 {
 189     BMDMAState *bm = opaque;
 190     IDEBus *bus = bm->bus;
 191     bool is_read;
 192     int error_status;
 193
 194     qemu_bh_delete(bm->bh);
 195     bm->bh = NULL;
 196
 197     if (bm->unit == (uint8_t) -1) {
 198         return;
 199     }
 200
 201     is_read = (bus->error_status & IDE_RETRY_READ) != 0;
 202
 203     /* The error status must be cleared before resubmitting the request: The
 204      * request may fail again, and this case can only be distinguished if the
 205      * called function can set a new error status. */
 206     error_status = bus->error_status;
 207     bus->error_status = 0;
 208
 209     if (error_status & IDE_RETRY_DMA) {
 210         if (error_status & IDE_RETRY_TRIM) {
 211             bmdma_restart_dma(bm, IDE_DMA_TRIM);
 212         } else {
 213             bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
 214         }
 215     } else if (error_status & IDE_RETRY_PIO) {
 216         if (is_read) {
 217             ide_sector_read(bmdma_active_if(bm));
 218         } else {
 219             ide_sector_write(bmdma_active_if(bm));
 220         }
 221     } else if (error_status & IDE_RETRY_FLUSH) {
 222         ide_flush_cache(bmdma_active_if(bm));
 223     }
 224 }
 225
 226 static void bmdma_restart_cb(void *opaque, int running, RunState state)
 227 {
 228     IDEDMA *dma = opaque;
 229     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 230
 231     if (!running)
 232         return;
 233
 234     if (!bm->bh) {
 235         bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
 236         qemu_bh_schedule(bm->bh);
 237     }
 238 }
 239
 240 static void bmdma_cancel(BMDMAState *bm)
 241 {
 242     if (bm->status & BM_STATUS_DMAING) {
 243         /* cancel DMA request */
 244         bmdma_set_inactive(&bm->dma, false);
 245     }
 246 }
 247
 248 static void bmdma_reset(IDEDMA *dma)
 249 {
 250     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 251
 252 #ifdef DEBUG_IDE
 253     printf("ide: dma_reset\n");
 254 #endif
 255     bmdma_cancel(bm);
 256     bm->cmd = 0;
 257     bm->status = 0;
 258     bm->addr = 0;
 259     bm->cur_addr = 0;
 260     bm->cur_prd_last = 0;
 261     bm->cur_prd_addr = 0;
 262     bm->cur_prd_len = 0;
 263     bm->sector_num = 0;
 264     bm->nsector = 0;
 265 }
 266
 267 static void bmdma_irq(void *opaque, int n, int level)
 268 {
 269     BMDMAState *bm = opaque;
 270
 271     if (!level) {
 272         /* pass through lower */
 273         qemu_set_irq(bm->irq, level);
 274         return;
 275     }
 276
 277     bm->status |= BM_STATUS_INT;
 278
 279     /* trigger the real irq */
 280     qemu_set_irq(bm->irq, level);
 281 }
 282
 283 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 284 {
 285 #ifdef DEBUG_IDE
 286     printf("%s: 0x%08x\n", __func__, val);
 287 #endif
 288
 289     /* Ignore writes to SSBM if it keeps the old value */
 290     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 291         if (!(val & BM_CMD_START)) {
 292             /*
 293              * We can't cancel Scatter Gather DMA in the middle of the
 294              * operation or a partial (not full) DMA transfer would reach
 295              * the storage so we wait for completion instead (we beahve
 296              * like if the DMA was completed by the time the guest trying
 297              * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
 298              * set).
 299              *
 300              * In the future we'll be able to safely cancel the I/O if the
 301              * whole DMA operation will be submitted to disk with a single
 302              * aio operation with preadv/pwritev.
 303              */
 304             if (bm->bus->dma->aiocb) {
 305                 blk_drain_all();
 306                 assert(bm->bus->dma->aiocb == NULL);
 307             }
 308             bm->status &= ~BM_STATUS_DMAING;
 309         } else {
 310             bm->cur_addr = bm->addr;
 311             if (!(bm->status & BM_STATUS_DMAING)) {
 312                 bm->status |= BM_STATUS_DMAING;
 313                 /* start dma transfer if possible */
 314                 if (bm->dma_cb)
 315                     bm->dma_cb(bmdma_active_if(bm), 0);
 316             }
 317         }
 318     }
 319
 320     bm->cmd = val & 0x09;
 321 }
 322
 323 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 324                                 unsigned width)
 325 {
 326     BMDMAState *bm = opaque;
 327     uint32_t mask = (1ULL << (width * 8)) - 1;
 328     uint64_t data;
 329
 330     data = (bm->addr >> (addr * 8)) & mask;
 331 #ifdef DEBUG_IDE
 332     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 333 #endif
 334     return data;
 335 }
 336
 337 static void bmdma_addr_write(void *opaque, hwaddr addr,
 338                              uint64_t data, unsigned width)
 339 {
 340     BMDMAState *bm = opaque;
 341     int shift = addr * 8;
 342     uint32_t mask = (1ULL << (width * 8)) - 1;
 343
 344 #ifdef DEBUG_IDE
 345     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 346 #endif
 347     bm->addr &= ~(mask << shift);
 348     bm->addr |= ((data & mask) << shift) & ~3;
 349 }
 350
 351 MemoryRegionOps bmdma_addr_ioport_ops = {
 352     .read = bmdma_addr_read,
 353     .write = bmdma_addr_write,
 354     .endianness = DEVICE_LITTLE_ENDIAN,
 355 };
 356
 357 static bool ide_bmdma_current_needed(void *opaque)
 358 {
 359     BMDMAState *bm = opaque;
 360
 361     return (bm->cur_prd_len != 0);
 362 }
 363
 364 static bool ide_bmdma_status_needed(void *opaque)
 365 {
 366     BMDMAState *bm = opaque;
 367
 368     /* Older versions abused some bits in the status register for internal
 369      * error state. If any of these bits are set, we must add a subsection to
 370      * transfer the real status register */
 371     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 372
 373     return ((bm->status & abused_bits) != 0);
 374 }
 375
 376 static void ide_bmdma_pre_save(void *opaque)
 377 {
 378     BMDMAState *bm = opaque;
 379     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 380
 381     bm->migration_compat_status =
 382         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 383 }
 384
 385 /* This function accesses bm->bus->error_status which is loaded only after
 386  * BMDMA itself. This is why the function is called from ide_pci_post_load
 387  * instead of being registered with VMState where it would run too early. */
 388 static int ide_bmdma_post_load(void *opaque, int version_id)
 389 {
 390     BMDMAState *bm = opaque;
 391     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 392
 393     if (bm->status == 0) {
 394         bm->status = bm->migration_compat_status & ~abused_bits;
 395         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 396     }
 397
 398     return 0;
 399 }
 400
 401 static const VMStateDescription vmstate_bmdma_current = {
 402     .name = "ide bmdma_current",
 403     .version_id = 1,
 404     .minimum_version_id = 1,
 405     .fields = (VMStateField[]) {
 406         VMSTATE_UINT32(cur_addr, BMDMAState),
 407         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 408         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 409         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 410         VMSTATE_END_OF_LIST()
 411     }
 412 };
 413
 414 static const VMStateDescription vmstate_bmdma_status = {
 415     .name ="ide bmdma/status",
 416     .version_id = 1,
 417     .minimum_version_id = 1,
 418     .fields = (VMStateField[]) {
 419         VMSTATE_UINT8(status, BMDMAState),
 420         VMSTATE_END_OF_LIST()
 421     }
 422 };
 423
 424 static const VMStateDescription vmstate_bmdma = {
 425     .name = "ide bmdma",
 426     .version_id = 3,
 427     .minimum_version_id = 0,
 428     .pre_save  = ide_bmdma_pre_save,
 429     .fields = (VMStateField[]) {
 430         VMSTATE_UINT8(cmd, BMDMAState),
 431         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 432         VMSTATE_UINT32(addr, BMDMAState),
 433         VMSTATE_INT64(sector_num, BMDMAState),
 434         VMSTATE_UINT32(nsector, BMDMAState),
 435         VMSTATE_UINT8(unit, BMDMAState),
 436         VMSTATE_END_OF_LIST()
 437     },
 438     .subsections = (VMStateSubsection []) {
 439         {
 440             .vmsd = &vmstate_bmdma_current,
 441             .needed = ide_bmdma_current_needed,
 442         }, {
 443             .vmsd = &vmstate_bmdma_status,
 444             .needed = ide_bmdma_status_needed,
 445         }, {
 446             /* empty */
 447         }
 448     }
 449 };
 450
 451 static int ide_pci_post_load(void *opaque, int version_id)
 452 {
 453     PCIIDEState *d = opaque;
 454     int i;
 455
 456     for(i = 0; i < 2; i++) {
 457         /* current versions always store 0/1, but older version
 458            stored bigger values. We only need last bit */
 459         d->bmdma[i].unit &= 1;
 460         ide_bmdma_post_load(&d->bmdma[i], -1);
 461     }
 462
 463     return 0;
 464 }
 465
 466 const VMStateDescription vmstate_ide_pci = {
 467     .name = "ide",
 468     .version_id = 3,
 469     .minimum_version_id = 0,
 470     .post_load = ide_pci_post_load,
 471     .fields = (VMStateField[]) {
 472         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 473         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 474                              vmstate_bmdma, BMDMAState),
 475         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 476         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 477         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 478         VMSTATE_END_OF_LIST()
 479     }
 480 };
 481
 482 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 483 {
 484     PCIIDEState *d = PCI_IDE(dev);
 485     static const int bus[4]  = { 0, 0, 1, 1 };
 486     static const int unit[4] = { 0, 1, 0, 1 };
 487     int i;
 488
 489     for (i = 0; i < 4; i++) {
 490         if (hd_table[i] == NULL)
 491             continue;
 492         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 493     }
 494 }
 495
 496 static const struct IDEDMAOps bmdma_ops = {
 497     .start_dma = bmdma_start_dma,
 498     .prepare_buf = bmdma_prepare_buf,
 499     .rw_buf = bmdma_rw_buf,
 500     .set_unit = bmdma_set_unit,
 501     .set_inactive = bmdma_set_inactive,
 502     .restart_cb = bmdma_restart_cb,
 503     .reset = bmdma_reset,
 504 };
 505
 506 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 507 {
 508     qemu_irq *irq;
 509
 510     if (bus->dma == &bm->dma) {
 511         return;
 512     }
 513
 514     bm->dma.ops = &bmdma_ops;
 515     bus->dma = &bm->dma;
 516     bm->irq = bus->irq;
 517     irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
 518     bus->irq = *irq;
 519     bm->pci_dev = d;
 520 }
 521
 522 static const TypeInfo pci_ide_type_info = {
 523     .name = TYPE_PCI_IDE,
 524     .parent = TYPE_PCI_DEVICE,
 525     .instance_size = sizeof(PCIIDEState),
 526     .abstract = true,
 527 };
 528
 529 static void pci_ide_register_types(void)
 530 {
 531     type_register_static(&pci_ide_type_info);
 532 }
 533
 534 type_init(pci_ide_register_types)