hw/ide/piix.c

   1 /*
   2  * QEMU IDE Emulation: PCI PIIX3/4 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * References:
  26  *  [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR,
  27  *      290550-002, Intel Corporation, April 1997.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "migration/vmstate.h"
  32 #include "qapi/error.h"
  33 #include "hw/pci/pci.h"
  34 #include "hw/ide/piix.h"
  35 #include "hw/ide/pci.h"
  36 #include "trace.h"
  37
  38 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
  39 {
  40     BMDMAState *bm = opaque;
  41     uint32_t val;
  42
  43     if (size != 1) {
  44         return ((uint64_t)1 << (size * 8)) - 1;
  45     }
  46
  47     switch(addr & 3) {
  48     case 0:
  49         val = bm->cmd;
  50         break;
  51     case 2:
  52         val = bm->status;
  53         break;
  54     default:
  55         val = 0xff;
  56         break;
  57     }
  58
  59     trace_bmdma_read(addr, val);
  60     return val;
  61 }
  62
  63 static void bmdma_write(void *opaque, hwaddr addr,
  64                         uint64_t val, unsigned size)
  65 {
  66     BMDMAState *bm = opaque;
  67
  68     if (size != 1) {
  69         return;
  70     }
  71
  72     trace_bmdma_write(addr, val);
  73
  74     switch(addr & 3) {
  75     case 0:
  76         bmdma_cmd_writeb(bm, val);
  77         break;
  78     case 2:
  79         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  80         break;
  81     }
  82 }
  83
  84 static const MemoryRegionOps piix_bmdma_ops = {
  85     .read = bmdma_read,
  86     .write = bmdma_write,
  87 };
  88
  89 static void bmdma_setup_bar(PCIIDEState *d)
  90 {
  91     int i;
  92
  93     memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
  94     for(i = 0;i < 2; i++) {
  95         BMDMAState *bm = &d->bmdma[i];
  96
  97         memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
  98                               "piix-bmdma", 4);
  99         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 100         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 101                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 102         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 103     }
 104 }
 105
 106 static void piix_ide_reset(DeviceState *dev)
 107 {
 108     PCIIDEState *d = PCI_IDE(dev);
 109     PCIDevice *pd = PCI_DEVICE(d);
 110     uint8_t *pci_conf = pd->config;
 111     int i;
 112
 113     for (i = 0; i < 2; i++) {
 114         ide_bus_reset(&d->bus[i]);
 115     }
 116
 117     /* PCI command register default value (0000h) per [1, p.48].  */
 118     pci_set_word(pci_conf + PCI_COMMAND, 0x0000);
 119     pci_set_word(pci_conf + PCI_STATUS,
 120                  PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
 121     pci_set_byte(pci_conf + 0x20, 0x01);  /* BMIBA: 20-23h */
 122 }
 123
 124 static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
 125 {
 126     static const struct {
 127         int iobase;
 128         int iobase2;
 129         int isairq;
 130     } port_info[] = {
 131         {0x1f0, 0x3f6, 14},
 132         {0x170, 0x376, 15},
 133     };
 134     int ret;
 135
 136     ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 137     ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 138                           port_info[i].iobase2);
 139     if (ret) {
 140         error_setg_errno(errp, -ret, "Failed to realize %s port %u",
 141                          object_get_typename(OBJECT(d)), i);
 142         return false;
 143     }
 144     ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 145
 146     bmdma_init(&d->bus[i], &d->bmdma[i], d);
 147     d->bmdma[i].bus = &d->bus[i];
 148     ide_bus_register_restart_cb(&d->bus[i]);
 149
 150     return true;
 151 }
 152
 153 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
 154 {
 155     PCIIDEState *d = PCI_IDE(dev);
 156     uint8_t *pci_conf = dev->config;
 157
 158     pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
 159
 160     bmdma_setup_bar(d);
 161     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 162
 163     vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
 164
 165     for (unsigned i = 0; i < 2; i++) {
 166         if (!pci_piix_init_bus(d, i, errp)) {
 167             return;
 168         }
 169     }
 170 }
 171
 172 static void pci_piix_ide_exitfn(PCIDevice *dev)
 173 {
 174     PCIIDEState *d = PCI_IDE(dev);
 175     unsigned i;
 176
 177     for (i = 0; i < 2; ++i) {
 178         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 179         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 180     }
 181 }
 182
 183 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
 184 static void piix3_ide_class_init(ObjectClass *klass, void *data)
 185 {
 186     DeviceClass *dc = DEVICE_CLASS(klass);
 187     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 188
 189     dc->reset = piix_ide_reset;
 190     k->realize = pci_piix_ide_realize;
 191     k->exit = pci_piix_ide_exitfn;
 192     k->vendor_id = PCI_VENDOR_ID_INTEL;
 193     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
 194     k->class_id = PCI_CLASS_STORAGE_IDE;
 195     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 196     dc->hotpluggable = false;
 197 }
 198
 199 static const TypeInfo piix3_ide_info = {
 200     .name          = TYPE_PIIX3_IDE,
 201     .parent        = TYPE_PCI_IDE,
 202     .class_init    = piix3_ide_class_init,
 203 };
 204
 205 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
 206 static void piix4_ide_class_init(ObjectClass *klass, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(klass);
 209     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 210
 211     dc->reset = piix_ide_reset;
 212     k->realize = pci_piix_ide_realize;
 213     k->exit = pci_piix_ide_exitfn;
 214     k->vendor_id = PCI_VENDOR_ID_INTEL;
 215     k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
 216     k->class_id = PCI_CLASS_STORAGE_IDE;
 217     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 218     dc->hotpluggable = false;
 219 }
 220
 221 static const TypeInfo piix4_ide_info = {
 222     .name          = TYPE_PIIX4_IDE,
 223     .parent        = TYPE_PCI_IDE,
 224     .class_init    = piix4_ide_class_init,
 225 };
 226
 227 static void piix_ide_register_types(void)
 228 {
 229     type_register_static(&piix3_ide_info);
 230     type_register_static(&piix4_ide_info);
 231 }
 232
 233 type_init(piix_ide_register_types)