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Replace the VMSTOP macros with a proper state type
[mirror_qemu.git] / hw / ide / via.c
1 /*
2 * QEMU IDE Emulation: PCI VIA82C686B support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26 #include <hw/hw.h>
27 #include <hw/pc.h>
28 #include <hw/pci.h>
29 #include <hw/isa.h>
30 #include "block.h"
31 #include "sysemu.h"
32 #include "dma.h"
33
34 #include <hw/ide/pci.h>
35
36 static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
37 unsigned size)
38 {
39 BMDMAState *bm = opaque;
40 uint32_t val;
41
42 if (size != 1) {
43 return ((uint64_t)1 << (size * 8)) - 1;
44 }
45
46 switch (addr & 3) {
47 case 0:
48 val = bm->cmd;
49 break;
50 case 2:
51 val = bm->status;
52 break;
53 default:
54 val = 0xff;
55 break;
56 }
57 #ifdef DEBUG_IDE
58 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
59 #endif
60 return val;
61 }
62
63 static void bmdma_write(void *opaque, target_phys_addr_t addr,
64 uint64_t val, unsigned size)
65 {
66 BMDMAState *bm = opaque;
67
68 if (size != 1) {
69 return;
70 }
71
72 #ifdef DEBUG_IDE
73 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
74 #endif
75 switch (addr & 3) {
76 case 0:
77 return bmdma_cmd_writeb(bm, val);
78 case 2:
79 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
80 break;
81 default:;
82 }
83 }
84
85 static MemoryRegionOps via_bmdma_ops = {
86 .read = bmdma_read,
87 .write = bmdma_write,
88 };
89
90 static void bmdma_setup_bar(PCIIDEState *d)
91 {
92 int i;
93
94 memory_region_init(&d->bmdma_bar, "via-bmdma-container", 16);
95 for(i = 0;i < 2; i++) {
96 BMDMAState *bm = &d->bmdma[i];
97
98 memory_region_init_io(&bm->extra_io, &via_bmdma_ops, bm,
99 "via-bmdma", 4);
100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
101 memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
102 "bmdma", 4);
103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
104 }
105 }
106
107 static void via_reset(void *opaque)
108 {
109 PCIIDEState *d = opaque;
110 uint8_t *pci_conf = d->dev.config;
111 int i;
112
113 for (i = 0; i < 2; i++) {
114 ide_bus_reset(&d->bus[i]);
115 }
116
117 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
118 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
119 PCI_STATUS_DEVSEL_MEDIUM);
120
121 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
122 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
123 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
124 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
125 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
126 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
127
128 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
129 pci_set_long(pci_conf + 0x40, 0x0a090600);
130 /* IDE misc configuration 1/2/3 */
131 pci_set_long(pci_conf + 0x44, 0x00c00068);
132 /* IDE Timing control */
133 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
134 /* IDE Address Setup Time */
135 pci_set_long(pci_conf + 0x4c, 0x000000ff);
136 /* UltraDMA Extended Timing Control*/
137 pci_set_long(pci_conf + 0x50, 0x07070707);
138 /* UltraDMA FIFO Control */
139 pci_set_long(pci_conf + 0x54, 0x00000004);
140 /* IDE primary sector size */
141 pci_set_long(pci_conf + 0x60, 0x00000200);
142 /* IDE secondary sector size */
143 pci_set_long(pci_conf + 0x68, 0x00000200);
144 /* PCI PM Block */
145 pci_set_long(pci_conf + 0xc0, 0x00020001);
146 }
147
148 static void vt82c686b_init_ports(PCIIDEState *d) {
149 int i;
150 struct {
151 int iobase;
152 int iobase2;
153 int isairq;
154 } port_info[] = {
155 {0x1f0, 0x3f6, 14},
156 {0x170, 0x376, 15},
157 };
158
159 for (i = 0; i < 2; i++) {
160 ide_bus_new(&d->bus[i], &d->dev.qdev, i);
161 ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
162 ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
163
164 bmdma_init(&d->bus[i], &d->bmdma[i], d);
165 d->bmdma[i].bus = &d->bus[i];
166 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
167 &d->bmdma[i].dma);
168 }
169 }
170
171 /* via ide func */
172 static int vt82c686b_ide_initfn(PCIDevice *dev)
173 {
174 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
175 uint8_t *pci_conf = d->dev.config;
176
177 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
178 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
179
180 qemu_register_reset(via_reset, d);
181 bmdma_setup_bar(d);
182 pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
183
184 vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
185
186 vt82c686b_init_ports(d);
187
188 return 0;
189 }
190
191 static int vt82c686b_ide_exitfn(PCIDevice *dev)
192 {
193 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
194 unsigned i;
195
196 for (i = 0; i < 2; ++i) {
197 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
198 memory_region_destroy(&d->bmdma[i].extra_io);
199 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
200 memory_region_destroy(&d->bmdma[i].addr_ioport);
201 }
202 memory_region_destroy(&d->bmdma_bar);
203
204 return 0;
205 }
206
207 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
208 {
209 PCIDevice *dev;
210
211 dev = pci_create_simple(bus, devfn, "via-ide");
212 pci_ide_create_devs(dev, hd_table);
213 }
214
215 static PCIDeviceInfo via_ide_info = {
216 .qdev.name = "via-ide",
217 .qdev.size = sizeof(PCIIDEState),
218 .qdev.no_user = 1,
219 .init = vt82c686b_ide_initfn,
220 .exit = vt82c686b_ide_exitfn,
221 .vendor_id = PCI_VENDOR_ID_VIA,
222 .device_id = PCI_DEVICE_ID_VIA_IDE,
223 .revision = 0x06,
224 .class_id = PCI_CLASS_STORAGE_IDE,
225 };
226
227 static void via_ide_register(void)
228 {
229 pci_qdev_register(&via_ide_info);
230 }
231 device_init(via_ide_register);