hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/pci/pci.h"
  29 #include "migration/vmstate.h"
  30 #include "qemu/module.h"
  31 #include "sysemu/dma.h"
  32 #include "hw/isa/vt82c686.h"
  33 #include "hw/ide/pci.h"
  34 #include "hw/irq.h"
  35 #include "trace.h"
  36
  37 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  38                            unsigned size)
  39 {
  40     BMDMAState *bm = opaque;
  41     uint32_t val;
  42
  43     if (size != 1) {
  44         return ((uint64_t)1 << (size * 8)) - 1;
  45     }
  46
  47     switch (addr & 3) {
  48     case 0:
  49         val = bm->cmd;
  50         break;
  51     case 2:
  52         val = bm->status;
  53         break;
  54     default:
  55         val = 0xff;
  56         break;
  57     }
  58
  59     trace_bmdma_read_via(addr, val);
  60     return val;
  61 }
  62
  63 static void bmdma_write(void *opaque, hwaddr addr,
  64                         uint64_t val, unsigned size)
  65 {
  66     BMDMAState *bm = opaque;
  67
  68     if (size != 1) {
  69         return;
  70     }
  71
  72     trace_bmdma_write_via(addr, val);
  73     switch (addr & 3) {
  74     case 0:
  75         bmdma_cmd_writeb(bm, val);
  76         break;
  77     case 2:
  78         bmdma_status_writeb(bm, val);
  79         break;
  80     default:;
  81     }
  82 }
  83
  84 static const MemoryRegionOps via_bmdma_ops = {
  85     .read = bmdma_read,
  86     .write = bmdma_write,
  87 };
  88
  89 static void bmdma_setup_bar(PCIIDEState *d)
  90 {
  91     int i;
  92
  93     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  94     for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) {
  95         BMDMAState *bm = &d->bmdma[i];
  96
  97         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
  98                               "via-bmdma", 4);
  99         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 100         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 101                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 102         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 103     }
 104 }
 105
 106 static void via_ide_set_irq(void *opaque, int n, int level)
 107 {
 108     PCIIDEState *s = opaque;
 109     PCIDevice *d = PCI_DEVICE(s);
 110
 111     if (level) {
 112         d->config[0x70 + n * 8] |= 0x80;
 113     } else {
 114         d->config[0x70 + n * 8] &= ~0x80;
 115     }
 116
 117     qemu_set_irq(s->isa_irq[n], level);
 118 }
 119
 120 static void via_ide_reset(DeviceState *dev)
 121 {
 122     PCIIDEState *d = PCI_IDE(dev);
 123     PCIDevice *pd = PCI_DEVICE(dev);
 124     uint8_t *pci_conf = pd->config;
 125     int i;
 126
 127     for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
 128         ide_bus_reset(&d->bus[i]);
 129     }
 130
 131     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT);
 132     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 133                  PCI_STATUS_DEVSEL_MEDIUM);
 134
 135     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
 136     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
 137     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
 138     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
 139     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
 140     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
 141
 142     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 143     pci_set_long(pci_conf + 0x40, 0x0a090600);
 144     /* IDE misc configuration 1/2/3 */
 145     pci_set_long(pci_conf + 0x44, 0x00c00068);
 146     /* IDE Timing control */
 147     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 148     /* IDE Address Setup Time */
 149     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 150     /* UltraDMA Extended Timing Control*/
 151     pci_set_long(pci_conf + 0x50, 0x07070707);
 152     /* UltraDMA FIFO Control */
 153     pci_set_long(pci_conf + 0x54, 0x00000004);
 154     /* IDE primary sector size */
 155     pci_set_long(pci_conf + 0x60, 0x00000200);
 156     /* IDE secondary sector size */
 157     pci_set_long(pci_conf + 0x68, 0x00000200);
 158     /* PCI PM Block */
 159     pci_set_long(pci_conf + 0xc0, 0x00020001);
 160 }
 161
 162 static void via_ide_realize(PCIDevice *dev, Error **errp)
 163 {
 164     PCIIDEState *d = PCI_IDE(dev);
 165     DeviceState *ds = DEVICE(dev);
 166     uint8_t *pci_conf = dev->config;
 167     int i;
 168
 169     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */
 170     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 171     dev->wmask[PCI_INTERRUPT_LINE] = 0;
 172     dev->wmask[PCI_CLASS_PROG] = 5;
 173
 174     memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
 175                           &d->bus[0], "via-ide0-data", 8);
 176     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
 177
 178     memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
 179                           &d->bus[0], "via-ide0-cmd", 4);
 180     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
 181
 182     memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
 183                           &d->bus[1], "via-ide1-data", 8);
 184     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
 185
 186     memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
 187                           &d->bus[1], "via-ide1-cmd", 4);
 188     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
 189
 190     bmdma_setup_bar(d);
 191     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 192
 193     qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus));
 194     for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
 195         ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS);
 196         ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
 197
 198         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 199         ide_bus_register_restart_cb(&d->bus[i]);
 200     }
 201 }
 202
 203 static void via_ide_exitfn(PCIDevice *dev)
 204 {
 205     PCIIDEState *d = PCI_IDE(dev);
 206     unsigned i;
 207
 208     for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) {
 209         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 210         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 211     }
 212 }
 213
 214 static void via_ide_class_init(ObjectClass *klass, void *data)
 215 {
 216     DeviceClass *dc = DEVICE_CLASS(klass);
 217     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 218
 219     dc->reset = via_ide_reset;
 220     dc->vmsd = &vmstate_ide_pci;
 221     /* Reason: only works as function of VIA southbridge */
 222     dc->user_creatable = false;
 223
 224     k->realize = via_ide_realize;
 225     k->exit = via_ide_exitfn;
 226     k->vendor_id = PCI_VENDOR_ID_VIA;
 227     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 228     k->revision = 0x06;
 229     k->class_id = PCI_CLASS_STORAGE_IDE;
 230     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 231 }
 232
 233 static const TypeInfo via_ide_info = {
 234     .name          = TYPE_VIA_IDE,
 235     .parent        = TYPE_PCI_IDE,
 236     .class_init    = via_ide_class_init,
 237 };
 238
 239 static void via_ide_register_types(void)
 240 {
 241     type_register_static(&via_ide_info);
 242 }
 243
 244 type_init(via_ide_register_types)