hw/intc/allwinner-a10-pic.c

   1 /*
   2  * Allwinner A10 interrupt controller device emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/sysbus.h"
  19 #include "hw/devices.h"
  20 #include "sysemu/sysemu.h"
  21 #include "hw/intc/allwinner-a10-pic.h"
  22
  23 static void aw_a10_pic_update(AwA10PICState *s)
  24 {
  25     uint8_t i;
  26     int irq = 0, fiq = 0, pending;
  27
  28     s->vector = 0;
  29
  30     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
  31         irq |= s->irq_pending[i] & ~s->mask[i];
  32         fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
  33
  34         if (!s->vector) {
  35             pending = ffs(s->irq_pending[i] & ~s->mask[i]);
  36             if (pending) {
  37                 s->vector = (i * 32 + pending - 1) * 4;
  38             }
  39         }
  40     }
  41
  42     qemu_set_irq(s->parent_irq, !!irq);
  43     qemu_set_irq(s->parent_fiq, !!fiq);
  44 }
  45
  46 static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
  47 {
  48     AwA10PICState *s = opaque;
  49
  50     if (level) {
  51         set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  52     } else {
  53         clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  54     }
  55     aw_a10_pic_update(s);
  56 }
  57
  58 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
  59 {
  60     AwA10PICState *s = opaque;
  61     uint8_t index = (offset & 0xc) / 4;
  62
  63     switch (offset) {
  64     case AW_A10_PIC_VECTOR:
  65         return s->vector;
  66     case AW_A10_PIC_BASE_ADDR:
  67         return s->base_addr;
  68     case AW_A10_PIC_PROTECT:
  69         return s->protect;
  70     case AW_A10_PIC_NMI:
  71         return s->nmi;
  72     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
  73         return s->irq_pending[index];
  74     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
  75         return s->fiq_pending[index];
  76     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  77         return s->select[index];
  78     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
  79         return s->enable[index];
  80     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
  81         return s->mask[index];
  82     default:
  83         qemu_log_mask(LOG_GUEST_ERROR,
  84                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  85         break;
  86     }
  87
  88     return 0;
  89 }
  90
  91 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
  92                              unsigned size)
  93 {
  94     AwA10PICState *s = opaque;
  95     uint8_t index = (offset & 0xc) / 4;
  96
  97     switch (offset) {
  98     case AW_A10_PIC_BASE_ADDR:
  99         s->base_addr = value & ~0x3;
 100     case AW_A10_PIC_PROTECT:
 101         s->protect = value;
 102         break;
 103     case AW_A10_PIC_NMI:
 104         s->nmi = value;
 105         break;
 106     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
 107         /*
 108          * The register is read-only; nevertheless, Linux (including
 109          * the version originally shipped by Allwinner) pretends to
 110          * write to the register. Just ignore it.
 111          */
 112         break;
 113     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
 114         s->fiq_pending[index] &= ~value;
 115         break;
 116     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
 117         s->select[index] = value;
 118         break;
 119     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
 120         s->enable[index] = value;
 121         break;
 122     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
 123         s->mask[index] = value;
 124         break;
 125     default:
 126         qemu_log_mask(LOG_GUEST_ERROR,
 127                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
 128         break;
 129     }
 130
 131     aw_a10_pic_update(s);
 132 }
 133
 134 static const MemoryRegionOps aw_a10_pic_ops = {
 135     .read = aw_a10_pic_read,
 136     .write = aw_a10_pic_write,
 137     .endianness = DEVICE_NATIVE_ENDIAN,
 138 };
 139
 140 static const VMStateDescription vmstate_aw_a10_pic = {
 141     .name = "a10.pic",
 142     .version_id = 1,
 143     .minimum_version_id = 1,
 144     .fields = (VMStateField[]) {
 145         VMSTATE_UINT32(vector, AwA10PICState),
 146         VMSTATE_UINT32(base_addr, AwA10PICState),
 147         VMSTATE_UINT32(protect, AwA10PICState),
 148         VMSTATE_UINT32(nmi, AwA10PICState),
 149         VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
 150         VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
 151         VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
 152         VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
 153         VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
 154         VMSTATE_END_OF_LIST()
 155     }
 156 };
 157
 158 static void aw_a10_pic_init(Object *obj)
 159 {
 160     AwA10PICState *s = AW_A10_PIC(obj);
 161     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 162
 163      qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
 164      sysbus_init_irq(dev, &s->parent_irq);
 165      sysbus_init_irq(dev, &s->parent_fiq);
 166      memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
 167                            TYPE_AW_A10_PIC, 0x400);
 168      sysbus_init_mmio(dev, &s->iomem);
 169 }
 170
 171 static void aw_a10_pic_reset(DeviceState *d)
 172 {
 173     AwA10PICState *s = AW_A10_PIC(d);
 174     uint8_t i;
 175
 176     s->base_addr = 0;
 177     s->protect = 0;
 178     s->nmi = 0;
 179     s->vector = 0;
 180     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
 181         s->irq_pending[i] = 0;
 182         s->fiq_pending[i] = 0;
 183         s->select[i] = 0;
 184         s->enable[i] = 0;
 185         s->mask[i] = 0;
 186     }
 187 }
 188
 189 static void aw_a10_pic_class_init(ObjectClass *klass, void *data)
 190 {
 191     DeviceClass *dc = DEVICE_CLASS(klass);
 192
 193     dc->reset = aw_a10_pic_reset;
 194     dc->desc = "allwinner a10 pic";
 195     dc->vmsd = &vmstate_aw_a10_pic;
 196  }
 197
 198 static const TypeInfo aw_a10_pic_info = {
 199     .name = TYPE_AW_A10_PIC,
 200     .parent = TYPE_SYS_BUS_DEVICE,
 201     .instance_size = sizeof(AwA10PICState),
 202     .instance_init = aw_a10_pic_init,
 203     .class_init = aw_a10_pic_class_init,
 204 };
 205
 206 static void aw_a10_register_types(void)
 207 {
 208     type_register_static(&aw_a10_pic_info);
 209 }
 210
 211 type_init(aw_a10_register_types);