2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
26 #include "qapi/visitor.h"
27 #include "hw/i386/apic.h"
28 #include "hw/i386/apic_internal.h"
30 #include "hw/boards.h"
31 #include "sysemu/hax.h"
32 #include "sysemu/kvm.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/sysbus.h"
35 #include "migration/vmstate.h"
37 static int apic_irq_delivered
;
38 bool apic_report_tpr_access
;
40 void cpu_set_apic_base(DeviceState
*dev
, uint64_t val
)
42 trace_cpu_set_apic_base(val
);
45 APICCommonState
*s
= APIC_COMMON(dev
);
46 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
47 /* switching to x2APIC, reset possibly modified xAPIC ID */
48 if (!(s
->apicbase
& MSR_IA32_APICBASE_EXTD
) &&
49 (val
& MSR_IA32_APICBASE_EXTD
)) {
50 s
->id
= s
->initial_apic_id
;
52 info
->set_base(s
, val
);
56 uint64_t cpu_get_apic_base(DeviceState
*dev
)
59 APICCommonState
*s
= APIC_COMMON(dev
);
60 trace_cpu_get_apic_base((uint64_t)s
->apicbase
);
63 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP
);
64 return MSR_IA32_APICBASE_BSP
;
68 void cpu_set_apic_tpr(DeviceState
*dev
, uint8_t val
)
71 APICCommonClass
*info
;
78 info
= APIC_COMMON_GET_CLASS(s
);
80 info
->set_tpr(s
, val
);
83 uint8_t cpu_get_apic_tpr(DeviceState
*dev
)
86 APICCommonClass
*info
;
93 info
= APIC_COMMON_GET_CLASS(s
);
95 return info
->get_tpr(s
);
98 void apic_enable_tpr_access_reporting(DeviceState
*dev
, bool enable
)
100 APICCommonState
*s
= APIC_COMMON(dev
);
101 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
103 apic_report_tpr_access
= enable
;
104 if (info
->enable_tpr_reporting
) {
105 info
->enable_tpr_reporting(s
, enable
);
109 void apic_enable_vapic(DeviceState
*dev
, hwaddr paddr
)
111 APICCommonState
*s
= APIC_COMMON(dev
);
112 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
114 s
->vapic_paddr
= paddr
;
115 info
->vapic_base_update(s
);
118 void apic_handle_tpr_access_report(DeviceState
*dev
, target_ulong ip
,
121 APICCommonState
*s
= APIC_COMMON(dev
);
123 vapic_report_tpr_access(s
->vapic
, CPU(s
->cpu
), ip
, access
);
126 void apic_report_irq_delivered(int delivered
)
128 apic_irq_delivered
+= delivered
;
130 trace_apic_report_irq_delivered(apic_irq_delivered
);
133 void apic_reset_irq_delivered(void)
135 /* Copy this into a local variable to encourage gcc to emit a plain
136 * register for a sys/sdt.h marker. For details on this workaround, see:
137 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
139 volatile int a_i_d
= apic_irq_delivered
;
140 trace_apic_reset_irq_delivered(a_i_d
);
142 apic_irq_delivered
= 0;
145 int apic_get_irq_delivered(void)
147 trace_apic_get_irq_delivered(apic_irq_delivered
);
149 return apic_irq_delivered
;
152 void apic_deliver_nmi(DeviceState
*dev
)
154 APICCommonState
*s
= APIC_COMMON(dev
);
155 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
157 info
->external_nmi(s
);
160 bool apic_next_timer(APICCommonState
*s
, int64_t current_time
)
164 /* We need to store the timer state separately to support APIC
165 * implementations that maintain a non-QEMU timer, e.g. inside the
166 * host kernel. This open-coded state allows us to migrate between
168 s
->timer_expiry
= -1;
170 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
) {
174 d
= (current_time
- s
->initial_count_load_time
) >> s
->count_shift
;
176 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
177 if (!s
->initial_count
) {
180 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) *
181 ((uint64_t)s
->initial_count
+ 1);
183 if (d
>= s
->initial_count
) {
186 d
= (uint64_t)s
->initial_count
+ 1;
188 s
->next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
189 s
->timer_expiry
= s
->next_time
;
193 uint32_t apic_get_current_count(APICCommonState
*s
)
197 d
= (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->initial_count_load_time
) >>
199 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
201 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
203 if (d
>= s
->initial_count
) {
206 val
= s
->initial_count
- d
;
212 void apic_init_reset(DeviceState
*dev
)
215 APICCommonClass
*info
;
221 s
= APIC_COMMON(dev
);
223 s
->spurious_vec
= 0xff;
226 memset(s
->isr
, 0, sizeof(s
->isr
));
227 memset(s
->tmr
, 0, sizeof(s
->tmr
));
228 memset(s
->irr
, 0, sizeof(s
->irr
));
229 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
230 s
->lvt
[i
] = APIC_LVT_MASKED
;
233 memset(s
->icr
, 0, sizeof(s
->icr
));
236 s
->initial_count
= 0;
237 s
->initial_count_load_time
= 0;
239 s
->wait_for_sipi
= !cpu_is_bsp(s
->cpu
);
244 s
->timer_expiry
= -1;
246 info
= APIC_COMMON_GET_CLASS(s
);
252 void apic_designate_bsp(DeviceState
*dev
, bool bsp
)
258 APICCommonState
*s
= APIC_COMMON(dev
);
260 s
->apicbase
|= MSR_IA32_APICBASE_BSP
;
262 s
->apicbase
&= ~MSR_IA32_APICBASE_BSP
;
266 static void apic_reset_common(DeviceState
*dev
)
268 APICCommonState
*s
= APIC_COMMON(dev
);
269 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
272 bsp
= s
->apicbase
& MSR_IA32_APICBASE_BSP
;
273 s
->apicbase
= APIC_DEFAULT_ADDRESS
| bsp
| MSR_IA32_APICBASE_ENABLE
;
274 s
->id
= s
->initial_apic_id
;
276 apic_reset_irq_delivered();
279 info
->vapic_base_update(s
);
281 apic_init_reset(dev
);
284 static const VMStateDescription vmstate_apic_common
;
286 static void apic_common_realize(DeviceState
*dev
, Error
**errp
)
288 APICCommonState
*s
= APIC_COMMON(dev
);
289 APICCommonClass
*info
;
290 static DeviceState
*vapic
;
291 uint32_t instance_id
= s
->initial_apic_id
;
293 /* Normally initial APIC ID should be no more than hundreds */
294 assert(instance_id
!= VMSTATE_INSTANCE_ID_ANY
);
296 info
= APIC_COMMON_GET_CLASS(s
);
297 info
->realize(dev
, errp
);
299 /* Note: We need at least 1M to map the VAPIC option ROM */
300 if (!vapic
&& s
->vapic_control
& VAPIC_ENABLE_MASK
&&
301 !hax_enabled() && current_machine
->ram_size
>= 1024 * 1024) {
302 vapic
= sysbus_create_simple("kvmvapic", -1, NULL
);
305 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
306 info
->enable_tpr_reporting(s
, true);
309 if (s
->legacy_instance_id
) {
310 instance_id
= VMSTATE_INSTANCE_ID_ANY
;
312 vmstate_register_with_alias_id(NULL
, instance_id
, &vmstate_apic_common
,
316 static void apic_common_unrealize(DeviceState
*dev
)
318 APICCommonState
*s
= APIC_COMMON(dev
);
319 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
321 vmstate_unregister(NULL
, &vmstate_apic_common
, s
);
322 info
->unrealize(dev
);
324 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
325 info
->enable_tpr_reporting(s
, false);
329 static int apic_pre_load(void *opaque
)
331 APICCommonState
*s
= APIC_COMMON(opaque
);
333 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
334 * so that's what apic_common_sipi_needed checks for. Reset to
335 * the value that is assumed when the apic_sipi subsection is
338 s
->wait_for_sipi
= 0;
342 static int apic_dispatch_pre_save(void *opaque
)
344 APICCommonState
*s
= APIC_COMMON(opaque
);
345 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
347 if (info
->pre_save
) {
354 static int apic_dispatch_post_load(void *opaque
, int version_id
)
356 APICCommonState
*s
= APIC_COMMON(opaque
);
357 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
359 if (info
->post_load
) {
365 static bool apic_common_sipi_needed(void *opaque
)
367 APICCommonState
*s
= APIC_COMMON(opaque
);
368 return s
->wait_for_sipi
!= 0;
371 static const VMStateDescription vmstate_apic_common_sipi
= {
374 .minimum_version_id
= 1,
375 .needed
= apic_common_sipi_needed
,
376 .fields
= (VMStateField
[]) {
377 VMSTATE_INT32(sipi_vector
, APICCommonState
),
378 VMSTATE_INT32(wait_for_sipi
, APICCommonState
),
379 VMSTATE_END_OF_LIST()
383 static const VMStateDescription vmstate_apic_common
= {
386 .minimum_version_id
= 3,
387 .pre_load
= apic_pre_load
,
388 .pre_save
= apic_dispatch_pre_save
,
389 .post_load
= apic_dispatch_post_load
,
390 .fields
= (VMStateField
[]) {
391 VMSTATE_UINT32(apicbase
, APICCommonState
),
392 VMSTATE_UINT8(id
, APICCommonState
),
393 VMSTATE_UINT8(arb_id
, APICCommonState
),
394 VMSTATE_UINT8(tpr
, APICCommonState
),
395 VMSTATE_UINT32(spurious_vec
, APICCommonState
),
396 VMSTATE_UINT8(log_dest
, APICCommonState
),
397 VMSTATE_UINT8(dest_mode
, APICCommonState
),
398 VMSTATE_UINT32_ARRAY(isr
, APICCommonState
, 8),
399 VMSTATE_UINT32_ARRAY(tmr
, APICCommonState
, 8),
400 VMSTATE_UINT32_ARRAY(irr
, APICCommonState
, 8),
401 VMSTATE_UINT32_ARRAY(lvt
, APICCommonState
, APIC_LVT_NB
),
402 VMSTATE_UINT32(esr
, APICCommonState
),
403 VMSTATE_UINT32_ARRAY(icr
, APICCommonState
, 2),
404 VMSTATE_UINT32(divide_conf
, APICCommonState
),
405 VMSTATE_INT32(count_shift
, APICCommonState
),
406 VMSTATE_UINT32(initial_count
, APICCommonState
),
407 VMSTATE_INT64(initial_count_load_time
, APICCommonState
),
408 VMSTATE_INT64(next_time
, APICCommonState
),
409 VMSTATE_INT64(timer_expiry
,
410 APICCommonState
), /* open-coded timer state */
411 VMSTATE_END_OF_LIST()
413 .subsections
= (const VMStateDescription
*[]) {
414 &vmstate_apic_common_sipi
,
419 static Property apic_properties_common
[] = {
420 DEFINE_PROP_UINT8("version", APICCommonState
, version
, 0x14),
421 DEFINE_PROP_BIT("vapic", APICCommonState
, vapic_control
, VAPIC_ENABLE_BIT
,
423 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState
, legacy_instance_id
,
425 DEFINE_PROP_END_OF_LIST(),
428 static void apic_common_get_id(Object
*obj
, Visitor
*v
, const char *name
,
429 void *opaque
, Error
**errp
)
431 APICCommonState
*s
= APIC_COMMON(obj
);
434 value
= s
->apicbase
& MSR_IA32_APICBASE_EXTD
? s
->initial_apic_id
: s
->id
;
435 visit_type_uint32(v
, name
, &value
, errp
);
438 static void apic_common_set_id(Object
*obj
, Visitor
*v
, const char *name
,
439 void *opaque
, Error
**errp
)
441 APICCommonState
*s
= APIC_COMMON(obj
);
442 DeviceState
*dev
= DEVICE(obj
);
446 qdev_prop_set_after_realize(dev
, name
, errp
);
450 if (!visit_type_uint32(v
, name
, &value
, errp
)) {
454 s
->initial_apic_id
= value
;
455 s
->id
= (uint8_t)value
;
458 static void apic_common_initfn(Object
*obj
)
460 APICCommonState
*s
= APIC_COMMON(obj
);
462 s
->id
= s
->initial_apic_id
= -1;
463 object_property_add(obj
, "id", "uint32",
465 apic_common_set_id
, NULL
, NULL
);
468 static void apic_common_class_init(ObjectClass
*klass
, void *data
)
470 DeviceClass
*dc
= DEVICE_CLASS(klass
);
472 dc
->reset
= apic_reset_common
;
473 device_class_set_props(dc
, apic_properties_common
);
474 dc
->realize
= apic_common_realize
;
475 dc
->unrealize
= apic_common_unrealize
;
477 * Reason: APIC and CPU need to be wired up by
478 * x86_cpu_apic_create()
480 dc
->user_creatable
= false;
483 static const TypeInfo apic_common_type
= {
484 .name
= TYPE_APIC_COMMON
,
485 .parent
= TYPE_DEVICE
,
486 .instance_size
= sizeof(APICCommonState
),
487 .instance_init
= apic_common_initfn
,
488 .class_size
= sizeof(APICCommonClass
),
489 .class_init
= apic_common_class_init
,
493 static void apic_common_register_types(void)
495 type_register_static(&apic_common_type
);
498 type_init(apic_common_register_types
)