2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
25 #include "qapi/visitor.h"
26 #include "hw/i386/apic.h"
27 #include "hw/i386/apic_internal.h"
28 #include "hw/intc/kvm_irqcount.h"
30 #include "hw/boards.h"
31 #include "sysemu/kvm.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
36 bool apic_report_tpr_access
;
38 void cpu_set_apic_base(DeviceState
*dev
, uint64_t val
)
40 trace_cpu_set_apic_base(val
);
43 APICCommonState
*s
= APIC_COMMON(dev
);
44 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
45 /* switching to x2APIC, reset possibly modified xAPIC ID */
46 if (!(s
->apicbase
& MSR_IA32_APICBASE_EXTD
) &&
47 (val
& MSR_IA32_APICBASE_EXTD
)) {
48 s
->id
= s
->initial_apic_id
;
50 info
->set_base(s
, val
);
54 uint64_t cpu_get_apic_base(DeviceState
*dev
)
57 APICCommonState
*s
= APIC_COMMON(dev
);
58 trace_cpu_get_apic_base((uint64_t)s
->apicbase
);
61 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP
);
62 return MSR_IA32_APICBASE_BSP
;
66 void cpu_set_apic_tpr(DeviceState
*dev
, uint8_t val
)
69 APICCommonClass
*info
;
76 info
= APIC_COMMON_GET_CLASS(s
);
78 info
->set_tpr(s
, val
);
81 uint8_t cpu_get_apic_tpr(DeviceState
*dev
)
84 APICCommonClass
*info
;
91 info
= APIC_COMMON_GET_CLASS(s
);
93 return info
->get_tpr(s
);
96 void apic_enable_tpr_access_reporting(DeviceState
*dev
, bool enable
)
98 APICCommonState
*s
= APIC_COMMON(dev
);
99 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
101 apic_report_tpr_access
= enable
;
102 if (info
->enable_tpr_reporting
) {
103 info
->enable_tpr_reporting(s
, enable
);
107 void apic_enable_vapic(DeviceState
*dev
, hwaddr paddr
)
109 APICCommonState
*s
= APIC_COMMON(dev
);
110 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
112 s
->vapic_paddr
= paddr
;
113 info
->vapic_base_update(s
);
116 void apic_handle_tpr_access_report(DeviceState
*dev
, target_ulong ip
,
119 APICCommonState
*s
= APIC_COMMON(dev
);
121 vapic_report_tpr_access(s
->vapic
, CPU(s
->cpu
), ip
, access
);
124 void apic_deliver_nmi(DeviceState
*dev
)
126 APICCommonState
*s
= APIC_COMMON(dev
);
127 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
129 info
->external_nmi(s
);
132 bool apic_next_timer(APICCommonState
*s
, int64_t current_time
)
136 /* We need to store the timer state separately to support APIC
137 * implementations that maintain a non-QEMU timer, e.g. inside the
138 * host kernel. This open-coded state allows us to migrate between
140 s
->timer_expiry
= -1;
142 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
) {
146 d
= (current_time
- s
->initial_count_load_time
) >> s
->count_shift
;
148 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
149 if (!s
->initial_count
) {
152 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) *
153 ((uint64_t)s
->initial_count
+ 1);
155 if (d
>= s
->initial_count
) {
158 d
= (uint64_t)s
->initial_count
+ 1;
160 s
->next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
161 s
->timer_expiry
= s
->next_time
;
165 uint32_t apic_get_current_count(APICCommonState
*s
)
169 d
= (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->initial_count_load_time
) >>
171 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
173 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
175 if (d
>= s
->initial_count
) {
178 val
= s
->initial_count
- d
;
184 void apic_init_reset(DeviceState
*dev
)
187 APICCommonClass
*info
;
193 s
= APIC_COMMON(dev
);
195 s
->spurious_vec
= 0xff;
198 memset(s
->isr
, 0, sizeof(s
->isr
));
199 memset(s
->tmr
, 0, sizeof(s
->tmr
));
200 memset(s
->irr
, 0, sizeof(s
->irr
));
201 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
202 s
->lvt
[i
] = APIC_LVT_MASKED
;
205 memset(s
->icr
, 0, sizeof(s
->icr
));
208 s
->initial_count
= 0;
209 s
->initial_count_load_time
= 0;
211 s
->wait_for_sipi
= !cpu_is_bsp(s
->cpu
);
216 s
->timer_expiry
= -1;
218 info
= APIC_COMMON_GET_CLASS(s
);
224 void apic_designate_bsp(DeviceState
*dev
, bool bsp
)
230 APICCommonState
*s
= APIC_COMMON(dev
);
232 s
->apicbase
|= MSR_IA32_APICBASE_BSP
;
234 s
->apicbase
&= ~MSR_IA32_APICBASE_BSP
;
238 static void apic_reset_common(DeviceState
*dev
)
240 APICCommonState
*s
= APIC_COMMON(dev
);
241 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
244 bsp
= s
->apicbase
& MSR_IA32_APICBASE_BSP
;
245 s
->apicbase
= APIC_DEFAULT_ADDRESS
| bsp
| MSR_IA32_APICBASE_ENABLE
;
246 s
->id
= s
->initial_apic_id
;
248 kvm_reset_irq_delivered();
251 info
->vapic_base_update(s
);
253 apic_init_reset(dev
);
256 static const VMStateDescription vmstate_apic_common
;
258 static void apic_common_realize(DeviceState
*dev
, Error
**errp
)
260 APICCommonState
*s
= APIC_COMMON(dev
);
261 APICCommonClass
*info
;
262 static DeviceState
*vapic
;
263 uint32_t instance_id
= s
->initial_apic_id
;
265 /* Normally initial APIC ID should be no more than hundreds */
266 assert(instance_id
!= VMSTATE_INSTANCE_ID_ANY
);
268 info
= APIC_COMMON_GET_CLASS(s
);
269 info
->realize(dev
, errp
);
271 /* Note: We need at least 1M to map the VAPIC option ROM */
272 if (!vapic
&& s
->vapic_control
& VAPIC_ENABLE_MASK
&&
273 current_machine
->ram_size
>= 1024 * 1024) {
274 vapic
= sysbus_create_simple("kvmvapic", -1, NULL
);
277 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
278 info
->enable_tpr_reporting(s
, true);
281 if (s
->legacy_instance_id
) {
282 instance_id
= VMSTATE_INSTANCE_ID_ANY
;
284 vmstate_register_with_alias_id(NULL
, instance_id
, &vmstate_apic_common
,
288 static void apic_common_unrealize(DeviceState
*dev
)
290 APICCommonState
*s
= APIC_COMMON(dev
);
291 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
293 vmstate_unregister(NULL
, &vmstate_apic_common
, s
);
294 info
->unrealize(dev
);
296 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
297 info
->enable_tpr_reporting(s
, false);
301 static int apic_pre_load(void *opaque
)
303 APICCommonState
*s
= APIC_COMMON(opaque
);
305 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
306 * so that's what apic_common_sipi_needed checks for. Reset to
307 * the value that is assumed when the apic_sipi subsection is
310 s
->wait_for_sipi
= 0;
314 static int apic_dispatch_pre_save(void *opaque
)
316 APICCommonState
*s
= APIC_COMMON(opaque
);
317 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
319 if (info
->pre_save
) {
326 static int apic_dispatch_post_load(void *opaque
, int version_id
)
328 APICCommonState
*s
= APIC_COMMON(opaque
);
329 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
331 if (info
->post_load
) {
337 static bool apic_common_sipi_needed(void *opaque
)
339 APICCommonState
*s
= APIC_COMMON(opaque
);
340 return s
->wait_for_sipi
!= 0;
343 static const VMStateDescription vmstate_apic_common_sipi
= {
346 .minimum_version_id
= 1,
347 .needed
= apic_common_sipi_needed
,
348 .fields
= (VMStateField
[]) {
349 VMSTATE_INT32(sipi_vector
, APICCommonState
),
350 VMSTATE_INT32(wait_for_sipi
, APICCommonState
),
351 VMSTATE_END_OF_LIST()
355 static const VMStateDescription vmstate_apic_common
= {
358 .minimum_version_id
= 3,
359 .pre_load
= apic_pre_load
,
360 .pre_save
= apic_dispatch_pre_save
,
361 .post_load
= apic_dispatch_post_load
,
362 .fields
= (VMStateField
[]) {
363 VMSTATE_UINT32(apicbase
, APICCommonState
),
364 VMSTATE_UINT8(id
, APICCommonState
),
365 VMSTATE_UINT8(arb_id
, APICCommonState
),
366 VMSTATE_UINT8(tpr
, APICCommonState
),
367 VMSTATE_UINT32(spurious_vec
, APICCommonState
),
368 VMSTATE_UINT8(log_dest
, APICCommonState
),
369 VMSTATE_UINT8(dest_mode
, APICCommonState
),
370 VMSTATE_UINT32_ARRAY(isr
, APICCommonState
, 8),
371 VMSTATE_UINT32_ARRAY(tmr
, APICCommonState
, 8),
372 VMSTATE_UINT32_ARRAY(irr
, APICCommonState
, 8),
373 VMSTATE_UINT32_ARRAY(lvt
, APICCommonState
, APIC_LVT_NB
),
374 VMSTATE_UINT32(esr
, APICCommonState
),
375 VMSTATE_UINT32_ARRAY(icr
, APICCommonState
, 2),
376 VMSTATE_UINT32(divide_conf
, APICCommonState
),
377 VMSTATE_INT32(count_shift
, APICCommonState
),
378 VMSTATE_UINT32(initial_count
, APICCommonState
),
379 VMSTATE_INT64(initial_count_load_time
, APICCommonState
),
380 VMSTATE_INT64(next_time
, APICCommonState
),
381 VMSTATE_INT64(timer_expiry
,
382 APICCommonState
), /* open-coded timer state */
383 VMSTATE_END_OF_LIST()
385 .subsections
= (const VMStateDescription
*[]) {
386 &vmstate_apic_common_sipi
,
391 static Property apic_properties_common
[] = {
392 DEFINE_PROP_UINT8("version", APICCommonState
, version
, 0x14),
393 DEFINE_PROP_BIT("vapic", APICCommonState
, vapic_control
, VAPIC_ENABLE_BIT
,
395 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState
, legacy_instance_id
,
397 DEFINE_PROP_END_OF_LIST(),
400 static void apic_common_get_id(Object
*obj
, Visitor
*v
, const char *name
,
401 void *opaque
, Error
**errp
)
403 APICCommonState
*s
= APIC_COMMON(obj
);
406 value
= s
->apicbase
& MSR_IA32_APICBASE_EXTD
? s
->initial_apic_id
: s
->id
;
407 visit_type_uint32(v
, name
, &value
, errp
);
410 static void apic_common_set_id(Object
*obj
, Visitor
*v
, const char *name
,
411 void *opaque
, Error
**errp
)
413 APICCommonState
*s
= APIC_COMMON(obj
);
414 DeviceState
*dev
= DEVICE(obj
);
418 qdev_prop_set_after_realize(dev
, name
, errp
);
422 if (!visit_type_uint32(v
, name
, &value
, errp
)) {
426 s
->initial_apic_id
= value
;
427 s
->id
= (uint8_t)value
;
430 static void apic_common_initfn(Object
*obj
)
432 APICCommonState
*s
= APIC_COMMON(obj
);
434 s
->id
= s
->initial_apic_id
= -1;
435 object_property_add(obj
, "id", "uint32",
437 apic_common_set_id
, NULL
, NULL
);
440 static void apic_common_class_init(ObjectClass
*klass
, void *data
)
442 DeviceClass
*dc
= DEVICE_CLASS(klass
);
444 dc
->reset
= apic_reset_common
;
445 device_class_set_props(dc
, apic_properties_common
);
446 dc
->realize
= apic_common_realize
;
447 dc
->unrealize
= apic_common_unrealize
;
449 * Reason: APIC and CPU need to be wired up by
450 * x86_cpu_apic_create()
452 dc
->user_creatable
= false;
455 static const TypeInfo apic_common_type
= {
456 .name
= TYPE_APIC_COMMON
,
457 .parent
= TYPE_DEVICE
,
458 .instance_size
= sizeof(APICCommonState
),
459 .instance_init
= apic_common_initfn
,
460 .class_size
= sizeof(APICCommonClass
),
461 .class_init
= apic_common_class_init
,
465 static void apic_common_register_types(void)
467 type_register_static(&apic_common_type
);
470 type_init(apic_common_register_types
)