2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
26 #include "qapi/visitor.h"
27 #include "hw/i386/apic.h"
28 #include "hw/i386/apic_internal.h"
30 #include "sysemu/hax.h"
31 #include "sysemu/kvm.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/qemu-file-types.h"
35 #include "migration/vmstate.h"
37 static int apic_irq_delivered
;
38 bool apic_report_tpr_access
;
40 void cpu_set_apic_base(DeviceState
*dev
, uint64_t val
)
42 trace_cpu_set_apic_base(val
);
45 APICCommonState
*s
= APIC_COMMON(dev
);
46 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
47 /* switching to x2APIC, reset possibly modified xAPIC ID */
48 if (!(s
->apicbase
& MSR_IA32_APICBASE_EXTD
) &&
49 (val
& MSR_IA32_APICBASE_EXTD
)) {
50 s
->id
= s
->initial_apic_id
;
52 info
->set_base(s
, val
);
56 uint64_t cpu_get_apic_base(DeviceState
*dev
)
59 APICCommonState
*s
= APIC_COMMON(dev
);
60 trace_cpu_get_apic_base((uint64_t)s
->apicbase
);
63 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP
);
64 return MSR_IA32_APICBASE_BSP
;
68 void cpu_set_apic_tpr(DeviceState
*dev
, uint8_t val
)
71 APICCommonClass
*info
;
78 info
= APIC_COMMON_GET_CLASS(s
);
80 info
->set_tpr(s
, val
);
83 uint8_t cpu_get_apic_tpr(DeviceState
*dev
)
86 APICCommonClass
*info
;
93 info
= APIC_COMMON_GET_CLASS(s
);
95 return info
->get_tpr(s
);
98 void apic_enable_tpr_access_reporting(DeviceState
*dev
, bool enable
)
100 APICCommonState
*s
= APIC_COMMON(dev
);
101 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
103 apic_report_tpr_access
= enable
;
104 if (info
->enable_tpr_reporting
) {
105 info
->enable_tpr_reporting(s
, enable
);
109 void apic_enable_vapic(DeviceState
*dev
, hwaddr paddr
)
111 APICCommonState
*s
= APIC_COMMON(dev
);
112 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
114 s
->vapic_paddr
= paddr
;
115 info
->vapic_base_update(s
);
118 void apic_handle_tpr_access_report(DeviceState
*dev
, target_ulong ip
,
121 APICCommonState
*s
= APIC_COMMON(dev
);
123 vapic_report_tpr_access(s
->vapic
, CPU(s
->cpu
), ip
, access
);
126 void apic_report_irq_delivered(int delivered
)
128 apic_irq_delivered
+= delivered
;
130 trace_apic_report_irq_delivered(apic_irq_delivered
);
133 void apic_reset_irq_delivered(void)
135 /* Copy this into a local variable to encourage gcc to emit a plain
136 * register for a sys/sdt.h marker. For details on this workaround, see:
137 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
139 volatile int a_i_d
= apic_irq_delivered
;
140 trace_apic_reset_irq_delivered(a_i_d
);
142 apic_irq_delivered
= 0;
145 int apic_get_irq_delivered(void)
147 trace_apic_get_irq_delivered(apic_irq_delivered
);
149 return apic_irq_delivered
;
152 void apic_deliver_nmi(DeviceState
*dev
)
154 APICCommonState
*s
= APIC_COMMON(dev
);
155 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
157 info
->external_nmi(s
);
160 bool apic_next_timer(APICCommonState
*s
, int64_t current_time
)
164 /* We need to store the timer state separately to support APIC
165 * implementations that maintain a non-QEMU timer, e.g. inside the
166 * host kernel. This open-coded state allows us to migrate between
168 s
->timer_expiry
= -1;
170 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
) {
174 d
= (current_time
- s
->initial_count_load_time
) >> s
->count_shift
;
176 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
177 if (!s
->initial_count
) {
180 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) *
181 ((uint64_t)s
->initial_count
+ 1);
183 if (d
>= s
->initial_count
) {
186 d
= (uint64_t)s
->initial_count
+ 1;
188 s
->next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
189 s
->timer_expiry
= s
->next_time
;
193 void apic_init_reset(DeviceState
*dev
)
196 APICCommonClass
*info
;
202 s
= APIC_COMMON(dev
);
204 s
->spurious_vec
= 0xff;
207 memset(s
->isr
, 0, sizeof(s
->isr
));
208 memset(s
->tmr
, 0, sizeof(s
->tmr
));
209 memset(s
->irr
, 0, sizeof(s
->irr
));
210 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
211 s
->lvt
[i
] = APIC_LVT_MASKED
;
214 memset(s
->icr
, 0, sizeof(s
->icr
));
217 s
->initial_count
= 0;
218 s
->initial_count_load_time
= 0;
220 s
->wait_for_sipi
= !cpu_is_bsp(s
->cpu
);
225 s
->timer_expiry
= -1;
227 info
= APIC_COMMON_GET_CLASS(s
);
233 void apic_designate_bsp(DeviceState
*dev
, bool bsp
)
239 APICCommonState
*s
= APIC_COMMON(dev
);
241 s
->apicbase
|= MSR_IA32_APICBASE_BSP
;
243 s
->apicbase
&= ~MSR_IA32_APICBASE_BSP
;
247 static void apic_reset_common(DeviceState
*dev
)
249 APICCommonState
*s
= APIC_COMMON(dev
);
250 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
253 bsp
= s
->apicbase
& MSR_IA32_APICBASE_BSP
;
254 s
->apicbase
= APIC_DEFAULT_ADDRESS
| bsp
| MSR_IA32_APICBASE_ENABLE
;
255 s
->id
= s
->initial_apic_id
;
257 apic_reset_irq_delivered();
260 info
->vapic_base_update(s
);
262 apic_init_reset(dev
);
265 /* This function is only used for old state version 1 and 2 */
266 static int apic_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
268 APICCommonState
*s
= opaque
;
269 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
272 if (version_id
> 2) {
276 /* XXX: what if the base changes? (registered memory regions) */
277 qemu_get_be32s(f
, &s
->apicbase
);
278 qemu_get_8s(f
, &s
->id
);
279 qemu_get_8s(f
, &s
->arb_id
);
280 qemu_get_8s(f
, &s
->tpr
);
281 qemu_get_be32s(f
, &s
->spurious_vec
);
282 qemu_get_8s(f
, &s
->log_dest
);
283 qemu_get_8s(f
, &s
->dest_mode
);
284 for (i
= 0; i
< 8; i
++) {
285 qemu_get_be32s(f
, &s
->isr
[i
]);
286 qemu_get_be32s(f
, &s
->tmr
[i
]);
287 qemu_get_be32s(f
, &s
->irr
[i
]);
289 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
290 qemu_get_be32s(f
, &s
->lvt
[i
]);
292 qemu_get_be32s(f
, &s
->esr
);
293 qemu_get_be32s(f
, &s
->icr
[0]);
294 qemu_get_be32s(f
, &s
->icr
[1]);
295 qemu_get_be32s(f
, &s
->divide_conf
);
296 s
->count_shift
= qemu_get_be32(f
);
297 qemu_get_be32s(f
, &s
->initial_count
);
298 s
->initial_count_load_time
= qemu_get_be64(f
);
299 s
->next_time
= qemu_get_be64(f
);
301 if (version_id
>= 2) {
302 s
->timer_expiry
= qemu_get_be64(f
);
305 if (info
->post_load
) {
311 static const VMStateDescription vmstate_apic_common
;
313 static void apic_common_realize(DeviceState
*dev
, Error
**errp
)
315 APICCommonState
*s
= APIC_COMMON(dev
);
316 APICCommonClass
*info
;
317 static DeviceState
*vapic
;
318 int instance_id
= s
->id
;
320 info
= APIC_COMMON_GET_CLASS(s
);
321 info
->realize(dev
, errp
);
323 /* Note: We need at least 1M to map the VAPIC option ROM */
324 if (!vapic
&& s
->vapic_control
& VAPIC_ENABLE_MASK
&&
325 !hax_enabled() && ram_size
>= 1024 * 1024) {
326 vapic
= sysbus_create_simple("kvmvapic", -1, NULL
);
329 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
330 info
->enable_tpr_reporting(s
, true);
333 if (s
->legacy_instance_id
) {
336 vmstate_register_with_alias_id(NULL
, instance_id
, &vmstate_apic_common
,
340 static void apic_common_unrealize(DeviceState
*dev
, Error
**errp
)
342 APICCommonState
*s
= APIC_COMMON(dev
);
343 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
345 vmstate_unregister(NULL
, &vmstate_apic_common
, s
);
346 info
->unrealize(dev
, errp
);
348 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
349 info
->enable_tpr_reporting(s
, false);
353 static int apic_pre_load(void *opaque
)
355 APICCommonState
*s
= APIC_COMMON(opaque
);
357 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
358 * so that's what apic_common_sipi_needed checks for. Reset to
359 * the value that is assumed when the apic_sipi subsection is
362 s
->wait_for_sipi
= 0;
366 static int apic_dispatch_pre_save(void *opaque
)
368 APICCommonState
*s
= APIC_COMMON(opaque
);
369 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
371 if (info
->pre_save
) {
378 static int apic_dispatch_post_load(void *opaque
, int version_id
)
380 APICCommonState
*s
= APIC_COMMON(opaque
);
381 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
383 if (info
->post_load
) {
389 static bool apic_common_sipi_needed(void *opaque
)
391 APICCommonState
*s
= APIC_COMMON(opaque
);
392 return s
->wait_for_sipi
!= 0;
395 static const VMStateDescription vmstate_apic_common_sipi
= {
398 .minimum_version_id
= 1,
399 .needed
= apic_common_sipi_needed
,
400 .fields
= (VMStateField
[]) {
401 VMSTATE_INT32(sipi_vector
, APICCommonState
),
402 VMSTATE_INT32(wait_for_sipi
, APICCommonState
),
403 VMSTATE_END_OF_LIST()
407 static const VMStateDescription vmstate_apic_common
= {
410 .minimum_version_id
= 3,
411 .minimum_version_id_old
= 1,
412 .load_state_old
= apic_load_old
,
413 .pre_load
= apic_pre_load
,
414 .pre_save
= apic_dispatch_pre_save
,
415 .post_load
= apic_dispatch_post_load
,
416 .fields
= (VMStateField
[]) {
417 VMSTATE_UINT32(apicbase
, APICCommonState
),
418 VMSTATE_UINT8(id
, APICCommonState
),
419 VMSTATE_UINT8(arb_id
, APICCommonState
),
420 VMSTATE_UINT8(tpr
, APICCommonState
),
421 VMSTATE_UINT32(spurious_vec
, APICCommonState
),
422 VMSTATE_UINT8(log_dest
, APICCommonState
),
423 VMSTATE_UINT8(dest_mode
, APICCommonState
),
424 VMSTATE_UINT32_ARRAY(isr
, APICCommonState
, 8),
425 VMSTATE_UINT32_ARRAY(tmr
, APICCommonState
, 8),
426 VMSTATE_UINT32_ARRAY(irr
, APICCommonState
, 8),
427 VMSTATE_UINT32_ARRAY(lvt
, APICCommonState
, APIC_LVT_NB
),
428 VMSTATE_UINT32(esr
, APICCommonState
),
429 VMSTATE_UINT32_ARRAY(icr
, APICCommonState
, 2),
430 VMSTATE_UINT32(divide_conf
, APICCommonState
),
431 VMSTATE_INT32(count_shift
, APICCommonState
),
432 VMSTATE_UINT32(initial_count
, APICCommonState
),
433 VMSTATE_INT64(initial_count_load_time
, APICCommonState
),
434 VMSTATE_INT64(next_time
, APICCommonState
),
435 VMSTATE_INT64(timer_expiry
,
436 APICCommonState
), /* open-coded timer state */
437 VMSTATE_END_OF_LIST()
439 .subsections
= (const VMStateDescription
*[]) {
440 &vmstate_apic_common_sipi
,
445 static Property apic_properties_common
[] = {
446 DEFINE_PROP_UINT8("version", APICCommonState
, version
, 0x14),
447 DEFINE_PROP_BIT("vapic", APICCommonState
, vapic_control
, VAPIC_ENABLE_BIT
,
449 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState
, legacy_instance_id
,
451 DEFINE_PROP_END_OF_LIST(),
454 static void apic_common_get_id(Object
*obj
, Visitor
*v
, const char *name
,
455 void *opaque
, Error
**errp
)
457 APICCommonState
*s
= APIC_COMMON(obj
);
460 value
= s
->apicbase
& MSR_IA32_APICBASE_EXTD
? s
->initial_apic_id
: s
->id
;
461 visit_type_uint32(v
, name
, &value
, errp
);
464 static void apic_common_set_id(Object
*obj
, Visitor
*v
, const char *name
,
465 void *opaque
, Error
**errp
)
467 APICCommonState
*s
= APIC_COMMON(obj
);
468 DeviceState
*dev
= DEVICE(obj
);
469 Error
*local_err
= NULL
;
473 qdev_prop_set_after_realize(dev
, name
, errp
);
477 visit_type_uint32(v
, name
, &value
, &local_err
);
479 error_propagate(errp
, local_err
);
483 s
->initial_apic_id
= value
;
484 s
->id
= (uint8_t)value
;
487 static void apic_common_initfn(Object
*obj
)
489 APICCommonState
*s
= APIC_COMMON(obj
);
491 s
->id
= s
->initial_apic_id
= -1;
492 object_property_add(obj
, "id", "uint32",
494 apic_common_set_id
, NULL
, NULL
, NULL
);
497 static void apic_common_class_init(ObjectClass
*klass
, void *data
)
499 DeviceClass
*dc
= DEVICE_CLASS(klass
);
501 dc
->reset
= apic_reset_common
;
502 dc
->props
= apic_properties_common
;
503 dc
->realize
= apic_common_realize
;
504 dc
->unrealize
= apic_common_unrealize
;
506 * Reason: APIC and CPU need to be wired up by
507 * x86_cpu_apic_create()
509 dc
->user_creatable
= false;
512 static const TypeInfo apic_common_type
= {
513 .name
= TYPE_APIC_COMMON
,
514 .parent
= TYPE_DEVICE
,
515 .instance_size
= sizeof(APICCommonState
),
516 .instance_init
= apic_common_initfn
,
517 .class_size
= sizeof(APICCommonClass
),
518 .class_init
= apic_common_class_init
,
522 static void apic_common_register_types(void)
524 type_register_static(&apic_common_type
);
527 type_init(apic_common_register_types
)