2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
28 #include "sysemu/kvm.h"
30 /* #define DEBUG_GIC */
33 #define DEBUG_GIC_GATE 1
35 #define DEBUG_GIC_GATE 0
38 #define DPRINTF(fmt, ...) do { \
39 if (DEBUG_GIC_GATE) { \
40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
44 static const uint8_t gic_id_11mpcore
[] = {
45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
48 static const uint8_t gic_id_gicv1
[] = {
49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
52 static const uint8_t gic_id_gicv2
[] = {
53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
56 static inline int gic_get_current_cpu(GICState
*s
)
59 return current_cpu
->cpu_index
;
64 /* Return true if this GIC config has interrupt groups, which is
65 * true if we're a GICv2, or a GICv1 with the security extensions.
67 static inline bool gic_has_groups(GICState
*s
)
69 return s
->revision
== 2 || s
->security_extn
;
72 /* TODO: Many places that call this routine could be optimized. */
73 /* Update interrupt status after enabled or pending bits have been changed. */
74 void gic_update(GICState
*s
)
79 int irq_level
, fiq_level
;
83 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
85 s
->current_pending
[cpu
] = 1023;
86 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
87 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
88 qemu_irq_lower(s
->parent_irq
[cpu
]);
89 qemu_irq_lower(s
->parent_fiq
[cpu
]);
94 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
95 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
96 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
97 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
98 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
104 if (best_irq
!= 1023) {
105 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
106 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
109 irq_level
= fiq_level
= 0;
111 if (best_prio
< s
->priority_mask
[cpu
]) {
112 s
->current_pending
[cpu
] = best_irq
;
113 if (best_prio
< s
->running_priority
[cpu
]) {
114 int group
= GIC_TEST_GROUP(best_irq
, cm
);
116 if (extract32(s
->ctlr
, group
, 1) &&
117 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
118 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
119 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
122 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
124 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
127 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
133 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
134 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
138 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
142 if (gic_test_pending(s
, irq
, cm
)) {
146 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
147 GIC_SET_PENDING(irq
, cm
);
151 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
155 GIC_SET_LEVEL(irq
, cm
);
156 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
157 DPRINTF("Set %d pending mask %x\n", irq
, target
);
158 GIC_SET_PENDING(irq
, target
);
161 GIC_CLEAR_LEVEL(irq
, cm
);
165 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
169 GIC_SET_LEVEL(irq
, cm
);
170 DPRINTF("Set %d pending mask %x\n", irq
, target
);
171 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
172 GIC_SET_PENDING(irq
, target
);
175 GIC_CLEAR_LEVEL(irq
, cm
);
179 /* Process a change in an external IRQ input. */
180 static void gic_set_irq(void *opaque
, int irq
, int level
)
182 /* Meaning of the 'irq' parameter:
183 * [0..N-1] : external interrupts
184 * [N..N+31] : PPI (internal) interrupts for CPU 0
185 * [N+32..N+63] : PPI (internal interrupts for CPU 1
188 GICState
*s
= (GICState
*)opaque
;
190 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
191 /* The first external input line is internal interrupt 32. */
194 target
= GIC_TARGET(irq
);
197 irq
-= (s
->num_irq
- GIC_INTERNAL
);
198 cpu
= irq
/ GIC_INTERNAL
;
204 assert(irq
>= GIC_NR_SGIS
);
206 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
210 if (s
->revision
== REV_11MPCORE
) {
211 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
213 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
215 trace_gic_set_irq(irq
, level
, cm
, target
);
220 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
223 uint16_t pending_irq
= s
->current_pending
[cpu
];
225 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
226 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
227 /* On a GIC without the security extensions, reading this register
228 * behaves in the same way as a secure access to a GIC with them.
230 bool secure
= !s
->security_extn
|| attrs
.secure
;
232 if (group
== 0 && !secure
) {
233 /* Group0 interrupts hidden from Non-secure access */
236 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
237 /* Group1 interrupts only seen by Secure access if
246 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
248 /* Return the group priority of the specified interrupt
249 * (which is the top bits of its priority, with the number
250 * of bits masked determined by the applicable binary point register).
255 if (gic_has_groups(s
) &&
256 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
257 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
263 /* a BPR of 0 means the group priority bits are [7:1];
264 * a BPR of 1 means they are [7:2], and so on down to
265 * a BPR of 7 meaning no group priority bits at all.
267 mask
= ~0U << ((bpr
& 7) + 1);
269 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
272 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
274 /* Set the appropriate Active Priority Register bit for this IRQ,
275 * and update the running priority.
277 int prio
= gic_get_group_priority(s
, cpu
, irq
);
278 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
279 int regno
= preemption_level
/ 32;
280 int bitno
= preemption_level
% 32;
282 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
283 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
285 s
->apr
[regno
][cpu
] |= (1 << bitno
);
288 s
->running_priority
[cpu
] = prio
;
289 GIC_SET_ACTIVE(irq
, 1 << cpu
);
292 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
294 /* Recalculate the current running priority for this CPU based
295 * on the set bits in the Active Priority Registers.
298 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
299 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
303 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
308 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
310 /* Drop the priority of the currently active interrupt in the
313 * Note that we can guarantee (because of the requirement to nest
314 * GICC_IAR reads [which activate an interrupt and raise priority]
315 * with GICC_EOIR writes [which drop the priority for the interrupt])
316 * that the interrupt we're being called for is the highest priority
317 * active interrupt, meaning that it has the lowest set bit in the
320 * If the guest does not honour the ordering constraints then the
321 * behaviour of the GIC is UNPREDICTABLE, which for us means that
322 * the values of the APR registers might become incorrect and the
323 * running priority will be wrong, so interrupts that should preempt
324 * might not do so, and interrupts that should not preempt might do so.
328 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
329 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
333 /* Clear lowest set bit */
338 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
341 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
346 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
347 * for the case where this GIC supports grouping and the pending interrupt
348 * is in the wrong group.
350 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
351 trace_gic_acknowledge_irq(cpu
, irq
);
353 if (irq
>= GIC_MAXIRQ
) {
354 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
358 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
359 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
363 if (s
->revision
== REV_11MPCORE
) {
364 /* Clear pending flags for both level and edge triggered interrupts.
365 * Level triggered IRQs will be reasserted once they become inactive.
367 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
370 if (irq
< GIC_NR_SGIS
) {
371 /* Lookup the source CPU for the SGI and clear this in the
372 * sgi_pending map. Return the src and clear the overall pending
373 * state on this CPU if the SGI is not pending from any CPUs.
375 assert(s
->sgi_pending
[irq
][cpu
] != 0);
376 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
377 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
378 if (s
->sgi_pending
[irq
][cpu
] == 0) {
379 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
381 ret
= irq
| ((src
& 0x7) << 10);
383 /* Clear pending state for both level and edge triggered
384 * interrupts. (level triggered interrupts with an active line
385 * remain pending, see gic_test_pending)
387 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
392 gic_activate_irq(s
, cpu
, irq
);
394 DPRINTF("ACK %d\n", irq
);
398 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
401 if (s
->security_extn
&& !attrs
.secure
) {
402 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
403 return; /* Ignore Non-secure access of Group0 IRQ */
405 val
= 0x80 | (val
>> 1); /* Non-secure view */
408 if (irq
< GIC_INTERNAL
) {
409 s
->priority1
[irq
][cpu
] = val
;
411 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
415 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
418 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
420 if (s
->security_extn
&& !attrs
.secure
) {
421 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
422 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
424 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
429 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
432 if (s
->security_extn
&& !attrs
.secure
) {
433 if (s
->priority_mask
[cpu
] & 0x80) {
434 /* Priority Mask in upper half */
435 pmask
= 0x80 | (pmask
>> 1);
437 /* Non-secure write ignored if priority mask is in lower half */
441 s
->priority_mask
[cpu
] = pmask
;
444 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
446 uint32_t pmask
= s
->priority_mask
[cpu
];
448 if (s
->security_extn
&& !attrs
.secure
) {
450 /* Priority Mask in upper half, return Non-secure view */
451 pmask
= (pmask
<< 1) & 0xff;
453 /* Priority Mask in lower half, RAZ */
460 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
462 uint32_t ret
= s
->cpu_ctlr
[cpu
];
464 if (s
->security_extn
&& !attrs
.secure
) {
465 /* Construct the NS banked view of GICC_CTLR from the correct
466 * bits of the S banked view. We don't need to move the bypass
467 * control bits because we don't implement that (IMPDEF) part
468 * of the GIC architecture.
470 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
475 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
480 if (s
->security_extn
&& !attrs
.secure
) {
481 /* The NS view can only write certain bits in the register;
482 * the rest are unchanged
484 mask
= GICC_CTLR_EN_GRP1
;
485 if (s
->revision
== 2) {
486 mask
|= GICC_CTLR_EOIMODE_NS
;
488 s
->cpu_ctlr
[cpu
] &= ~mask
;
489 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
491 if (s
->revision
== 2) {
492 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
494 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
496 s
->cpu_ctlr
[cpu
] = value
& mask
;
498 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
499 "Group1 Interrupts %sabled\n", cpu
,
500 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
501 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
504 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
506 if (s
->security_extn
&& !attrs
.secure
) {
507 if (s
->running_priority
[cpu
] & 0x80) {
508 /* Running priority in upper half of range: return the Non-secure
509 * view of the priority.
511 return s
->running_priority
[cpu
] << 1;
513 /* Running priority in lower half of range: RAZ */
517 return s
->running_priority
[cpu
];
521 /* Return true if we should split priority drop and interrupt deactivation,
522 * ie whether the relevant EOIMode bit is set.
524 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
526 if (s
->revision
!= 2) {
527 /* Before GICv2 prio-drop and deactivate are not separable */
530 if (s
->security_extn
&& !attrs
.secure
) {
531 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
533 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
536 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
539 int group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
541 if (!gic_eoi_split(s
, cpu
, attrs
)) {
542 /* This is UNPREDICTABLE; we choose to ignore it */
543 qemu_log_mask(LOG_GUEST_ERROR
,
544 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
548 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
549 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
553 GIC_CLEAR_ACTIVE(irq
, cm
);
556 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
561 DPRINTF("EOI %d\n", irq
);
562 if (irq
>= s
->num_irq
) {
563 /* This handles two cases:
564 * 1. If software writes the ID of a spurious interrupt [ie 1023]
565 * to the GICC_EOIR, the GIC ignores that write.
566 * 2. If software writes the number of a non-existent interrupt
567 * this must be a subcase of "value written does not match the last
568 * valid interrupt value read from the Interrupt Acknowledge
569 * register" and so this is UNPREDICTABLE. We choose to ignore it.
573 if (s
->running_priority
[cpu
] == 0x100) {
574 return; /* No active IRQ. */
577 if (s
->revision
== REV_11MPCORE
) {
578 /* Mark level triggered interrupts as pending if they are still
580 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
581 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
582 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
583 GIC_SET_PENDING(irq
, cm
);
587 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
589 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
590 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
594 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
595 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
596 * i.e. go ahead and complete the irq anyway.
599 gic_drop_prio(s
, cpu
, group
);
601 /* In GICv2 the guest can choose to split priority-drop and deactivate */
602 if (!gic_eoi_split(s
, cpu
, attrs
)) {
603 GIC_CLEAR_ACTIVE(irq
, cm
);
608 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
610 GICState
*s
= (GICState
*)opaque
;
618 cpu
= gic_get_current_cpu(s
);
620 if (offset
< 0x100) {
621 if (offset
== 0) { /* GICD_CTLR */
622 if (s
->security_extn
&& !attrs
.secure
) {
623 /* The NS bank of this register is just an alias of the
624 * EnableGrp1 bit in the S bank version.
626 return extract32(s
->ctlr
, 1, 1);
632 /* Interrupt Controller Type Register */
633 return ((s
->num_irq
/ 32) - 1)
634 | ((s
->num_cpu
- 1) << 5)
635 | (s
->security_extn
<< 10);
638 if (offset
>= 0x80) {
639 /* Interrupt Group Registers: these RAZ/WI if this is an NS
640 * access to a GIC with the security extensions, or if the GIC
641 * doesn't have groups at all.
644 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
645 /* Every byte offset holds 8 group status bits */
646 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
647 if (irq
>= s
->num_irq
) {
650 for (i
= 0; i
< 8; i
++) {
651 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
659 } else if (offset
< 0x200) {
660 /* Interrupt Set/Clear Enable. */
662 irq
= (offset
- 0x100) * 8;
664 irq
= (offset
- 0x180) * 8;
666 if (irq
>= s
->num_irq
)
669 for (i
= 0; i
< 8; i
++) {
670 if (s
->security_extn
&& !attrs
.secure
&&
671 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
672 continue; /* Ignore Non-secure access of Group0 IRQ */
675 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
679 } else if (offset
< 0x300) {
680 /* Interrupt Set/Clear Pending. */
682 irq
= (offset
- 0x200) * 8;
684 irq
= (offset
- 0x280) * 8;
686 if (irq
>= s
->num_irq
)
689 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
690 for (i
= 0; i
< 8; i
++) {
691 if (s
->security_extn
&& !attrs
.secure
&&
692 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
693 continue; /* Ignore Non-secure access of Group0 IRQ */
696 if (gic_test_pending(s
, irq
+ i
, mask
)) {
700 } else if (offset
< 0x400) {
701 /* Interrupt Active. */
702 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
703 if (irq
>= s
->num_irq
)
706 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
707 for (i
= 0; i
< 8; i
++) {
708 if (s
->security_extn
&& !attrs
.secure
&&
709 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
710 continue; /* Ignore Non-secure access of Group0 IRQ */
713 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
717 } else if (offset
< 0x800) {
718 /* Interrupt Priority. */
719 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
720 if (irq
>= s
->num_irq
)
722 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
723 } else if (offset
< 0xc00) {
724 /* Interrupt CPU Target. */
725 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
726 /* For uniprocessor GICs these RAZ/WI */
729 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
730 if (irq
>= s
->num_irq
) {
733 if (irq
>= 29 && irq
<= 31) {
736 res
= GIC_TARGET(irq
);
739 } else if (offset
< 0xf00) {
740 /* Interrupt Configuration. */
741 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
742 if (irq
>= s
->num_irq
)
745 for (i
= 0; i
< 4; i
++) {
746 if (s
->security_extn
&& !attrs
.secure
&&
747 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
748 continue; /* Ignore Non-secure access of Group0 IRQ */
751 if (GIC_TEST_MODEL(irq
+ i
))
752 res
|= (1 << (i
* 2));
753 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
754 res
|= (2 << (i
* 2));
756 } else if (offset
< 0xf10) {
758 } else if (offset
< 0xf30) {
759 if (s
->revision
== REV_11MPCORE
) {
763 if (offset
< 0xf20) {
764 /* GICD_CPENDSGIRn */
765 irq
= (offset
- 0xf10);
767 irq
= (offset
- 0xf20);
768 /* GICD_SPENDSGIRn */
771 if (s
->security_extn
&& !attrs
.secure
&&
772 !GIC_TEST_GROUP(irq
, 1 << cpu
)) {
773 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
775 res
= s
->sgi_pending
[irq
][cpu
];
777 } else if (offset
< 0xfd0) {
779 } else if (offset
< 0x1000) {
783 switch (s
->revision
) {
785 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
788 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
791 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
798 g_assert_not_reached();
802 qemu_log_mask(LOG_GUEST_ERROR
,
803 "gic_dist_readb: Bad offset %x\n", (int)offset
);
807 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
808 unsigned size
, MemTxAttrs attrs
)
812 *data
= gic_dist_readb(opaque
, offset
, attrs
);
815 *data
= gic_dist_readb(opaque
, offset
, attrs
);
816 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
819 *data
= gic_dist_readb(opaque
, offset
, attrs
);
820 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
821 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
822 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
829 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
830 uint32_t value
, MemTxAttrs attrs
)
832 GICState
*s
= (GICState
*)opaque
;
837 cpu
= gic_get_current_cpu(s
);
838 if (offset
< 0x100) {
840 if (s
->security_extn
&& !attrs
.secure
) {
841 /* NS version is just an alias of the S version's bit 1 */
842 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
843 } else if (gic_has_groups(s
)) {
844 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
846 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
848 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
849 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
850 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
851 } else if (offset
< 4) {
853 } else if (offset
>= 0x80) {
854 /* Interrupt Group Registers: RAZ/WI for NS access to secure
855 * GIC, or for GICs without groups.
857 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
858 /* Every byte offset holds 8 group status bits */
859 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
860 if (irq
>= s
->num_irq
) {
863 for (i
= 0; i
< 8; i
++) {
864 /* Group bits are banked for private interrupts */
865 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
866 if (value
& (1 << i
)) {
867 /* Group1 (Non-secure) */
868 GIC_SET_GROUP(irq
+ i
, cm
);
870 /* Group0 (Secure) */
871 GIC_CLEAR_GROUP(irq
+ i
, cm
);
878 } else if (offset
< 0x180) {
879 /* Interrupt Set Enable. */
880 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
881 if (irq
>= s
->num_irq
)
883 if (irq
< GIC_NR_SGIS
) {
887 for (i
= 0; i
< 8; i
++) {
888 if (value
& (1 << i
)) {
890 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
891 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
893 if (s
->security_extn
&& !attrs
.secure
&&
894 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
895 continue; /* Ignore Non-secure access of Group0 IRQ */
898 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
899 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
900 trace_gic_enable_irq(irq
+ i
);
902 GIC_SET_ENABLED(irq
+ i
, cm
);
903 /* If a raised level triggered IRQ enabled then mark
905 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
906 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
907 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
908 GIC_SET_PENDING(irq
+ i
, mask
);
912 } else if (offset
< 0x200) {
913 /* Interrupt Clear Enable. */
914 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
915 if (irq
>= s
->num_irq
)
917 if (irq
< GIC_NR_SGIS
) {
921 for (i
= 0; i
< 8; i
++) {
922 if (value
& (1 << i
)) {
923 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
925 if (s
->security_extn
&& !attrs
.secure
&&
926 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
927 continue; /* Ignore Non-secure access of Group0 IRQ */
930 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
931 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
932 trace_gic_disable_irq(irq
+ i
);
934 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
937 } else if (offset
< 0x280) {
938 /* Interrupt Set Pending. */
939 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
940 if (irq
>= s
->num_irq
)
942 if (irq
< GIC_NR_SGIS
) {
946 for (i
= 0; i
< 8; i
++) {
947 if (value
& (1 << i
)) {
948 if (s
->security_extn
&& !attrs
.secure
&&
949 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
950 continue; /* Ignore Non-secure access of Group0 IRQ */
953 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
956 } else if (offset
< 0x300) {
957 /* Interrupt Clear Pending. */
958 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
959 if (irq
>= s
->num_irq
)
961 if (irq
< GIC_NR_SGIS
) {
965 for (i
= 0; i
< 8; i
++) {
966 if (s
->security_extn
&& !attrs
.secure
&&
967 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
968 continue; /* Ignore Non-secure access of Group0 IRQ */
971 /* ??? This currently clears the pending bit for all CPUs, even
972 for per-CPU interrupts. It's unclear whether this is the
974 if (value
& (1 << i
)) {
975 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
978 } else if (offset
< 0x400) {
979 /* Interrupt Active. */
981 } else if (offset
< 0x800) {
982 /* Interrupt Priority. */
983 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
984 if (irq
>= s
->num_irq
)
986 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
987 } else if (offset
< 0xc00) {
988 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
989 * annoying exception of the 11MPCore's GIC.
991 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
992 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
993 if (irq
>= s
->num_irq
) {
998 } else if (irq
< GIC_INTERNAL
) {
999 value
= ALL_CPU_MASK
;
1001 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1003 } else if (offset
< 0xf00) {
1004 /* Interrupt Configuration. */
1005 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1006 if (irq
>= s
->num_irq
)
1008 if (irq
< GIC_NR_SGIS
)
1010 for (i
= 0; i
< 4; i
++) {
1011 if (s
->security_extn
&& !attrs
.secure
&&
1012 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1013 continue; /* Ignore Non-secure access of Group0 IRQ */
1016 if (s
->revision
== REV_11MPCORE
) {
1017 if (value
& (1 << (i
* 2))) {
1018 GIC_SET_MODEL(irq
+ i
);
1020 GIC_CLEAR_MODEL(irq
+ i
);
1023 if (value
& (2 << (i
* 2))) {
1024 GIC_SET_EDGE_TRIGGER(irq
+ i
);
1026 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
1029 } else if (offset
< 0xf10) {
1030 /* 0xf00 is only handled for 32-bit writes. */
1032 } else if (offset
< 0xf20) {
1033 /* GICD_CPENDSGIRn */
1034 if (s
->revision
== REV_11MPCORE
) {
1037 irq
= (offset
- 0xf10);
1039 if (!s
->security_extn
|| attrs
.secure
||
1040 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1041 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1042 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1043 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
1046 } else if (offset
< 0xf30) {
1047 /* GICD_SPENDSGIRn */
1048 if (s
->revision
== REV_11MPCORE
) {
1051 irq
= (offset
- 0xf20);
1053 if (!s
->security_extn
|| attrs
.secure
||
1054 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1055 GIC_SET_PENDING(irq
, 1 << cpu
);
1056 s
->sgi_pending
[irq
][cpu
] |= value
;
1064 qemu_log_mask(LOG_GUEST_ERROR
,
1065 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1068 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1069 uint32_t value
, MemTxAttrs attrs
)
1071 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1072 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1075 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1076 uint32_t value
, MemTxAttrs attrs
)
1078 GICState
*s
= (GICState
*)opaque
;
1079 if (offset
== 0xf00) {
1085 cpu
= gic_get_current_cpu(s
);
1086 irq
= value
& 0x3ff;
1087 switch ((value
>> 24) & 3) {
1089 mask
= (value
>> 16) & ALL_CPU_MASK
;
1092 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1098 DPRINTF("Bad Soft Int target filter\n");
1099 mask
= ALL_CPU_MASK
;
1102 GIC_SET_PENDING(irq
, mask
);
1103 target_cpu
= ctz32(mask
);
1104 while (target_cpu
< GIC_NCPU
) {
1105 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1106 mask
&= ~(1 << target_cpu
);
1107 target_cpu
= ctz32(mask
);
1112 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1113 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1116 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1117 unsigned size
, MemTxAttrs attrs
)
1121 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1124 gic_dist_writew(opaque
, offset
, data
, attrs
);
1127 gic_dist_writel(opaque
, offset
, data
, attrs
);
1134 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1136 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1137 * second half of GICC_NSAPR.
1139 switch (GIC_MIN_BPR
) {
1142 return s
->nsapr
[regno
+ 2][cpu
];
1147 return s
->nsapr
[regno
+ 1][cpu
];
1152 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1157 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1161 g_assert_not_reached();
1166 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1169 /* Write the Nonsecure view of GICC_APR<regno>. */
1170 switch (GIC_MIN_BPR
) {
1173 s
->nsapr
[regno
+ 2][cpu
] = value
;
1178 s
->nsapr
[regno
+ 1][cpu
] = value
;
1183 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1188 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1192 g_assert_not_reached();
1196 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1197 uint64_t *data
, MemTxAttrs attrs
)
1200 case 0x00: /* Control */
1201 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1203 case 0x04: /* Priority mask */
1204 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1206 case 0x08: /* Binary Point */
1207 if (s
->security_extn
&& !attrs
.secure
) {
1208 /* BPR is banked. Non-secure copy stored in ABPR. */
1209 *data
= s
->abpr
[cpu
];
1211 *data
= s
->bpr
[cpu
];
1214 case 0x0c: /* Acknowledge */
1215 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1217 case 0x14: /* Running Priority */
1218 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1220 case 0x18: /* Highest Pending Interrupt */
1221 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1223 case 0x1c: /* Aliased Binary Point */
1224 /* GIC v2, no security: ABPR
1225 * GIC v1, no security: not implemented (RAZ/WI)
1226 * With security extensions, secure access: ABPR (alias of NS BPR)
1227 * With security extensions, nonsecure access: RAZ/WI
1229 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1232 *data
= s
->abpr
[cpu
];
1235 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1237 int regno
= (offset
- 0xd0) / 4;
1239 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1241 } else if (s
->security_extn
&& !attrs
.secure
) {
1242 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1243 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1245 *data
= s
->apr
[regno
][cpu
];
1249 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1251 int regno
= (offset
- 0xe0) / 4;
1253 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1254 (s
->security_extn
&& !attrs
.secure
)) {
1257 *data
= s
->nsapr
[regno
][cpu
];
1262 qemu_log_mask(LOG_GUEST_ERROR
,
1263 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1269 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1270 uint32_t value
, MemTxAttrs attrs
)
1273 case 0x00: /* Control */
1274 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1276 case 0x04: /* Priority mask */
1277 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1279 case 0x08: /* Binary Point */
1280 if (s
->security_extn
&& !attrs
.secure
) {
1281 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1283 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1286 case 0x10: /* End Of Interrupt */
1287 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1289 case 0x1c: /* Aliased Binary Point */
1290 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1291 /* unimplemented, or NS access: RAZ/WI */
1294 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1297 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1299 int regno
= (offset
- 0xd0) / 4;
1301 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1304 if (s
->security_extn
&& !attrs
.secure
) {
1305 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1306 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1308 s
->apr
[regno
][cpu
] = value
;
1312 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1314 int regno
= (offset
- 0xe0) / 4;
1316 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1319 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1322 s
->nsapr
[regno
][cpu
] = value
;
1327 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1330 qemu_log_mask(LOG_GUEST_ERROR
,
1331 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1338 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1339 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1340 unsigned size
, MemTxAttrs attrs
)
1342 GICState
*s
= (GICState
*)opaque
;
1343 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1346 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1347 uint64_t value
, unsigned size
,
1350 GICState
*s
= (GICState
*)opaque
;
1351 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1354 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1355 * These just decode the opaque pointer into GICState* + cpu id.
1357 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1358 unsigned size
, MemTxAttrs attrs
)
1360 GICState
**backref
= (GICState
**)opaque
;
1361 GICState
*s
= *backref
;
1362 int id
= (backref
- s
->backref
);
1363 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1366 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1367 uint64_t value
, unsigned size
,
1370 GICState
**backref
= (GICState
**)opaque
;
1371 GICState
*s
= *backref
;
1372 int id
= (backref
- s
->backref
);
1373 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1376 static const MemoryRegionOps gic_ops
[2] = {
1378 .read_with_attrs
= gic_dist_read
,
1379 .write_with_attrs
= gic_dist_write
,
1380 .endianness
= DEVICE_NATIVE_ENDIAN
,
1383 .read_with_attrs
= gic_thiscpu_read
,
1384 .write_with_attrs
= gic_thiscpu_write
,
1385 .endianness
= DEVICE_NATIVE_ENDIAN
,
1389 static const MemoryRegionOps gic_cpu_ops
= {
1390 .read_with_attrs
= gic_do_cpu_read
,
1391 .write_with_attrs
= gic_do_cpu_write
,
1392 .endianness
= DEVICE_NATIVE_ENDIAN
,
1395 /* This function is used by nvic model */
1396 void gic_init_irqs_and_distributor(GICState
*s
)
1398 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1401 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1403 /* Device instance realize function for the GIC sysbus device */
1405 GICState
*s
= ARM_GIC(dev
);
1406 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1407 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1408 Error
*local_err
= NULL
;
1410 agc
->parent_realize(dev
, &local_err
);
1412 error_propagate(errp
, local_err
);
1416 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
1417 error_setg(errp
, "KVM with user space irqchip only works when the "
1418 "host kernel supports KVM_CAP_ARM_USER_IRQ");
1422 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1423 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1425 /* Extra core-specific regions for the CPU interfaces. This is
1426 * necessary for "franken-GIC" implementations, for example on
1428 * NB that the memory region size of 0x100 applies for the 11MPCore
1429 * and also cores following the GIC v1 spec (ie A9).
1430 * GIC v2 defines a larger memory region (0x1000) so this will need
1431 * to be extended when we implement A15.
1433 for (i
= 0; i
< s
->num_cpu
; i
++) {
1435 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1436 &s
->backref
[i
], "gic_cpu", 0x100);
1437 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1441 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1443 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1444 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1446 agc
->parent_realize
= dc
->realize
;
1447 dc
->realize
= arm_gic_realize
;
1450 static const TypeInfo arm_gic_info
= {
1451 .name
= TYPE_ARM_GIC
,
1452 .parent
= TYPE_ARM_GIC_COMMON
,
1453 .instance_size
= sizeof(GICState
),
1454 .class_init
= arm_gic_class_init
,
1455 .class_size
= sizeof(ARMGICClass
),
1458 static void arm_gic_register_types(void)
1460 type_register_static(&arm_gic_info
);
1463 type_init(arm_gic_register_types
)