hw/intc/arm_gic_kvm.c

   1 /*
   2  * ARM Generic Interrupt Controller using KVM in-kernel support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  * Save/Restore logic added by Christoffer Dall.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/module.h"
  25 #include "cpu.h"
  26 #include "migration/blocker.h"
  27 #include "sysemu/kvm.h"
  28 #include "kvm_arm.h"
  29 #include "gic_internal.h"
  30 #include "vgic_common.h"
  31 #include "qom/object.h"
  32
  33 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
  34 typedef struct KVMARMGICClass KVMARMGICClass;
  35 /* This is reusing the GICState typedef from ARM_GIC_COMMON */
  36 DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
  37                      KVM_ARM_GIC, TYPE_KVM_ARM_GIC)
  38
  39 struct KVMARMGICClass {
  40     ARMGICCommonClass parent_class;
  41     DeviceRealize parent_realize;
  42     void (*parent_reset)(DeviceState *dev);
  43 };
  44
  45 void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
  46 {
  47     /* Meaning of the 'irq' parameter:
  48      *  [0..N-1] : external interrupts
  49      *  [N..N+31] : PPI (internal) interrupts for CPU 0
  50      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
  51      *  ...
  52      * Convert this to the kernel's desired encoding, which
  53      * has separate fields in the irq number for type,
  54      * CPU number and interrupt number.
  55      */
  56     int irqtype, cpu;
  57
  58     if (irq < (num_irq - GIC_INTERNAL)) {
  59         /* External interrupt. The kernel numbers these like the GIC
  60          * hardware, with external interrupt IDs starting after the
  61          * internal ones.
  62          */
  63         irqtype = KVM_ARM_IRQ_TYPE_SPI;
  64         cpu = 0;
  65         irq += GIC_INTERNAL;
  66     } else {
  67         /* Internal interrupt: decode into (cpu, interrupt id) */
  68         irqtype = KVM_ARM_IRQ_TYPE_PPI;
  69         irq -= (num_irq - GIC_INTERNAL);
  70         cpu = irq / GIC_INTERNAL;
  71         irq %= GIC_INTERNAL;
  72     }
  73     kvm_arm_set_irq(cpu, irqtype, irq, !!level);
  74 }
  75
  76 static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
  77 {
  78     GICState *s = (GICState *)opaque;
  79
  80     kvm_arm_gic_set_irq(s->num_irq, irq, level);
  81 }
  82
  83 static bool kvm_arm_gic_can_save_restore(GICState *s)
  84 {
  85     return s->dev_fd >= 0;
  86 }
  87
  88 #define KVM_VGIC_ATTR(offset, cpu) \
  89     ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
  90       KVM_DEV_ARM_VGIC_CPUID_MASK) | \
  91      (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
  92       KVM_DEV_ARM_VGIC_OFFSET_MASK))
  93
  94 static void kvm_gicd_access(GICState *s, int offset, int cpu,
  95                             uint32_t *val, bool write)
  96 {
  97     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
  98                       KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
  99 }
 100
 101 static void kvm_gicc_access(GICState *s, int offset, int cpu,
 102                             uint32_t *val, bool write)
 103 {
 104     kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
 105                       KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
 106 }
 107
 108 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
 109     for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
 110
 111 /*
 112  * Translate from the in-kernel field for an IRQ value to/from the qemu
 113  * representation.
 114  */
 115 typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
 116                                   uint32_t *field, bool to_kernel);
 117
 118 /* synthetic translate function used for clear/set registers to completely
 119  * clear a setting using a clear-register before setting the remaining bits
 120  * using a set-register */
 121 static void translate_clear(GICState *s, int irq, int cpu,
 122                             uint32_t *field, bool to_kernel)
 123 {
 124     if (to_kernel) {
 125         *field = ~0;
 126     } else {
 127         /* does not make sense: qemu model doesn't use set/clear regs */
 128         abort();
 129     }
 130 }
 131
 132 static void translate_group(GICState *s, int irq, int cpu,
 133                             uint32_t *field, bool to_kernel)
 134 {
 135     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 136
 137     if (to_kernel) {
 138         *field = GIC_DIST_TEST_GROUP(irq, cm);
 139     } else {
 140         if (*field & 1) {
 141             GIC_DIST_SET_GROUP(irq, cm);
 142         }
 143     }
 144 }
 145
 146 static void translate_enabled(GICState *s, int irq, int cpu,
 147                               uint32_t *field, bool to_kernel)
 148 {
 149     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 150
 151     if (to_kernel) {
 152         *field = GIC_DIST_TEST_ENABLED(irq, cm);
 153     } else {
 154         if (*field & 1) {
 155             GIC_DIST_SET_ENABLED(irq, cm);
 156         }
 157     }
 158 }
 159
 160 static void translate_pending(GICState *s, int irq, int cpu,
 161                               uint32_t *field, bool to_kernel)
 162 {
 163     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 164
 165     if (to_kernel) {
 166         *field = gic_test_pending(s, irq, cm);
 167     } else {
 168         if (*field & 1) {
 169             GIC_DIST_SET_PENDING(irq, cm);
 170             /* TODO: Capture is level-line is held high in the kernel */
 171         }
 172     }
 173 }
 174
 175 static void translate_active(GICState *s, int irq, int cpu,
 176                              uint32_t *field, bool to_kernel)
 177 {
 178     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 179
 180     if (to_kernel) {
 181         *field = GIC_DIST_TEST_ACTIVE(irq, cm);
 182     } else {
 183         if (*field & 1) {
 184             GIC_DIST_SET_ACTIVE(irq, cm);
 185         }
 186     }
 187 }
 188
 189 static void translate_trigger(GICState *s, int irq, int cpu,
 190                               uint32_t *field, bool to_kernel)
 191 {
 192     if (to_kernel) {
 193         *field = (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
 194     } else {
 195         if (*field & 0x2) {
 196             GIC_DIST_SET_EDGE_TRIGGER(irq);
 197         }
 198     }
 199 }
 200
 201 static void translate_priority(GICState *s, int irq, int cpu,
 202                                uint32_t *field, bool to_kernel)
 203 {
 204     if (to_kernel) {
 205         *field = GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff;
 206     } else {
 207         gic_dist_set_priority(s, cpu, irq,
 208                               *field & 0xff, MEMTXATTRS_UNSPECIFIED);
 209     }
 210 }
 211
 212 static void translate_targets(GICState *s, int irq, int cpu,
 213                               uint32_t *field, bool to_kernel)
 214 {
 215     if (to_kernel) {
 216         *field = s->irq_target[irq] & 0xff;
 217     } else {
 218         s->irq_target[irq] = *field & 0xff;
 219     }
 220 }
 221
 222 static void translate_sgisource(GICState *s, int irq, int cpu,
 223                                 uint32_t *field, bool to_kernel)
 224 {
 225     if (to_kernel) {
 226         *field = s->sgi_pending[irq][cpu] & 0xff;
 227     } else {
 228         s->sgi_pending[irq][cpu] = *field & 0xff;
 229     }
 230 }
 231
 232 /* Read a register group from the kernel VGIC */
 233 static void kvm_dist_get(GICState *s, uint32_t offset, int width,
 234                          int maxirq, vgic_translate_fn translate_fn)
 235 {
 236     uint32_t reg;
 237     int i;
 238     int j;
 239     int irq;
 240     int cpu;
 241     int regsz = 32 / width; /* irqs per kernel register */
 242     uint32_t field;
 243
 244     for_each_irq_reg(i, maxirq, width) {
 245         irq = i * regsz;
 246         cpu = 0;
 247         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 248             kvm_gicd_access(s, offset, cpu, &reg, false);
 249             for (j = 0; j < regsz; j++) {
 250                 field = extract32(reg, j * width, width);
 251                 translate_fn(s, irq + j, cpu, &field, false);
 252             }
 253
 254             cpu++;
 255         }
 256         offset += 4;
 257     }
 258 }
 259
 260 /* Write a register group to the kernel VGIC */
 261 static void kvm_dist_put(GICState *s, uint32_t offset, int width,
 262                          int maxirq, vgic_translate_fn translate_fn)
 263 {
 264     uint32_t reg;
 265     int i;
 266     int j;
 267     int irq;
 268     int cpu;
 269     int regsz = 32 / width; /* irqs per kernel register */
 270     uint32_t field;
 271
 272     for_each_irq_reg(i, maxirq, width) {
 273         irq = i * regsz;
 274         cpu = 0;
 275         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 276             reg = 0;
 277             for (j = 0; j < regsz; j++) {
 278                 translate_fn(s, irq + j, cpu, &field, true);
 279                 reg = deposit32(reg, j * width, width, field);
 280             }
 281             kvm_gicd_access(s, offset, cpu, &reg, true);
 282
 283             cpu++;
 284         }
 285         offset += 4;
 286     }
 287 }
 288
 289 static void kvm_arm_gic_put(GICState *s)
 290 {
 291     uint32_t reg;
 292     int i;
 293     int cpu;
 294     int num_cpu;
 295     int num_irq;
 296
 297     /* Note: We do the restore in a slightly different order than the save
 298      * (where the order doesn't matter and is simply ordered according to the
 299      * register offset values */
 300
 301     /*****************************************************************
 302      * Distributor State
 303      */
 304
 305     /* s->ctlr -> GICD_CTLR */
 306     reg = s->ctlr;
 307     kvm_gicd_access(s, 0x0, 0, &reg, true);
 308
 309     /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
 310     kvm_gicd_access(s, 0x4, 0, &reg, false);
 311     num_irq = ((reg & 0x1f) + 1) * 32;
 312     num_cpu = ((reg & 0xe0) >> 5) + 1;
 313
 314     if (num_irq < s->num_irq) {
 315             fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
 316                     s->num_irq, num_irq);
 317             abort();
 318     } else if (num_cpu != s->num_cpu) {
 319             fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
 320                     s->num_cpu, num_cpu);
 321             /* Did we not create the VCPUs in the kernel yet? */
 322             abort();
 323     }
 324
 325     /* TODO: Consider checking compatibility with the IIDR ? */
 326
 327     /* irq_state[n].enabled -> GICD_ISENABLERn */
 328     kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
 329     kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
 330
 331     /* irq_state[n].group -> GICD_IGROUPRn */
 332     kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
 333
 334     /* s->irq_target[irq] -> GICD_ITARGETSRn
 335      * (restore targets before pending to ensure the pending state is set on
 336      * the appropriate CPU interfaces in the kernel) */
 337     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 338
 339     /* irq_state[n].trigger -> GICD_ICFGRn
 340      * (restore configuration registers before pending IRQs so we treat
 341      * level/edge correctly) */
 342     kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 343
 344     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
 345     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
 346     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
 347
 348     /* irq_state[n].active -> GICD_ISACTIVERn */
 349     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
 350     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 351
 352
 353     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
 354     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
 355
 356     /* s->sgi_pending -> ICD_CPENDSGIRn */
 357     kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
 358     kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
 359
 360
 361     /*****************************************************************
 362      * CPU Interface(s) State
 363      */
 364
 365     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 366         /* s->cpu_ctlr[cpu] -> GICC_CTLR */
 367         reg = s->cpu_ctlr[cpu];
 368         kvm_gicc_access(s, 0x00, cpu, &reg, true);
 369
 370         /* s->priority_mask[cpu] -> GICC_PMR */
 371         reg = (s->priority_mask[cpu] & 0xff);
 372         kvm_gicc_access(s, 0x04, cpu, &reg, true);
 373
 374         /* s->bpr[cpu] -> GICC_BPR */
 375         reg = (s->bpr[cpu] & 0x7);
 376         kvm_gicc_access(s, 0x08, cpu, &reg, true);
 377
 378         /* s->abpr[cpu] -> GICC_ABPR */
 379         reg = (s->abpr[cpu] & 0x7);
 380         kvm_gicc_access(s, 0x1c, cpu, &reg, true);
 381
 382         /* s->apr[n][cpu] -> GICC_APRn */
 383         for (i = 0; i < 4; i++) {
 384             reg = s->apr[i][cpu];
 385             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
 386         }
 387     }
 388 }
 389
 390 static void kvm_arm_gic_get(GICState *s)
 391 {
 392     uint32_t reg;
 393     int i;
 394     int cpu;
 395
 396     /*****************************************************************
 397      * Distributor State
 398      */
 399
 400     /* GICD_CTLR -> s->ctlr */
 401     kvm_gicd_access(s, 0x0, 0, &reg, false);
 402     s->ctlr = reg;
 403
 404     /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
 405     kvm_gicd_access(s, 0x4, 0, &reg, false);
 406     s->num_irq = ((reg & 0x1f) + 1) * 32;
 407     s->num_cpu = ((reg & 0xe0) >> 5) + 1;
 408
 409     if (s->num_irq > GIC_MAXIRQ) {
 410             fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
 411                     s->num_irq);
 412             abort();
 413     }
 414
 415     /* GICD_IIDR -> ? */
 416     kvm_gicd_access(s, 0x8, 0, &reg, false);
 417
 418     /* Clear all the IRQ settings */
 419     for (i = 0; i < s->num_irq; i++) {
 420         memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
 421     }
 422
 423     /* GICD_IGROUPRn -> irq_state[n].group */
 424     kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
 425
 426     /* GICD_ISENABLERn -> irq_state[n].enabled */
 427     kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
 428
 429     /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
 430     kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
 431
 432     /* GICD_ISACTIVERn -> irq_state[n].active */
 433     kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
 434
 435     /* GICD_ICFRn -> irq_state[n].trigger */
 436     kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
 437
 438     /* GICD_IPRIORITYRn -> s->priorityX[irq] */
 439     kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
 440
 441     /* GICD_ITARGETSRn -> s->irq_target[irq] */
 442     kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
 443
 444     /* GICD_CPENDSGIRn -> s->sgi_pending */
 445     kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
 446
 447
 448     /*****************************************************************
 449      * CPU Interface(s) State
 450      */
 451
 452     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 453         /* GICC_CTLR -> s->cpu_ctlr[cpu] */
 454         kvm_gicc_access(s, 0x00, cpu, &reg, false);
 455         s->cpu_ctlr[cpu] = reg;
 456
 457         /* GICC_PMR -> s->priority_mask[cpu] */
 458         kvm_gicc_access(s, 0x04, cpu, &reg, false);
 459         s->priority_mask[cpu] = (reg & 0xff);
 460
 461         /* GICC_BPR -> s->bpr[cpu] */
 462         kvm_gicc_access(s, 0x08, cpu, &reg, false);
 463         s->bpr[cpu] = (reg & 0x7);
 464
 465         /* GICC_ABPR -> s->abpr[cpu] */
 466         kvm_gicc_access(s, 0x1c, cpu, &reg, false);
 467         s->abpr[cpu] = (reg & 0x7);
 468
 469         /* GICC_APRn -> s->apr[n][cpu] */
 470         for (i = 0; i < 4; i++) {
 471             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
 472             s->apr[i][cpu] = reg;
 473         }
 474     }
 475 }
 476
 477 static void kvm_arm_gic_reset(DeviceState *dev)
 478 {
 479     GICState *s = ARM_GIC_COMMON(dev);
 480     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 481
 482     kgc->parent_reset(dev);
 483
 484     if (kvm_arm_gic_can_save_restore(s)) {
 485         kvm_arm_gic_put(s);
 486     }
 487 }
 488
 489 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 490 {
 491     int i;
 492     GICState *s = KVM_ARM_GIC(dev);
 493     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 494     Error *local_err = NULL;
 495     int ret;
 496
 497     kgc->parent_realize(dev, &local_err);
 498     if (local_err) {
 499         error_propagate(errp, local_err);
 500         return;
 501     }
 502
 503     if (s->security_extn) {
 504         error_setg(errp, "the in-kernel VGIC does not implement the "
 505                    "security extensions");
 506         return;
 507     }
 508
 509     if (s->virt_extn) {
 510         error_setg(errp, "the in-kernel VGIC does not implement the "
 511                    "virtualization extensions");
 512         return;
 513     }
 514
 515     if (!kvm_arm_gic_can_save_restore(s)) {
 516         error_setg(&s->migration_blocker, "This operating system kernel does "
 517                                           "not support vGICv2 migration");
 518         if (migrate_add_blocker(s->migration_blocker, errp) < 0) {
 519             error_free(s->migration_blocker);
 520             return;
 521         }
 522     }
 523
 524     gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL);
 525
 526     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
 527         qemu_irq irq = qdev_get_gpio_in(dev, i);
 528         kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
 529     }
 530
 531     /* Try to create the device via the device control API */
 532     s->dev_fd = -1;
 533     ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
 534     if (ret >= 0) {
 535         s->dev_fd = ret;
 536
 537         /* Newstyle API is used, we may have attributes */
 538         if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
 539             uint32_t numirqs = s->num_irq;
 540             kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
 541                               &numirqs, true, &error_abort);
 542         }
 543         /* Tell the kernel to complete VGIC initialization now */
 544         if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
 545                                   KVM_DEV_ARM_VGIC_CTRL_INIT)) {
 546             kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
 547                               KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
 548                               &error_abort);
 549         }
 550     } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
 551         error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
 552         error_append_hint(errp,
 553                           "Perhaps the host CPU does not support GICv2?\n");
 554     } else if (ret != -ENODEV && ret != -ENOTSUP) {
 555         /*
 556          * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
 557          * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
 558          * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
 559          */
 560         error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
 561         return;
 562     }
 563
 564     /* Distributor */
 565     kvm_arm_register_device(&s->iomem,
 566                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 567                             | KVM_VGIC_V2_ADDR_TYPE_DIST,
 568                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 569                             KVM_VGIC_V2_ADDR_TYPE_DIST,
 570                             s->dev_fd, 0);
 571     /* CPU interface for current core. Unlike arm_gic, we don't
 572      * provide the "interface for core #N" memory regions, because
 573      * cores with a VGIC don't have those.
 574      */
 575     kvm_arm_register_device(&s->cpuiomem[0],
 576                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 577                             | KVM_VGIC_V2_ADDR_TYPE_CPU,
 578                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 579                             KVM_VGIC_V2_ADDR_TYPE_CPU,
 580                             s->dev_fd, 0);
 581
 582     if (kvm_has_gsi_routing()) {
 583         /* set up irq routing */
 584         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
 585             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
 586         }
 587
 588         kvm_gsi_routing_allowed = true;
 589
 590         kvm_irqchip_commit_routes(kvm_state);
 591     }
 592 }
 593
 594 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
 595 {
 596     DeviceClass *dc = DEVICE_CLASS(klass);
 597     ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
 598     KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
 599
 600     agcc->pre_save = kvm_arm_gic_get;
 601     agcc->post_load = kvm_arm_gic_put;
 602     device_class_set_parent_realize(dc, kvm_arm_gic_realize,
 603                                     &kgc->parent_realize);
 604     device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
 605 }
 606
 607 static const TypeInfo kvm_arm_gic_info = {
 608     .name = TYPE_KVM_ARM_GIC,
 609     .parent = TYPE_ARM_GIC_COMMON,
 610     .instance_size = sizeof(GICState),
 611     .class_init = kvm_arm_gic_class_init,
 612     .class_size = sizeof(KVMARMGICClass),
 613 };
 614
 615 static void kvm_arm_gic_register_types(void)
 616 {
 617     type_register_static(&kvm_arm_gic_info);
 618 }
 619
 620 type_init(kvm_arm_gic_register_types)