2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
6 * Save/Restore logic added by Christoffer Dall.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "migration/migration.h"
25 #include "sysemu/kvm.h"
27 #include "gic_internal.h"
28 #include "vgic_common.h"
30 //#define DEBUG_GIC_KVM
33 static const int debug_gic_kvm
= 1;
35 static const int debug_gic_kvm
= 0;
38 #define DPRINTF(fmt, ...) do { \
39 if (debug_gic_kvm) { \
40 printf("arm_gic: " fmt , ## __VA_ARGS__); \
44 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
45 #define KVM_ARM_GIC(obj) \
46 OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
47 #define KVM_ARM_GIC_CLASS(klass) \
48 OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
49 #define KVM_ARM_GIC_GET_CLASS(obj) \
50 OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
52 typedef struct KVMARMGICClass
{
53 ARMGICCommonClass parent_class
;
54 DeviceRealize parent_realize
;
55 void (*parent_reset
)(DeviceState
*dev
);
58 void kvm_arm_gic_set_irq(uint32_t num_irq
, int irq
, int level
)
60 /* Meaning of the 'irq' parameter:
61 * [0..N-1] : external interrupts
62 * [N..N+31] : PPI (internal) interrupts for CPU 0
63 * [N+32..N+63] : PPI (internal interrupts for CPU 1
65 * Convert this to the kernel's desired encoding, which
66 * has separate fields in the irq number for type,
67 * CPU number and interrupt number.
69 int kvm_irq
, irqtype
, cpu
;
71 if (irq
< (num_irq
- GIC_INTERNAL
)) {
72 /* External interrupt. The kernel numbers these like the GIC
73 * hardware, with external interrupt IDs starting after the
76 irqtype
= KVM_ARM_IRQ_TYPE_SPI
;
80 /* Internal interrupt: decode into (cpu, interrupt id) */
81 irqtype
= KVM_ARM_IRQ_TYPE_PPI
;
82 irq
-= (num_irq
- GIC_INTERNAL
);
83 cpu
= irq
/ GIC_INTERNAL
;
86 kvm_irq
= (irqtype
<< KVM_ARM_IRQ_TYPE_SHIFT
)
87 | (cpu
<< KVM_ARM_IRQ_VCPU_SHIFT
) | irq
;
89 kvm_set_irq(kvm_state
, kvm_irq
, !!level
);
92 static void kvm_arm_gicv2_set_irq(void *opaque
, int irq
, int level
)
94 GICState
*s
= (GICState
*)opaque
;
96 kvm_arm_gic_set_irq(s
->num_irq
, irq
, level
);
99 static bool kvm_arm_gic_can_save_restore(GICState
*s
)
101 return s
->dev_fd
>= 0;
104 #define KVM_VGIC_ATTR(offset, cpu) \
105 ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
106 KVM_DEV_ARM_VGIC_CPUID_MASK) | \
107 (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
108 KVM_DEV_ARM_VGIC_OFFSET_MASK))
110 static void kvm_gicd_access(GICState
*s
, int offset
, int cpu
,
111 uint32_t *val
, bool write
)
113 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
114 KVM_VGIC_ATTR(offset
, cpu
), val
, write
);
117 static void kvm_gicc_access(GICState
*s
, int offset
, int cpu
,
118 uint32_t *val
, bool write
)
120 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_REGS
,
121 KVM_VGIC_ATTR(offset
, cpu
), val
, write
);
124 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
125 for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
128 * Translate from the in-kernel field for an IRQ value to/from the qemu
131 typedef void (*vgic_translate_fn
)(GICState
*s
, int irq
, int cpu
,
132 uint32_t *field
, bool to_kernel
);
134 /* synthetic translate function used for clear/set registers to completely
135 * clear a setting using a clear-register before setting the remaining bits
136 * using a set-register */
137 static void translate_clear(GICState
*s
, int irq
, int cpu
,
138 uint32_t *field
, bool to_kernel
)
143 /* does not make sense: qemu model doesn't use set/clear regs */
148 static void translate_group(GICState
*s
, int irq
, int cpu
,
149 uint32_t *field
, bool to_kernel
)
151 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
154 *field
= GIC_TEST_GROUP(irq
, cm
);
157 GIC_SET_GROUP(irq
, cm
);
162 static void translate_enabled(GICState
*s
, int irq
, int cpu
,
163 uint32_t *field
, bool to_kernel
)
165 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
168 *field
= GIC_TEST_ENABLED(irq
, cm
);
171 GIC_SET_ENABLED(irq
, cm
);
176 static void translate_pending(GICState
*s
, int irq
, int cpu
,
177 uint32_t *field
, bool to_kernel
)
179 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
182 *field
= gic_test_pending(s
, irq
, cm
);
185 GIC_SET_PENDING(irq
, cm
);
186 /* TODO: Capture is level-line is held high in the kernel */
191 static void translate_active(GICState
*s
, int irq
, int cpu
,
192 uint32_t *field
, bool to_kernel
)
194 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
197 *field
= GIC_TEST_ACTIVE(irq
, cm
);
200 GIC_SET_ACTIVE(irq
, cm
);
205 static void translate_trigger(GICState
*s
, int irq
, int cpu
,
206 uint32_t *field
, bool to_kernel
)
209 *field
= (GIC_TEST_EDGE_TRIGGER(irq
)) ? 0x2 : 0x0;
212 GIC_SET_EDGE_TRIGGER(irq
);
217 static void translate_priority(GICState
*s
, int irq
, int cpu
,
218 uint32_t *field
, bool to_kernel
)
221 *field
= GIC_GET_PRIORITY(irq
, cpu
) & 0xff;
223 gic_set_priority(s
, cpu
, irq
, *field
& 0xff, MEMTXATTRS_UNSPECIFIED
);
227 static void translate_targets(GICState
*s
, int irq
, int cpu
,
228 uint32_t *field
, bool to_kernel
)
231 *field
= s
->irq_target
[irq
] & 0xff;
233 s
->irq_target
[irq
] = *field
& 0xff;
237 static void translate_sgisource(GICState
*s
, int irq
, int cpu
,
238 uint32_t *field
, bool to_kernel
)
241 *field
= s
->sgi_pending
[irq
][cpu
] & 0xff;
243 s
->sgi_pending
[irq
][cpu
] = *field
& 0xff;
247 /* Read a register group from the kernel VGIC */
248 static void kvm_dist_get(GICState
*s
, uint32_t offset
, int width
,
249 int maxirq
, vgic_translate_fn translate_fn
)
256 int regsz
= 32 / width
; /* irqs per kernel register */
259 for_each_irq_reg(i
, maxirq
, width
) {
262 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
263 kvm_gicd_access(s
, offset
, cpu
, ®
, false);
264 for (j
= 0; j
< regsz
; j
++) {
265 field
= extract32(reg
, j
* width
, width
);
266 translate_fn(s
, irq
+ j
, cpu
, &field
, false);
275 /* Write a register group to the kernel VGIC */
276 static void kvm_dist_put(GICState
*s
, uint32_t offset
, int width
,
277 int maxirq
, vgic_translate_fn translate_fn
)
284 int regsz
= 32 / width
; /* irqs per kernel register */
287 for_each_irq_reg(i
, maxirq
, width
) {
290 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
292 for (j
= 0; j
< regsz
; j
++) {
293 translate_fn(s
, irq
+ j
, cpu
, &field
, true);
294 reg
= deposit32(reg
, j
* width
, width
, field
);
296 kvm_gicd_access(s
, offset
, cpu
, ®
, true);
304 static void kvm_arm_gic_put(GICState
*s
)
312 /* Note: We do the restore in a slightly different order than the save
313 * (where the order doesn't matter and is simply ordered according to the
314 * register offset values */
316 /*****************************************************************
320 /* s->ctlr -> GICD_CTLR */
322 kvm_gicd_access(s
, 0x0, 0, ®
, true);
324 /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
325 kvm_gicd_access(s
, 0x4, 0, ®
, false);
326 num_irq
= ((reg
& 0x1f) + 1) * 32;
327 num_cpu
= ((reg
& 0xe0) >> 5) + 1;
329 if (num_irq
< s
->num_irq
) {
330 fprintf(stderr
, "Restoring %u IRQs, but kernel supports max %d\n",
331 s
->num_irq
, num_irq
);
333 } else if (num_cpu
!= s
->num_cpu
) {
334 fprintf(stderr
, "Restoring %u CPU interfaces, kernel only has %d\n",
335 s
->num_cpu
, num_cpu
);
336 /* Did we not create the VCPUs in the kernel yet? */
340 /* TODO: Consider checking compatibility with the IIDR ? */
342 /* irq_state[n].enabled -> GICD_ISENABLERn */
343 kvm_dist_put(s
, 0x180, 1, s
->num_irq
, translate_clear
);
344 kvm_dist_put(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
346 /* irq_state[n].group -> GICD_IGROUPRn */
347 kvm_dist_put(s
, 0x80, 1, s
->num_irq
, translate_group
);
349 /* s->irq_target[irq] -> GICD_ITARGETSRn
350 * (restore targets before pending to ensure the pending state is set on
351 * the appropriate CPU interfaces in the kernel) */
352 kvm_dist_put(s
, 0x800, 8, s
->num_irq
, translate_targets
);
354 /* irq_state[n].trigger -> GICD_ICFGRn
355 * (restore configuration registers before pending IRQs so we treat
356 * level/edge correctly) */
357 kvm_dist_put(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
359 /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
360 kvm_dist_put(s
, 0x280, 1, s
->num_irq
, translate_clear
);
361 kvm_dist_put(s
, 0x200, 1, s
->num_irq
, translate_pending
);
363 /* irq_state[n].active -> GICD_ISACTIVERn */
364 kvm_dist_put(s
, 0x380, 1, s
->num_irq
, translate_clear
);
365 kvm_dist_put(s
, 0x300, 1, s
->num_irq
, translate_active
);
368 /* s->priorityX[irq] -> ICD_IPRIORITYRn */
369 kvm_dist_put(s
, 0x400, 8, s
->num_irq
, translate_priority
);
371 /* s->sgi_pending -> ICD_CPENDSGIRn */
372 kvm_dist_put(s
, 0xf10, 8, GIC_NR_SGIS
, translate_clear
);
373 kvm_dist_put(s
, 0xf20, 8, GIC_NR_SGIS
, translate_sgisource
);
376 /*****************************************************************
377 * CPU Interface(s) State
380 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
381 /* s->cpu_ctlr[cpu] -> GICC_CTLR */
382 reg
= s
->cpu_ctlr
[cpu
];
383 kvm_gicc_access(s
, 0x00, cpu
, ®
, true);
385 /* s->priority_mask[cpu] -> GICC_PMR */
386 reg
= (s
->priority_mask
[cpu
] & 0xff);
387 kvm_gicc_access(s
, 0x04, cpu
, ®
, true);
389 /* s->bpr[cpu] -> GICC_BPR */
390 reg
= (s
->bpr
[cpu
] & 0x7);
391 kvm_gicc_access(s
, 0x08, cpu
, ®
, true);
393 /* s->abpr[cpu] -> GICC_ABPR */
394 reg
= (s
->abpr
[cpu
] & 0x7);
395 kvm_gicc_access(s
, 0x1c, cpu
, ®
, true);
397 /* s->apr[n][cpu] -> GICC_APRn */
398 for (i
= 0; i
< 4; i
++) {
399 reg
= s
->apr
[i
][cpu
];
400 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, true);
405 static void kvm_arm_gic_get(GICState
*s
)
411 /*****************************************************************
415 /* GICD_CTLR -> s->ctlr */
416 kvm_gicd_access(s
, 0x0, 0, ®
, false);
419 /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
420 kvm_gicd_access(s
, 0x4, 0, ®
, false);
421 s
->num_irq
= ((reg
& 0x1f) + 1) * 32;
422 s
->num_cpu
= ((reg
& 0xe0) >> 5) + 1;
424 if (s
->num_irq
> GIC_MAXIRQ
) {
425 fprintf(stderr
, "Too many IRQs reported from the kernel: %d\n",
431 kvm_gicd_access(s
, 0x8, 0, ®
, false);
433 /* Clear all the IRQ settings */
434 for (i
= 0; i
< s
->num_irq
; i
++) {
435 memset(&s
->irq_state
[i
], 0, sizeof(s
->irq_state
[0]));
438 /* GICD_IGROUPRn -> irq_state[n].group */
439 kvm_dist_get(s
, 0x80, 1, s
->num_irq
, translate_group
);
441 /* GICD_ISENABLERn -> irq_state[n].enabled */
442 kvm_dist_get(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
444 /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
445 kvm_dist_get(s
, 0x200, 1, s
->num_irq
, translate_pending
);
447 /* GICD_ISACTIVERn -> irq_state[n].active */
448 kvm_dist_get(s
, 0x300, 1, s
->num_irq
, translate_active
);
450 /* GICD_ICFRn -> irq_state[n].trigger */
451 kvm_dist_get(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
453 /* GICD_IPRIORITYRn -> s->priorityX[irq] */
454 kvm_dist_get(s
, 0x400, 8, s
->num_irq
, translate_priority
);
456 /* GICD_ITARGETSRn -> s->irq_target[irq] */
457 kvm_dist_get(s
, 0x800, 8, s
->num_irq
, translate_targets
);
459 /* GICD_CPENDSGIRn -> s->sgi_pending */
460 kvm_dist_get(s
, 0xf10, 8, GIC_NR_SGIS
, translate_sgisource
);
463 /*****************************************************************
464 * CPU Interface(s) State
467 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
468 /* GICC_CTLR -> s->cpu_ctlr[cpu] */
469 kvm_gicc_access(s
, 0x00, cpu
, ®
, false);
470 s
->cpu_ctlr
[cpu
] = reg
;
472 /* GICC_PMR -> s->priority_mask[cpu] */
473 kvm_gicc_access(s
, 0x04, cpu
, ®
, false);
474 s
->priority_mask
[cpu
] = (reg
& 0xff);
476 /* GICC_BPR -> s->bpr[cpu] */
477 kvm_gicc_access(s
, 0x08, cpu
, ®
, false);
478 s
->bpr
[cpu
] = (reg
& 0x7);
480 /* GICC_ABPR -> s->abpr[cpu] */
481 kvm_gicc_access(s
, 0x1c, cpu
, ®
, false);
482 s
->abpr
[cpu
] = (reg
& 0x7);
484 /* GICC_APRn -> s->apr[n][cpu] */
485 for (i
= 0; i
< 4; i
++) {
486 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, false);
487 s
->apr
[i
][cpu
] = reg
;
492 static void kvm_arm_gic_reset(DeviceState
*dev
)
494 GICState
*s
= ARM_GIC_COMMON(dev
);
495 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
497 kgc
->parent_reset(dev
);
499 if (kvm_arm_gic_can_save_restore(s
)) {
504 static void kvm_arm_gic_realize(DeviceState
*dev
, Error
**errp
)
507 GICState
*s
= KVM_ARM_GIC(dev
);
508 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
509 Error
*local_err
= NULL
;
512 kgc
->parent_realize(dev
, &local_err
);
514 error_propagate(errp
, local_err
);
518 if (s
->security_extn
) {
519 error_setg(errp
, "the in-kernel VGIC does not implement the "
520 "security extensions");
524 gic_init_irqs_and_mmio(s
, kvm_arm_gicv2_set_irq
, NULL
);
526 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; i
++) {
527 qemu_irq irq
= qdev_get_gpio_in(dev
, i
);
528 kvm_irqchip_set_qemuirq_gsi(kvm_state
, irq
, i
);
531 /* Try to create the device via the device control API */
533 ret
= kvm_create_device(kvm_state
, KVM_DEV_TYPE_ARM_VGIC_V2
, false);
537 /* Newstyle API is used, we may have attributes */
538 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0)) {
539 uint32_t numirqs
= s
->num_irq
;
540 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0,
543 /* Tell the kernel to complete VGIC initialization now */
544 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
545 KVM_DEV_ARM_VGIC_CTRL_INIT
)) {
546 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
547 KVM_DEV_ARM_VGIC_CTRL_INIT
, NULL
, true);
549 } else if (ret
!= -ENODEV
&& ret
!= -ENOTSUP
) {
550 error_setg_errno(errp
, -ret
, "error creating in-kernel VGIC");
555 kvm_arm_register_device(&s
->iomem
,
556 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
557 | KVM_VGIC_V2_ADDR_TYPE_DIST
,
558 KVM_DEV_ARM_VGIC_GRP_ADDR
,
559 KVM_VGIC_V2_ADDR_TYPE_DIST
,
561 /* CPU interface for current core. Unlike arm_gic, we don't
562 * provide the "interface for core #N" memory regions, because
563 * cores with a VGIC don't have those.
565 kvm_arm_register_device(&s
->cpuiomem
[0],
566 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
567 | KVM_VGIC_V2_ADDR_TYPE_CPU
,
568 KVM_DEV_ARM_VGIC_GRP_ADDR
,
569 KVM_VGIC_V2_ADDR_TYPE_CPU
,
572 if (!kvm_arm_gic_can_save_restore(s
)) {
573 error_setg(&s
->migration_blocker
, "This operating system kernel does "
574 "not support vGICv2 migration");
575 migrate_add_blocker(s
->migration_blocker
);
579 static void kvm_arm_gic_class_init(ObjectClass
*klass
, void *data
)
581 DeviceClass
*dc
= DEVICE_CLASS(klass
);
582 ARMGICCommonClass
*agcc
= ARM_GIC_COMMON_CLASS(klass
);
583 KVMARMGICClass
*kgc
= KVM_ARM_GIC_CLASS(klass
);
585 agcc
->pre_save
= kvm_arm_gic_get
;
586 agcc
->post_load
= kvm_arm_gic_put
;
587 kgc
->parent_realize
= dc
->realize
;
588 kgc
->parent_reset
= dc
->reset
;
589 dc
->realize
= kvm_arm_gic_realize
;
590 dc
->reset
= kvm_arm_gic_reset
;
593 static const TypeInfo kvm_arm_gic_info
= {
594 .name
= TYPE_KVM_ARM_GIC
,
595 .parent
= TYPE_ARM_GIC_COMMON
,
596 .instance_size
= sizeof(GICState
),
597 .class_init
= kvm_arm_gic_class_init
,
598 .class_size
= sizeof(KVMARMGICClass
),
601 static void kvm_arm_gic_register_types(void)
603 type_register_static(&kvm_arm_gic_info
);
606 type_init(kvm_arm_gic_register_types
)